ARMAsmParser.cpp revision a1c7367a5bed459acc88e3ea2a482b4b5dac942a 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringSwitch.h"
34#include "llvm/ADT/Twine.h"
35
36using namespace llvm;
37
38namespace {
39
40class ARMOperand;
41
42enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
43
44class ARMAsmParser : public MCTargetAsmParser {
45  MCSubtargetInfo &STI;
46  MCAsmParser &Parser;
47  const MCRegisterInfo *MRI;
48
49  // Map of register aliases registers via the .req directive.
50  StringMap<unsigned> RegisterReqs;
51
52  struct {
53    ARMCC::CondCodes Cond;    // Condition for IT block.
54    unsigned Mask:4;          // Condition mask for instructions.
55                              // Starting at first 1 (from lsb).
56                              //   '1'  condition as indicated in IT.
57                              //   '0'  inverse of condition (else).
58                              // Count of instructions in IT block is
59                              // 4 - trailingzeroes(mask)
60
61    bool FirstCond;           // Explicit flag for when we're parsing the
62                              // First instruction in the IT block. It's
63                              // implied in the mask, so needs special
64                              // handling.
65
66    unsigned CurPosition;     // Current position in parsing of IT
67                              // block. In range [0,3]. Initialized
68                              // according to count of instructions in block.
69                              // ~0U if no active IT block.
70  } ITState;
71  bool inITBlock() { return ITState.CurPosition != ~0U;}
72  void forwardITPosition() {
73    if (!inITBlock()) return;
74    // Move to the next instruction in the IT block, if there is one. If not,
75    // mark the block as done.
76    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
77    if (++ITState.CurPosition == 5 - TZ)
78      ITState.CurPosition = ~0U; // Done with the IT block after this.
79  }
80
81
82  MCAsmParser &getParser() const { return Parser; }
83  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
84
85  bool Warning(SMLoc L, const Twine &Msg,
86               ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
87    return Parser.Warning(L, Msg, Ranges);
88  }
89  bool Error(SMLoc L, const Twine &Msg,
90             ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
91    return Parser.Error(L, Msg, Ranges);
92  }
93
94  int tryParseRegister();
95  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
96  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
97  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
98  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
99  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
100  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
101  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
102                              unsigned &ShiftAmount);
103  bool parseDirectiveWord(unsigned Size, SMLoc L);
104  bool parseDirectiveThumb(SMLoc L);
105  bool parseDirectiveARM(SMLoc L);
106  bool parseDirectiveThumbFunc(SMLoc L);
107  bool parseDirectiveCode(SMLoc L);
108  bool parseDirectiveSyntax(SMLoc L);
109  bool parseDirectiveReq(StringRef Name, SMLoc L);
110  bool parseDirectiveUnreq(SMLoc L);
111  bool parseDirectiveArch(SMLoc L);
112  bool parseDirectiveEabiAttr(SMLoc L);
113
114  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
115                          bool &CarrySetting, unsigned &ProcessorIMod,
116                          StringRef &ITMask);
117  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
118                             bool &CanAcceptPredicationCode);
119
120  bool isThumb() const {
121    // FIXME: Can tablegen auto-generate this?
122    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
123  }
124  bool isThumbOne() const {
125    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
126  }
127  bool isThumbTwo() const {
128    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
129  }
130  bool hasV6Ops() const {
131    return STI.getFeatureBits() & ARM::HasV6Ops;
132  }
133  bool hasV7Ops() const {
134    return STI.getFeatureBits() & ARM::HasV7Ops;
135  }
136  void SwitchMode() {
137    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
138    setAvailableFeatures(FB);
139  }
140  bool isMClass() const {
141    return STI.getFeatureBits() & ARM::FeatureMClass;
142  }
143
144  /// @name Auto-generated Match Functions
145  /// {
146
147#define GET_ASSEMBLER_HEADER
148#include "ARMGenAsmMatcher.inc"
149
150  /// }
151
152  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
153  OperandMatchResultTy parseCoprocNumOperand(
154    SmallVectorImpl<MCParsedAsmOperand*>&);
155  OperandMatchResultTy parseCoprocRegOperand(
156    SmallVectorImpl<MCParsedAsmOperand*>&);
157  OperandMatchResultTy parseCoprocOptionOperand(
158    SmallVectorImpl<MCParsedAsmOperand*>&);
159  OperandMatchResultTy parseMemBarrierOptOperand(
160    SmallVectorImpl<MCParsedAsmOperand*>&);
161  OperandMatchResultTy parseProcIFlagsOperand(
162    SmallVectorImpl<MCParsedAsmOperand*>&);
163  OperandMatchResultTy parseMSRMaskOperand(
164    SmallVectorImpl<MCParsedAsmOperand*>&);
165  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
166                                   StringRef Op, int Low, int High);
167  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
168    return parsePKHImm(O, "lsl", 0, 31);
169  }
170  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171    return parsePKHImm(O, "asr", 1, 32);
172  }
173  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
174  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
175  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
176  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
177  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
178  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
179  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
180  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
181  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
182
183  // Asm Match Converter Methods
184  bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
185                    const SmallVectorImpl<MCParsedAsmOperand*> &);
186  bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
187                    const SmallVectorImpl<MCParsedAsmOperand*> &);
188  bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
189                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
190  bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
191                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
192  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
193                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
194  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
195                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
196  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
197                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
198  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
199                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
200  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
201                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
202  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
203                             const SmallVectorImpl<MCParsedAsmOperand*> &);
204  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
205                             const SmallVectorImpl<MCParsedAsmOperand*> &);
206  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
207                             const SmallVectorImpl<MCParsedAsmOperand*> &);
208  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
209                             const SmallVectorImpl<MCParsedAsmOperand*> &);
210  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
211                  const SmallVectorImpl<MCParsedAsmOperand*> &);
212  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
213                  const SmallVectorImpl<MCParsedAsmOperand*> &);
214  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
215                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
216  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
217                        const SmallVectorImpl<MCParsedAsmOperand*> &);
218  bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
219                     const SmallVectorImpl<MCParsedAsmOperand*> &);
220  bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
221                        const SmallVectorImpl<MCParsedAsmOperand*> &);
222  bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
223                     const SmallVectorImpl<MCParsedAsmOperand*> &);
224  bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
225                        const SmallVectorImpl<MCParsedAsmOperand*> &);
226
227  bool validateInstruction(MCInst &Inst,
228                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
229  bool processInstruction(MCInst &Inst,
230                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
231  bool shouldOmitCCOutOperand(StringRef Mnemonic,
232                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
233
234public:
235  enum ARMMatchResultTy {
236    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
237    Match_RequiresNotITBlock,
238    Match_RequiresV6,
239    Match_RequiresThumb2
240  };
241
242  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
243    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
244    MCAsmParserExtension::Initialize(_Parser);
245
246    // Cache the MCRegisterInfo.
247    MRI = &getContext().getRegisterInfo();
248
249    // Initialize the set of available features.
250    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
251
252    // Not in an ITBlock to start with.
253    ITState.CurPosition = ~0U;
254  }
255
256  // Implementation of the MCTargetAsmParser interface:
257  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
258  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
259                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
260  bool ParseDirective(AsmToken DirectiveID);
261
262  unsigned checkTargetMatchPredicate(MCInst &Inst);
263
264  bool MatchAndEmitInstruction(SMLoc IDLoc,
265                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
266                               MCStreamer &Out);
267};
268} // end anonymous namespace
269
270namespace {
271
272/// ARMOperand - Instances of this class represent a parsed ARM machine
273/// instruction.
274class ARMOperand : public MCParsedAsmOperand {
275  enum KindTy {
276    k_CondCode,
277    k_CCOut,
278    k_ITCondMask,
279    k_CoprocNum,
280    k_CoprocReg,
281    k_CoprocOption,
282    k_Immediate,
283    k_MemBarrierOpt,
284    k_Memory,
285    k_PostIndexRegister,
286    k_MSRMask,
287    k_ProcIFlags,
288    k_VectorIndex,
289    k_Register,
290    k_RegisterList,
291    k_DPRRegisterList,
292    k_SPRRegisterList,
293    k_VectorList,
294    k_VectorListAllLanes,
295    k_VectorListIndexed,
296    k_ShiftedRegister,
297    k_ShiftedImmediate,
298    k_ShifterImmediate,
299    k_RotateImmediate,
300    k_BitfieldDescriptor,
301    k_Token
302  } Kind;
303
304  SMLoc StartLoc, EndLoc;
305  SmallVector<unsigned, 8> Registers;
306
307  union {
308    struct {
309      ARMCC::CondCodes Val;
310    } CC;
311
312    struct {
313      unsigned Val;
314    } Cop;
315
316    struct {
317      unsigned Val;
318    } CoprocOption;
319
320    struct {
321      unsigned Mask:4;
322    } ITMask;
323
324    struct {
325      ARM_MB::MemBOpt Val;
326    } MBOpt;
327
328    struct {
329      ARM_PROC::IFlags Val;
330    } IFlags;
331
332    struct {
333      unsigned Val;
334    } MMask;
335
336    struct {
337      const char *Data;
338      unsigned Length;
339    } Tok;
340
341    struct {
342      unsigned RegNum;
343    } Reg;
344
345    // A vector register list is a sequential list of 1 to 4 registers.
346    struct {
347      unsigned RegNum;
348      unsigned Count;
349      unsigned LaneIndex;
350      bool isDoubleSpaced;
351    } VectorList;
352
353    struct {
354      unsigned Val;
355    } VectorIndex;
356
357    struct {
358      const MCExpr *Val;
359    } Imm;
360
361    /// Combined record for all forms of ARM address expressions.
362    struct {
363      unsigned BaseRegNum;
364      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
365      // was specified.
366      const MCConstantExpr *OffsetImm;  // Offset immediate value
367      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
368      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
369      unsigned ShiftImm;        // shift for OffsetReg.
370      unsigned Alignment;       // 0 = no alignment specified
371                                // n = alignment in bytes (2, 4, 8, 16, or 32)
372      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
373    } Memory;
374
375    struct {
376      unsigned RegNum;
377      bool isAdd;
378      ARM_AM::ShiftOpc ShiftTy;
379      unsigned ShiftImm;
380    } PostIdxReg;
381
382    struct {
383      bool isASR;
384      unsigned Imm;
385    } ShifterImm;
386    struct {
387      ARM_AM::ShiftOpc ShiftTy;
388      unsigned SrcReg;
389      unsigned ShiftReg;
390      unsigned ShiftImm;
391    } RegShiftedReg;
392    struct {
393      ARM_AM::ShiftOpc ShiftTy;
394      unsigned SrcReg;
395      unsigned ShiftImm;
396    } RegShiftedImm;
397    struct {
398      unsigned Imm;
399    } RotImm;
400    struct {
401      unsigned LSB;
402      unsigned Width;
403    } Bitfield;
404  };
405
406  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
407public:
408  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
409    Kind = o.Kind;
410    StartLoc = o.StartLoc;
411    EndLoc = o.EndLoc;
412    switch (Kind) {
413    case k_CondCode:
414      CC = o.CC;
415      break;
416    case k_ITCondMask:
417      ITMask = o.ITMask;
418      break;
419    case k_Token:
420      Tok = o.Tok;
421      break;
422    case k_CCOut:
423    case k_Register:
424      Reg = o.Reg;
425      break;
426    case k_RegisterList:
427    case k_DPRRegisterList:
428    case k_SPRRegisterList:
429      Registers = o.Registers;
430      break;
431    case k_VectorList:
432    case k_VectorListAllLanes:
433    case k_VectorListIndexed:
434      VectorList = o.VectorList;
435      break;
436    case k_CoprocNum:
437    case k_CoprocReg:
438      Cop = o.Cop;
439      break;
440    case k_CoprocOption:
441      CoprocOption = o.CoprocOption;
442      break;
443    case k_Immediate:
444      Imm = o.Imm;
445      break;
446    case k_MemBarrierOpt:
447      MBOpt = o.MBOpt;
448      break;
449    case k_Memory:
450      Memory = o.Memory;
451      break;
452    case k_PostIndexRegister:
453      PostIdxReg = o.PostIdxReg;
454      break;
455    case k_MSRMask:
456      MMask = o.MMask;
457      break;
458    case k_ProcIFlags:
459      IFlags = o.IFlags;
460      break;
461    case k_ShifterImmediate:
462      ShifterImm = o.ShifterImm;
463      break;
464    case k_ShiftedRegister:
465      RegShiftedReg = o.RegShiftedReg;
466      break;
467    case k_ShiftedImmediate:
468      RegShiftedImm = o.RegShiftedImm;
469      break;
470    case k_RotateImmediate:
471      RotImm = o.RotImm;
472      break;
473    case k_BitfieldDescriptor:
474      Bitfield = o.Bitfield;
475      break;
476    case k_VectorIndex:
477      VectorIndex = o.VectorIndex;
478      break;
479    }
480  }
481
482  /// getStartLoc - Get the location of the first token of this operand.
483  SMLoc getStartLoc() const { return StartLoc; }
484  /// getEndLoc - Get the location of the last token of this operand.
485  SMLoc getEndLoc() const { return EndLoc; }
486
487  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
488
489  ARMCC::CondCodes getCondCode() const {
490    assert(Kind == k_CondCode && "Invalid access!");
491    return CC.Val;
492  }
493
494  unsigned getCoproc() const {
495    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
496    return Cop.Val;
497  }
498
499  StringRef getToken() const {
500    assert(Kind == k_Token && "Invalid access!");
501    return StringRef(Tok.Data, Tok.Length);
502  }
503
504  unsigned getReg() const {
505    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
506    return Reg.RegNum;
507  }
508
509  const SmallVectorImpl<unsigned> &getRegList() const {
510    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
511            Kind == k_SPRRegisterList) && "Invalid access!");
512    return Registers;
513  }
514
515  const MCExpr *getImm() const {
516    assert(isImm() && "Invalid access!");
517    return Imm.Val;
518  }
519
520  unsigned getVectorIndex() const {
521    assert(Kind == k_VectorIndex && "Invalid access!");
522    return VectorIndex.Val;
523  }
524
525  ARM_MB::MemBOpt getMemBarrierOpt() const {
526    assert(Kind == k_MemBarrierOpt && "Invalid access!");
527    return MBOpt.Val;
528  }
529
530  ARM_PROC::IFlags getProcIFlags() const {
531    assert(Kind == k_ProcIFlags && "Invalid access!");
532    return IFlags.Val;
533  }
534
535  unsigned getMSRMask() const {
536    assert(Kind == k_MSRMask && "Invalid access!");
537    return MMask.Val;
538  }
539
540  bool isCoprocNum() const { return Kind == k_CoprocNum; }
541  bool isCoprocReg() const { return Kind == k_CoprocReg; }
542  bool isCoprocOption() const { return Kind == k_CoprocOption; }
543  bool isCondCode() const { return Kind == k_CondCode; }
544  bool isCCOut() const { return Kind == k_CCOut; }
545  bool isITMask() const { return Kind == k_ITCondMask; }
546  bool isITCondCode() const { return Kind == k_CondCode; }
547  bool isImm() const { return Kind == k_Immediate; }
548  bool isFPImm() const {
549    if (!isImm()) return false;
550    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
551    if (!CE) return false;
552    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
553    return Val != -1;
554  }
555  bool isFBits16() const {
556    if (!isImm()) return false;
557    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
558    if (!CE) return false;
559    int64_t Value = CE->getValue();
560    return Value >= 0 && Value <= 16;
561  }
562  bool isFBits32() const {
563    if (!isImm()) return false;
564    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
565    if (!CE) return false;
566    int64_t Value = CE->getValue();
567    return Value >= 1 && Value <= 32;
568  }
569  bool isImm8s4() const {
570    if (!isImm()) return false;
571    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
572    if (!CE) return false;
573    int64_t Value = CE->getValue();
574    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
575  }
576  bool isImm0_1020s4() const {
577    if (!isImm()) return false;
578    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
579    if (!CE) return false;
580    int64_t Value = CE->getValue();
581    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
582  }
583  bool isImm0_508s4() const {
584    if (!isImm()) return false;
585    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
586    if (!CE) return false;
587    int64_t Value = CE->getValue();
588    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
589  }
590  bool isImm0_508s4Neg() const {
591    if (!isImm()) return false;
592    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
593    if (!CE) return false;
594    int64_t Value = -CE->getValue();
595    // explicitly exclude zero. we want that to use the normal 0_508 version.
596    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
597  }
598  bool isImm0_255() const {
599    if (!isImm()) return false;
600    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
601    if (!CE) return false;
602    int64_t Value = CE->getValue();
603    return Value >= 0 && Value < 256;
604  }
605  bool isImm0_4095() const {
606    if (!isImm()) return false;
607    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
608    if (!CE) return false;
609    int64_t Value = CE->getValue();
610    return Value >= 0 && Value < 4096;
611  }
612  bool isImm0_4095Neg() const {
613    if (!isImm()) return false;
614    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
615    if (!CE) return false;
616    int64_t Value = -CE->getValue();
617    return Value > 0 && Value < 4096;
618  }
619  bool isImm0_1() const {
620    if (!isImm()) return false;
621    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
622    if (!CE) return false;
623    int64_t Value = CE->getValue();
624    return Value >= 0 && Value < 2;
625  }
626  bool isImm0_3() const {
627    if (!isImm()) return false;
628    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
629    if (!CE) return false;
630    int64_t Value = CE->getValue();
631    return Value >= 0 && Value < 4;
632  }
633  bool isImm0_7() const {
634    if (!isImm()) return false;
635    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
636    if (!CE) return false;
637    int64_t Value = CE->getValue();
638    return Value >= 0 && Value < 8;
639  }
640  bool isImm0_15() const {
641    if (!isImm()) return false;
642    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
643    if (!CE) return false;
644    int64_t Value = CE->getValue();
645    return Value >= 0 && Value < 16;
646  }
647  bool isImm0_31() const {
648    if (!isImm()) return false;
649    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
650    if (!CE) return false;
651    int64_t Value = CE->getValue();
652    return Value >= 0 && Value < 32;
653  }
654  bool isImm0_63() const {
655    if (!isImm()) return false;
656    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
657    if (!CE) return false;
658    int64_t Value = CE->getValue();
659    return Value >= 0 && Value < 64;
660  }
661  bool isImm8() const {
662    if (!isImm()) return false;
663    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
664    if (!CE) return false;
665    int64_t Value = CE->getValue();
666    return Value == 8;
667  }
668  bool isImm16() const {
669    if (!isImm()) return false;
670    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
671    if (!CE) return false;
672    int64_t Value = CE->getValue();
673    return Value == 16;
674  }
675  bool isImm32() const {
676    if (!isImm()) return false;
677    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
678    if (!CE) return false;
679    int64_t Value = CE->getValue();
680    return Value == 32;
681  }
682  bool isShrImm8() const {
683    if (!isImm()) return false;
684    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
685    if (!CE) return false;
686    int64_t Value = CE->getValue();
687    return Value > 0 && Value <= 8;
688  }
689  bool isShrImm16() const {
690    if (!isImm()) return false;
691    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
692    if (!CE) return false;
693    int64_t Value = CE->getValue();
694    return Value > 0 && Value <= 16;
695  }
696  bool isShrImm32() const {
697    if (!isImm()) return false;
698    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
699    if (!CE) return false;
700    int64_t Value = CE->getValue();
701    return Value > 0 && Value <= 32;
702  }
703  bool isShrImm64() const {
704    if (!isImm()) return false;
705    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
706    if (!CE) return false;
707    int64_t Value = CE->getValue();
708    return Value > 0 && Value <= 64;
709  }
710  bool isImm1_7() const {
711    if (!isImm()) return false;
712    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
713    if (!CE) return false;
714    int64_t Value = CE->getValue();
715    return Value > 0 && Value < 8;
716  }
717  bool isImm1_15() const {
718    if (!isImm()) return false;
719    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
720    if (!CE) return false;
721    int64_t Value = CE->getValue();
722    return Value > 0 && Value < 16;
723  }
724  bool isImm1_31() const {
725    if (!isImm()) return false;
726    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
727    if (!CE) return false;
728    int64_t Value = CE->getValue();
729    return Value > 0 && Value < 32;
730  }
731  bool isImm1_16() const {
732    if (!isImm()) return false;
733    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
734    if (!CE) return false;
735    int64_t Value = CE->getValue();
736    return Value > 0 && Value < 17;
737  }
738  bool isImm1_32() const {
739    if (!isImm()) return false;
740    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
741    if (!CE) return false;
742    int64_t Value = CE->getValue();
743    return Value > 0 && Value < 33;
744  }
745  bool isImm0_32() const {
746    if (!isImm()) return false;
747    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748    if (!CE) return false;
749    int64_t Value = CE->getValue();
750    return Value >= 0 && Value < 33;
751  }
752  bool isImm0_65535() const {
753    if (!isImm()) return false;
754    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
755    if (!CE) return false;
756    int64_t Value = CE->getValue();
757    return Value >= 0 && Value < 65536;
758  }
759  bool isImm0_65535Expr() const {
760    if (!isImm()) return false;
761    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762    // If it's not a constant expression, it'll generate a fixup and be
763    // handled later.
764    if (!CE) return true;
765    int64_t Value = CE->getValue();
766    return Value >= 0 && Value < 65536;
767  }
768  bool isImm24bit() const {
769    if (!isImm()) return false;
770    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771    if (!CE) return false;
772    int64_t Value = CE->getValue();
773    return Value >= 0 && Value <= 0xffffff;
774  }
775  bool isImmThumbSR() const {
776    if (!isImm()) return false;
777    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
778    if (!CE) return false;
779    int64_t Value = CE->getValue();
780    return Value > 0 && Value < 33;
781  }
782  bool isPKHLSLImm() const {
783    if (!isImm()) return false;
784    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785    if (!CE) return false;
786    int64_t Value = CE->getValue();
787    return Value >= 0 && Value < 32;
788  }
789  bool isPKHASRImm() const {
790    if (!isImm()) return false;
791    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
792    if (!CE) return false;
793    int64_t Value = CE->getValue();
794    return Value > 0 && Value <= 32;
795  }
796  bool isARMSOImm() const {
797    if (!isImm()) return false;
798    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
799    if (!CE) return false;
800    int64_t Value = CE->getValue();
801    return ARM_AM::getSOImmVal(Value) != -1;
802  }
803  bool isARMSOImmNot() const {
804    if (!isImm()) return false;
805    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
806    if (!CE) return false;
807    int64_t Value = CE->getValue();
808    return ARM_AM::getSOImmVal(~Value) != -1;
809  }
810  bool isARMSOImmNeg() const {
811    if (!isImm()) return false;
812    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
813    if (!CE) return false;
814    int64_t Value = CE->getValue();
815    // Only use this when not representable as a plain so_imm.
816    return ARM_AM::getSOImmVal(Value) == -1 &&
817      ARM_AM::getSOImmVal(-Value) != -1;
818  }
819  bool isT2SOImm() const {
820    if (!isImm()) return false;
821    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
822    if (!CE) return false;
823    int64_t Value = CE->getValue();
824    return ARM_AM::getT2SOImmVal(Value) != -1;
825  }
826  bool isT2SOImmNot() const {
827    if (!isImm()) return false;
828    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
829    if (!CE) return false;
830    int64_t Value = CE->getValue();
831    return ARM_AM::getT2SOImmVal(~Value) != -1;
832  }
833  bool isT2SOImmNeg() const {
834    if (!isImm()) return false;
835    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
836    if (!CE) return false;
837    int64_t Value = CE->getValue();
838    // Only use this when not representable as a plain so_imm.
839    return ARM_AM::getT2SOImmVal(Value) == -1 &&
840      ARM_AM::getT2SOImmVal(-Value) != -1;
841  }
842  bool isSetEndImm() const {
843    if (!isImm()) return false;
844    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
845    if (!CE) return false;
846    int64_t Value = CE->getValue();
847    return Value == 1 || Value == 0;
848  }
849  bool isReg() const { return Kind == k_Register; }
850  bool isRegList() const { return Kind == k_RegisterList; }
851  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
852  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
853  bool isToken() const { return Kind == k_Token; }
854  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
855  bool isMemory() const { return Kind == k_Memory; }
856  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
857  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
858  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
859  bool isRotImm() const { return Kind == k_RotateImmediate; }
860  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
861  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
862  bool isPostIdxReg() const {
863    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
864  }
865  bool isMemNoOffset(bool alignOK = false) const {
866    if (!isMemory())
867      return false;
868    // No offset of any kind.
869    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
870     (alignOK || Memory.Alignment == 0);
871  }
872  bool isMemPCRelImm12() const {
873    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
874      return false;
875    // Base register must be PC.
876    if (Memory.BaseRegNum != ARM::PC)
877      return false;
878    // Immediate offset in range [-4095, 4095].
879    if (!Memory.OffsetImm) return true;
880    int64_t Val = Memory.OffsetImm->getValue();
881    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
882  }
883  bool isAlignedMemory() const {
884    return isMemNoOffset(true);
885  }
886  bool isAddrMode2() const {
887    if (!isMemory() || Memory.Alignment != 0) return false;
888    // Check for register offset.
889    if (Memory.OffsetRegNum) return true;
890    // Immediate offset in range [-4095, 4095].
891    if (!Memory.OffsetImm) return true;
892    int64_t Val = Memory.OffsetImm->getValue();
893    return Val > -4096 && Val < 4096;
894  }
895  bool isAM2OffsetImm() const {
896    if (!isImm()) return false;
897    // Immediate offset in range [-4095, 4095].
898    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
899    if (!CE) return false;
900    int64_t Val = CE->getValue();
901    return Val > -4096 && Val < 4096;
902  }
903  bool isAddrMode3() const {
904    // If we have an immediate that's not a constant, treat it as a label
905    // reference needing a fixup. If it is a constant, it's something else
906    // and we reject it.
907    if (isImm() && !isa<MCConstantExpr>(getImm()))
908      return true;
909    if (!isMemory() || Memory.Alignment != 0) return false;
910    // No shifts are legal for AM3.
911    if (Memory.ShiftType != ARM_AM::no_shift) return false;
912    // Check for register offset.
913    if (Memory.OffsetRegNum) return true;
914    // Immediate offset in range [-255, 255].
915    if (!Memory.OffsetImm) return true;
916    int64_t Val = Memory.OffsetImm->getValue();
917    // The #-0 offset is encoded as INT32_MIN, and we have to check
918    // for this too.
919    return (Val > -256 && Val < 256) || Val == INT32_MIN;
920  }
921  bool isAM3Offset() const {
922    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
923      return false;
924    if (Kind == k_PostIndexRegister)
925      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
926    // Immediate offset in range [-255, 255].
927    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
928    if (!CE) return false;
929    int64_t Val = CE->getValue();
930    // Special case, #-0 is INT32_MIN.
931    return (Val > -256 && Val < 256) || Val == INT32_MIN;
932  }
933  bool isAddrMode5() const {
934    // If we have an immediate that's not a constant, treat it as a label
935    // reference needing a fixup. If it is a constant, it's something else
936    // and we reject it.
937    if (isImm() && !isa<MCConstantExpr>(getImm()))
938      return true;
939    if (!isMemory() || Memory.Alignment != 0) return false;
940    // Check for register offset.
941    if (Memory.OffsetRegNum) return false;
942    // Immediate offset in range [-1020, 1020] and a multiple of 4.
943    if (!Memory.OffsetImm) return true;
944    int64_t Val = Memory.OffsetImm->getValue();
945    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
946      Val == INT32_MIN;
947  }
948  bool isMemTBB() const {
949    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
950        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
951      return false;
952    return true;
953  }
954  bool isMemTBH() const {
955    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
956        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
957        Memory.Alignment != 0 )
958      return false;
959    return true;
960  }
961  bool isMemRegOffset() const {
962    if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
963      return false;
964    return true;
965  }
966  bool isT2MemRegOffset() const {
967    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
968        Memory.Alignment != 0)
969      return false;
970    // Only lsl #{0, 1, 2, 3} allowed.
971    if (Memory.ShiftType == ARM_AM::no_shift)
972      return true;
973    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
974      return false;
975    return true;
976  }
977  bool isMemThumbRR() const {
978    // Thumb reg+reg addressing is simple. Just two registers, a base and
979    // an offset. No shifts, negations or any other complicating factors.
980    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
981        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
982      return false;
983    return isARMLowRegister(Memory.BaseRegNum) &&
984      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
985  }
986  bool isMemThumbRIs4() const {
987    if (!isMemory() || Memory.OffsetRegNum != 0 ||
988        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
989      return false;
990    // Immediate offset, multiple of 4 in range [0, 124].
991    if (!Memory.OffsetImm) return true;
992    int64_t Val = Memory.OffsetImm->getValue();
993    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
994  }
995  bool isMemThumbRIs2() const {
996    if (!isMemory() || Memory.OffsetRegNum != 0 ||
997        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
998      return false;
999    // Immediate offset, multiple of 4 in range [0, 62].
1000    if (!Memory.OffsetImm) return true;
1001    int64_t Val = Memory.OffsetImm->getValue();
1002    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1003  }
1004  bool isMemThumbRIs1() const {
1005    if (!isMemory() || Memory.OffsetRegNum != 0 ||
1006        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1007      return false;
1008    // Immediate offset in range [0, 31].
1009    if (!Memory.OffsetImm) return true;
1010    int64_t Val = Memory.OffsetImm->getValue();
1011    return Val >= 0 && Val <= 31;
1012  }
1013  bool isMemThumbSPI() const {
1014    if (!isMemory() || Memory.OffsetRegNum != 0 ||
1015        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1016      return false;
1017    // Immediate offset, multiple of 4 in range [0, 1020].
1018    if (!Memory.OffsetImm) return true;
1019    int64_t Val = Memory.OffsetImm->getValue();
1020    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1021  }
1022  bool isMemImm8s4Offset() const {
1023    // If we have an immediate that's not a constant, treat it as a label
1024    // reference needing a fixup. If it is a constant, it's something else
1025    // and we reject it.
1026    if (isImm() && !isa<MCConstantExpr>(getImm()))
1027      return true;
1028    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1029      return false;
1030    // Immediate offset a multiple of 4 in range [-1020, 1020].
1031    if (!Memory.OffsetImm) return true;
1032    int64_t Val = Memory.OffsetImm->getValue();
1033    return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
1034  }
1035  bool isMemImm0_1020s4Offset() const {
1036    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1037      return false;
1038    // Immediate offset a multiple of 4 in range [0, 1020].
1039    if (!Memory.OffsetImm) return true;
1040    int64_t Val = Memory.OffsetImm->getValue();
1041    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1042  }
1043  bool isMemImm8Offset() const {
1044    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1045      return false;
1046    // Base reg of PC isn't allowed for these encodings.
1047    if (Memory.BaseRegNum == ARM::PC) return false;
1048    // Immediate offset in range [-255, 255].
1049    if (!Memory.OffsetImm) return true;
1050    int64_t Val = Memory.OffsetImm->getValue();
1051    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1052  }
1053  bool isMemPosImm8Offset() const {
1054    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1055      return false;
1056    // Immediate offset in range [0, 255].
1057    if (!Memory.OffsetImm) return true;
1058    int64_t Val = Memory.OffsetImm->getValue();
1059    return Val >= 0 && Val < 256;
1060  }
1061  bool isMemNegImm8Offset() const {
1062    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1063      return false;
1064    // Base reg of PC isn't allowed for these encodings.
1065    if (Memory.BaseRegNum == ARM::PC) return false;
1066    // Immediate offset in range [-255, -1].
1067    if (!Memory.OffsetImm) return false;
1068    int64_t Val = Memory.OffsetImm->getValue();
1069    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1070  }
1071  bool isMemUImm12Offset() const {
1072    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1073      return false;
1074    // Immediate offset in range [0, 4095].
1075    if (!Memory.OffsetImm) return true;
1076    int64_t Val = Memory.OffsetImm->getValue();
1077    return (Val >= 0 && Val < 4096);
1078  }
1079  bool isMemImm12Offset() const {
1080    // If we have an immediate that's not a constant, treat it as a label
1081    // reference needing a fixup. If it is a constant, it's something else
1082    // and we reject it.
1083    if (isImm() && !isa<MCConstantExpr>(getImm()))
1084      return true;
1085
1086    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1087      return false;
1088    // Immediate offset in range [-4095, 4095].
1089    if (!Memory.OffsetImm) return true;
1090    int64_t Val = Memory.OffsetImm->getValue();
1091    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1092  }
1093  bool isPostIdxImm8() const {
1094    if (!isImm()) return false;
1095    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1096    if (!CE) return false;
1097    int64_t Val = CE->getValue();
1098    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1099  }
1100  bool isPostIdxImm8s4() const {
1101    if (!isImm()) return false;
1102    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1103    if (!CE) return false;
1104    int64_t Val = CE->getValue();
1105    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1106      (Val == INT32_MIN);
1107  }
1108
1109  bool isMSRMask() const { return Kind == k_MSRMask; }
1110  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1111
1112  // NEON operands.
1113  bool isSingleSpacedVectorList() const {
1114    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1115  }
1116  bool isDoubleSpacedVectorList() const {
1117    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1118  }
1119  bool isVecListOneD() const {
1120    if (!isSingleSpacedVectorList()) return false;
1121    return VectorList.Count == 1;
1122  }
1123
1124  bool isVecListDPair() const {
1125    if (!isSingleSpacedVectorList()) return false;
1126    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1127              .contains(VectorList.RegNum));
1128  }
1129
1130  bool isVecListThreeD() const {
1131    if (!isSingleSpacedVectorList()) return false;
1132    return VectorList.Count == 3;
1133  }
1134
1135  bool isVecListFourD() const {
1136    if (!isSingleSpacedVectorList()) return false;
1137    return VectorList.Count == 4;
1138  }
1139
1140  bool isVecListDPairSpaced() const {
1141    if (isSingleSpacedVectorList()) return false;
1142    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1143              .contains(VectorList.RegNum));
1144  }
1145
1146  bool isVecListThreeQ() const {
1147    if (!isDoubleSpacedVectorList()) return false;
1148    return VectorList.Count == 3;
1149  }
1150
1151  bool isVecListFourQ() const {
1152    if (!isDoubleSpacedVectorList()) return false;
1153    return VectorList.Count == 4;
1154  }
1155
1156  bool isSingleSpacedVectorAllLanes() const {
1157    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1158  }
1159  bool isDoubleSpacedVectorAllLanes() const {
1160    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1161  }
1162  bool isVecListOneDAllLanes() const {
1163    if (!isSingleSpacedVectorAllLanes()) return false;
1164    return VectorList.Count == 1;
1165  }
1166
1167  bool isVecListDPairAllLanes() const {
1168    if (!isSingleSpacedVectorAllLanes()) return false;
1169    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1170              .contains(VectorList.RegNum));
1171  }
1172
1173  bool isVecListDPairSpacedAllLanes() const {
1174    if (!isDoubleSpacedVectorAllLanes()) return false;
1175    return VectorList.Count == 2;
1176  }
1177
1178  bool isVecListThreeDAllLanes() const {
1179    if (!isSingleSpacedVectorAllLanes()) return false;
1180    return VectorList.Count == 3;
1181  }
1182
1183  bool isVecListThreeQAllLanes() const {
1184    if (!isDoubleSpacedVectorAllLanes()) return false;
1185    return VectorList.Count == 3;
1186  }
1187
1188  bool isVecListFourDAllLanes() const {
1189    if (!isSingleSpacedVectorAllLanes()) return false;
1190    return VectorList.Count == 4;
1191  }
1192
1193  bool isVecListFourQAllLanes() const {
1194    if (!isDoubleSpacedVectorAllLanes()) return false;
1195    return VectorList.Count == 4;
1196  }
1197
1198  bool isSingleSpacedVectorIndexed() const {
1199    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1200  }
1201  bool isDoubleSpacedVectorIndexed() const {
1202    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1203  }
1204  bool isVecListOneDByteIndexed() const {
1205    if (!isSingleSpacedVectorIndexed()) return false;
1206    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1207  }
1208
1209  bool isVecListOneDHWordIndexed() const {
1210    if (!isSingleSpacedVectorIndexed()) return false;
1211    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1212  }
1213
1214  bool isVecListOneDWordIndexed() const {
1215    if (!isSingleSpacedVectorIndexed()) return false;
1216    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1217  }
1218
1219  bool isVecListTwoDByteIndexed() const {
1220    if (!isSingleSpacedVectorIndexed()) return false;
1221    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1222  }
1223
1224  bool isVecListTwoDHWordIndexed() const {
1225    if (!isSingleSpacedVectorIndexed()) return false;
1226    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1227  }
1228
1229  bool isVecListTwoQWordIndexed() const {
1230    if (!isDoubleSpacedVectorIndexed()) return false;
1231    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1232  }
1233
1234  bool isVecListTwoQHWordIndexed() const {
1235    if (!isDoubleSpacedVectorIndexed()) return false;
1236    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1237  }
1238
1239  bool isVecListTwoDWordIndexed() const {
1240    if (!isSingleSpacedVectorIndexed()) return false;
1241    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1242  }
1243
1244  bool isVecListThreeDByteIndexed() const {
1245    if (!isSingleSpacedVectorIndexed()) return false;
1246    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1247  }
1248
1249  bool isVecListThreeDHWordIndexed() const {
1250    if (!isSingleSpacedVectorIndexed()) return false;
1251    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1252  }
1253
1254  bool isVecListThreeQWordIndexed() const {
1255    if (!isDoubleSpacedVectorIndexed()) return false;
1256    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1257  }
1258
1259  bool isVecListThreeQHWordIndexed() const {
1260    if (!isDoubleSpacedVectorIndexed()) return false;
1261    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1262  }
1263
1264  bool isVecListThreeDWordIndexed() const {
1265    if (!isSingleSpacedVectorIndexed()) return false;
1266    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1267  }
1268
1269  bool isVecListFourDByteIndexed() const {
1270    if (!isSingleSpacedVectorIndexed()) return false;
1271    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1272  }
1273
1274  bool isVecListFourDHWordIndexed() const {
1275    if (!isSingleSpacedVectorIndexed()) return false;
1276    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1277  }
1278
1279  bool isVecListFourQWordIndexed() const {
1280    if (!isDoubleSpacedVectorIndexed()) return false;
1281    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1282  }
1283
1284  bool isVecListFourQHWordIndexed() const {
1285    if (!isDoubleSpacedVectorIndexed()) return false;
1286    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1287  }
1288
1289  bool isVecListFourDWordIndexed() const {
1290    if (!isSingleSpacedVectorIndexed()) return false;
1291    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1292  }
1293
1294  bool isVectorIndex8() const {
1295    if (Kind != k_VectorIndex) return false;
1296    return VectorIndex.Val < 8;
1297  }
1298  bool isVectorIndex16() const {
1299    if (Kind != k_VectorIndex) return false;
1300    return VectorIndex.Val < 4;
1301  }
1302  bool isVectorIndex32() const {
1303    if (Kind != k_VectorIndex) return false;
1304    return VectorIndex.Val < 2;
1305  }
1306
1307  bool isNEONi8splat() const {
1308    if (!isImm()) return false;
1309    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1310    // Must be a constant.
1311    if (!CE) return false;
1312    int64_t Value = CE->getValue();
1313    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1314    // value.
1315    return Value >= 0 && Value < 256;
1316  }
1317
1318  bool isNEONi16splat() const {
1319    if (!isImm()) return false;
1320    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1321    // Must be a constant.
1322    if (!CE) return false;
1323    int64_t Value = CE->getValue();
1324    // i16 value in the range [0,255] or [0x0100, 0xff00]
1325    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1326  }
1327
1328  bool isNEONi32splat() const {
1329    if (!isImm()) return false;
1330    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1331    // Must be a constant.
1332    if (!CE) return false;
1333    int64_t Value = CE->getValue();
1334    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1335    return (Value >= 0 && Value < 256) ||
1336      (Value >= 0x0100 && Value <= 0xff00) ||
1337      (Value >= 0x010000 && Value <= 0xff0000) ||
1338      (Value >= 0x01000000 && Value <= 0xff000000);
1339  }
1340
1341  bool isNEONi32vmov() const {
1342    if (!isImm()) return false;
1343    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1344    // Must be a constant.
1345    if (!CE) return false;
1346    int64_t Value = CE->getValue();
1347    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1348    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1349    return (Value >= 0 && Value < 256) ||
1350      (Value >= 0x0100 && Value <= 0xff00) ||
1351      (Value >= 0x010000 && Value <= 0xff0000) ||
1352      (Value >= 0x01000000 && Value <= 0xff000000) ||
1353      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1354      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1355  }
1356  bool isNEONi32vmovNeg() const {
1357    if (!isImm()) return false;
1358    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1359    // Must be a constant.
1360    if (!CE) return false;
1361    int64_t Value = ~CE->getValue();
1362    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1363    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1364    return (Value >= 0 && Value < 256) ||
1365      (Value >= 0x0100 && Value <= 0xff00) ||
1366      (Value >= 0x010000 && Value <= 0xff0000) ||
1367      (Value >= 0x01000000 && Value <= 0xff000000) ||
1368      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1369      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1370  }
1371
1372  bool isNEONi64splat() const {
1373    if (!isImm()) return false;
1374    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1375    // Must be a constant.
1376    if (!CE) return false;
1377    uint64_t Value = CE->getValue();
1378    // i64 value with each byte being either 0 or 0xff.
1379    for (unsigned i = 0; i < 8; ++i)
1380      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1381    return true;
1382  }
1383
1384  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1385    // Add as immediates when possible.  Null MCExpr = 0.
1386    if (Expr == 0)
1387      Inst.addOperand(MCOperand::CreateImm(0));
1388    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1389      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1390    else
1391      Inst.addOperand(MCOperand::CreateExpr(Expr));
1392  }
1393
1394  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1395    assert(N == 2 && "Invalid number of operands!");
1396    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1397    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1398    Inst.addOperand(MCOperand::CreateReg(RegNum));
1399  }
1400
1401  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1402    assert(N == 1 && "Invalid number of operands!");
1403    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1404  }
1405
1406  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1407    assert(N == 1 && "Invalid number of operands!");
1408    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1409  }
1410
1411  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1412    assert(N == 1 && "Invalid number of operands!");
1413    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1414  }
1415
1416  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1417    assert(N == 1 && "Invalid number of operands!");
1418    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1419  }
1420
1421  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1422    assert(N == 1 && "Invalid number of operands!");
1423    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1424  }
1425
1426  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1427    assert(N == 1 && "Invalid number of operands!");
1428    Inst.addOperand(MCOperand::CreateReg(getReg()));
1429  }
1430
1431  void addRegOperands(MCInst &Inst, unsigned N) const {
1432    assert(N == 1 && "Invalid number of operands!");
1433    Inst.addOperand(MCOperand::CreateReg(getReg()));
1434  }
1435
1436  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1437    assert(N == 3 && "Invalid number of operands!");
1438    assert(isRegShiftedReg() &&
1439           "addRegShiftedRegOperands() on non RegShiftedReg!");
1440    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1441    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1442    Inst.addOperand(MCOperand::CreateImm(
1443      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1444  }
1445
1446  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1447    assert(N == 2 && "Invalid number of operands!");
1448    assert(isRegShiftedImm() &&
1449           "addRegShiftedImmOperands() on non RegShiftedImm!");
1450    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1451    // Shift of #32 is encoded as 0 where permitted
1452    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1453    Inst.addOperand(MCOperand::CreateImm(
1454      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1455  }
1456
1457  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1458    assert(N == 1 && "Invalid number of operands!");
1459    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1460                                         ShifterImm.Imm));
1461  }
1462
1463  void addRegListOperands(MCInst &Inst, unsigned N) const {
1464    assert(N == 1 && "Invalid number of operands!");
1465    const SmallVectorImpl<unsigned> &RegList = getRegList();
1466    for (SmallVectorImpl<unsigned>::const_iterator
1467           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1468      Inst.addOperand(MCOperand::CreateReg(*I));
1469  }
1470
1471  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1472    addRegListOperands(Inst, N);
1473  }
1474
1475  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1476    addRegListOperands(Inst, N);
1477  }
1478
1479  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1480    assert(N == 1 && "Invalid number of operands!");
1481    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1482    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1483  }
1484
1485  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1486    assert(N == 1 && "Invalid number of operands!");
1487    // Munge the lsb/width into a bitfield mask.
1488    unsigned lsb = Bitfield.LSB;
1489    unsigned width = Bitfield.Width;
1490    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1491    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1492                      (32 - (lsb + width)));
1493    Inst.addOperand(MCOperand::CreateImm(Mask));
1494  }
1495
1496  void addImmOperands(MCInst &Inst, unsigned N) const {
1497    assert(N == 1 && "Invalid number of operands!");
1498    addExpr(Inst, getImm());
1499  }
1500
1501  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1502    assert(N == 1 && "Invalid number of operands!");
1503    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1504    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1505  }
1506
1507  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1508    assert(N == 1 && "Invalid number of operands!");
1509    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1510    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1511  }
1512
1513  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1514    assert(N == 1 && "Invalid number of operands!");
1515    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1516    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1517    Inst.addOperand(MCOperand::CreateImm(Val));
1518  }
1519
1520  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1521    assert(N == 1 && "Invalid number of operands!");
1522    // FIXME: We really want to scale the value here, but the LDRD/STRD
1523    // instruction don't encode operands that way yet.
1524    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1525    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1526  }
1527
1528  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1529    assert(N == 1 && "Invalid number of operands!");
1530    // The immediate is scaled by four in the encoding and is stored
1531    // in the MCInst as such. Lop off the low two bits here.
1532    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1533    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1534  }
1535
1536  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1537    assert(N == 1 && "Invalid number of operands!");
1538    // The immediate is scaled by four in the encoding and is stored
1539    // in the MCInst as such. Lop off the low two bits here.
1540    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1541    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1542  }
1543
1544  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1545    assert(N == 1 && "Invalid number of operands!");
1546    // The immediate is scaled by four in the encoding and is stored
1547    // in the MCInst as such. Lop off the low two bits here.
1548    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1549    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1550  }
1551
1552  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1553    assert(N == 1 && "Invalid number of operands!");
1554    // The constant encodes as the immediate-1, and we store in the instruction
1555    // the bits as encoded, so subtract off one here.
1556    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1557    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1558  }
1559
1560  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1561    assert(N == 1 && "Invalid number of operands!");
1562    // The constant encodes as the immediate-1, and we store in the instruction
1563    // the bits as encoded, so subtract off one here.
1564    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1565    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1566  }
1567
1568  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1569    assert(N == 1 && "Invalid number of operands!");
1570    // The constant encodes as the immediate, except for 32, which encodes as
1571    // zero.
1572    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1573    unsigned Imm = CE->getValue();
1574    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1575  }
1576
1577  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1578    assert(N == 1 && "Invalid number of operands!");
1579    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1580    // the instruction as well.
1581    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1582    int Val = CE->getValue();
1583    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1584  }
1585
1586  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1587    assert(N == 1 && "Invalid number of operands!");
1588    // The operand is actually a t2_so_imm, but we have its bitwise
1589    // negation in the assembly source, so twiddle it here.
1590    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1591    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1592  }
1593
1594  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1595    assert(N == 1 && "Invalid number of operands!");
1596    // The operand is actually a t2_so_imm, but we have its
1597    // negation in the assembly source, so twiddle it here.
1598    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1599    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1600  }
1601
1602  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1603    assert(N == 1 && "Invalid number of operands!");
1604    // The operand is actually an imm0_4095, but we have its
1605    // negation in the assembly source, so twiddle it here.
1606    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1607    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1608  }
1609
1610  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1611    assert(N == 1 && "Invalid number of operands!");
1612    // The operand is actually a so_imm, but we have its bitwise
1613    // negation in the assembly source, so twiddle it here.
1614    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1615    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1616  }
1617
1618  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1619    assert(N == 1 && "Invalid number of operands!");
1620    // The operand is actually a so_imm, but we have its
1621    // negation in the assembly source, so twiddle it here.
1622    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1623    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1624  }
1625
1626  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1627    assert(N == 1 && "Invalid number of operands!");
1628    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1629  }
1630
1631  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1632    assert(N == 1 && "Invalid number of operands!");
1633    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1634  }
1635
1636  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1637    assert(N == 1 && "Invalid number of operands!");
1638    int32_t Imm = Memory.OffsetImm->getValue();
1639    // FIXME: Handle #-0
1640    if (Imm == INT32_MIN) Imm = 0;
1641    Inst.addOperand(MCOperand::CreateImm(Imm));
1642  }
1643
1644  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1645    assert(N == 2 && "Invalid number of operands!");
1646    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1647    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1648  }
1649
1650  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1651    assert(N == 3 && "Invalid number of operands!");
1652    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1653    if (!Memory.OffsetRegNum) {
1654      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1655      // Special case for #-0
1656      if (Val == INT32_MIN) Val = 0;
1657      if (Val < 0) Val = -Val;
1658      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1659    } else {
1660      // For register offset, we encode the shift type and negation flag
1661      // here.
1662      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1663                              Memory.ShiftImm, Memory.ShiftType);
1664    }
1665    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1666    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1667    Inst.addOperand(MCOperand::CreateImm(Val));
1668  }
1669
1670  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1671    assert(N == 2 && "Invalid number of operands!");
1672    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1673    assert(CE && "non-constant AM2OffsetImm operand!");
1674    int32_t Val = CE->getValue();
1675    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1676    // Special case for #-0
1677    if (Val == INT32_MIN) Val = 0;
1678    if (Val < 0) Val = -Val;
1679    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1680    Inst.addOperand(MCOperand::CreateReg(0));
1681    Inst.addOperand(MCOperand::CreateImm(Val));
1682  }
1683
1684  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1685    assert(N == 3 && "Invalid number of operands!");
1686    // If we have an immediate that's not a constant, treat it as a label
1687    // reference needing a fixup. If it is a constant, it's something else
1688    // and we reject it.
1689    if (isImm()) {
1690      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1691      Inst.addOperand(MCOperand::CreateReg(0));
1692      Inst.addOperand(MCOperand::CreateImm(0));
1693      return;
1694    }
1695
1696    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1697    if (!Memory.OffsetRegNum) {
1698      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1699      // Special case for #-0
1700      if (Val == INT32_MIN) Val = 0;
1701      if (Val < 0) Val = -Val;
1702      Val = ARM_AM::getAM3Opc(AddSub, Val);
1703    } else {
1704      // For register offset, we encode the shift type and negation flag
1705      // here.
1706      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1707    }
1708    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1709    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1710    Inst.addOperand(MCOperand::CreateImm(Val));
1711  }
1712
1713  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1714    assert(N == 2 && "Invalid number of operands!");
1715    if (Kind == k_PostIndexRegister) {
1716      int32_t Val =
1717        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1718      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1719      Inst.addOperand(MCOperand::CreateImm(Val));
1720      return;
1721    }
1722
1723    // Constant offset.
1724    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1725    int32_t Val = CE->getValue();
1726    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1727    // Special case for #-0
1728    if (Val == INT32_MIN) Val = 0;
1729    if (Val < 0) Val = -Val;
1730    Val = ARM_AM::getAM3Opc(AddSub, Val);
1731    Inst.addOperand(MCOperand::CreateReg(0));
1732    Inst.addOperand(MCOperand::CreateImm(Val));
1733  }
1734
1735  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1736    assert(N == 2 && "Invalid number of operands!");
1737    // If we have an immediate that's not a constant, treat it as a label
1738    // reference needing a fixup. If it is a constant, it's something else
1739    // and we reject it.
1740    if (isImm()) {
1741      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1742      Inst.addOperand(MCOperand::CreateImm(0));
1743      return;
1744    }
1745
1746    // The lower two bits are always zero and as such are not encoded.
1747    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1748    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1749    // Special case for #-0
1750    if (Val == INT32_MIN) Val = 0;
1751    if (Val < 0) Val = -Val;
1752    Val = ARM_AM::getAM5Opc(AddSub, Val);
1753    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1754    Inst.addOperand(MCOperand::CreateImm(Val));
1755  }
1756
1757  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1758    assert(N == 2 && "Invalid number of operands!");
1759    // If we have an immediate that's not a constant, treat it as a label
1760    // reference needing a fixup. If it is a constant, it's something else
1761    // and we reject it.
1762    if (isImm()) {
1763      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1764      Inst.addOperand(MCOperand::CreateImm(0));
1765      return;
1766    }
1767
1768    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1769    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1770    Inst.addOperand(MCOperand::CreateImm(Val));
1771  }
1772
1773  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1774    assert(N == 2 && "Invalid number of operands!");
1775    // The lower two bits are always zero and as such are not encoded.
1776    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1777    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1778    Inst.addOperand(MCOperand::CreateImm(Val));
1779  }
1780
1781  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1782    assert(N == 2 && "Invalid number of operands!");
1783    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1784    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1785    Inst.addOperand(MCOperand::CreateImm(Val));
1786  }
1787
1788  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1789    addMemImm8OffsetOperands(Inst, N);
1790  }
1791
1792  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1793    addMemImm8OffsetOperands(Inst, N);
1794  }
1795
1796  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1797    assert(N == 2 && "Invalid number of operands!");
1798    // If this is an immediate, it's a label reference.
1799    if (isImm()) {
1800      addExpr(Inst, getImm());
1801      Inst.addOperand(MCOperand::CreateImm(0));
1802      return;
1803    }
1804
1805    // Otherwise, it's a normal memory reg+offset.
1806    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1807    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1808    Inst.addOperand(MCOperand::CreateImm(Val));
1809  }
1810
1811  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1812    assert(N == 2 && "Invalid number of operands!");
1813    // If this is an immediate, it's a label reference.
1814    if (isImm()) {
1815      addExpr(Inst, getImm());
1816      Inst.addOperand(MCOperand::CreateImm(0));
1817      return;
1818    }
1819
1820    // Otherwise, it's a normal memory reg+offset.
1821    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1822    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1823    Inst.addOperand(MCOperand::CreateImm(Val));
1824  }
1825
1826  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1827    assert(N == 2 && "Invalid number of operands!");
1828    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1829    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1830  }
1831
1832  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1833    assert(N == 2 && "Invalid number of operands!");
1834    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1835    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1836  }
1837
1838  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1839    assert(N == 3 && "Invalid number of operands!");
1840    unsigned Val =
1841      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1842                        Memory.ShiftImm, Memory.ShiftType);
1843    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1844    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1845    Inst.addOperand(MCOperand::CreateImm(Val));
1846  }
1847
1848  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1849    assert(N == 3 && "Invalid number of operands!");
1850    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1851    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1852    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1853  }
1854
1855  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1856    assert(N == 2 && "Invalid number of operands!");
1857    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1858    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1859  }
1860
1861  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1862    assert(N == 2 && "Invalid number of operands!");
1863    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1864    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1865    Inst.addOperand(MCOperand::CreateImm(Val));
1866  }
1867
1868  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1869    assert(N == 2 && "Invalid number of operands!");
1870    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1871    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1872    Inst.addOperand(MCOperand::CreateImm(Val));
1873  }
1874
1875  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1876    assert(N == 2 && "Invalid number of operands!");
1877    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1878    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1879    Inst.addOperand(MCOperand::CreateImm(Val));
1880  }
1881
1882  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1883    assert(N == 2 && "Invalid number of operands!");
1884    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1885    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1886    Inst.addOperand(MCOperand::CreateImm(Val));
1887  }
1888
1889  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1890    assert(N == 1 && "Invalid number of operands!");
1891    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1892    assert(CE && "non-constant post-idx-imm8 operand!");
1893    int Imm = CE->getValue();
1894    bool isAdd = Imm >= 0;
1895    if (Imm == INT32_MIN) Imm = 0;
1896    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1897    Inst.addOperand(MCOperand::CreateImm(Imm));
1898  }
1899
1900  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1901    assert(N == 1 && "Invalid number of operands!");
1902    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1903    assert(CE && "non-constant post-idx-imm8s4 operand!");
1904    int Imm = CE->getValue();
1905    bool isAdd = Imm >= 0;
1906    if (Imm == INT32_MIN) Imm = 0;
1907    // Immediate is scaled by 4.
1908    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1909    Inst.addOperand(MCOperand::CreateImm(Imm));
1910  }
1911
1912  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1913    assert(N == 2 && "Invalid number of operands!");
1914    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1915    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1916  }
1917
1918  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1919    assert(N == 2 && "Invalid number of operands!");
1920    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1921    // The sign, shift type, and shift amount are encoded in a single operand
1922    // using the AM2 encoding helpers.
1923    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1924    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1925                                     PostIdxReg.ShiftTy);
1926    Inst.addOperand(MCOperand::CreateImm(Imm));
1927  }
1928
1929  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1930    assert(N == 1 && "Invalid number of operands!");
1931    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1932  }
1933
1934  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1935    assert(N == 1 && "Invalid number of operands!");
1936    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1937  }
1938
1939  void addVecListOperands(MCInst &Inst, unsigned N) const {
1940    assert(N == 1 && "Invalid number of operands!");
1941    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1942  }
1943
1944  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1945    assert(N == 2 && "Invalid number of operands!");
1946    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1947    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1948  }
1949
1950  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1951    assert(N == 1 && "Invalid number of operands!");
1952    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1953  }
1954
1955  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1956    assert(N == 1 && "Invalid number of operands!");
1957    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1958  }
1959
1960  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1961    assert(N == 1 && "Invalid number of operands!");
1962    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1963  }
1964
1965  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1966    assert(N == 1 && "Invalid number of operands!");
1967    // The immediate encodes the type of constant as well as the value.
1968    // Mask in that this is an i8 splat.
1969    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1970    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1971  }
1972
1973  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1974    assert(N == 1 && "Invalid number of operands!");
1975    // The immediate encodes the type of constant as well as the value.
1976    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1977    unsigned Value = CE->getValue();
1978    if (Value >= 256)
1979      Value = (Value >> 8) | 0xa00;
1980    else
1981      Value |= 0x800;
1982    Inst.addOperand(MCOperand::CreateImm(Value));
1983  }
1984
1985  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1986    assert(N == 1 && "Invalid number of operands!");
1987    // The immediate encodes the type of constant as well as the value.
1988    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1989    unsigned Value = CE->getValue();
1990    if (Value >= 256 && Value <= 0xff00)
1991      Value = (Value >> 8) | 0x200;
1992    else if (Value > 0xffff && Value <= 0xff0000)
1993      Value = (Value >> 16) | 0x400;
1994    else if (Value > 0xffffff)
1995      Value = (Value >> 24) | 0x600;
1996    Inst.addOperand(MCOperand::CreateImm(Value));
1997  }
1998
1999  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2000    assert(N == 1 && "Invalid number of operands!");
2001    // The immediate encodes the type of constant as well as the value.
2002    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2003    unsigned Value = CE->getValue();
2004    if (Value >= 256 && Value <= 0xffff)
2005      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2006    else if (Value > 0xffff && Value <= 0xffffff)
2007      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2008    else if (Value > 0xffffff)
2009      Value = (Value >> 24) | 0x600;
2010    Inst.addOperand(MCOperand::CreateImm(Value));
2011  }
2012
2013  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2014    assert(N == 1 && "Invalid number of operands!");
2015    // The immediate encodes the type of constant as well as the value.
2016    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2017    unsigned Value = ~CE->getValue();
2018    if (Value >= 256 && Value <= 0xffff)
2019      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2020    else if (Value > 0xffff && Value <= 0xffffff)
2021      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2022    else if (Value > 0xffffff)
2023      Value = (Value >> 24) | 0x600;
2024    Inst.addOperand(MCOperand::CreateImm(Value));
2025  }
2026
2027  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2028    assert(N == 1 && "Invalid number of operands!");
2029    // The immediate encodes the type of constant as well as the value.
2030    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2031    uint64_t Value = CE->getValue();
2032    unsigned Imm = 0;
2033    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2034      Imm |= (Value & 1) << i;
2035    }
2036    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2037  }
2038
2039  virtual void print(raw_ostream &OS) const;
2040
2041  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2042    ARMOperand *Op = new ARMOperand(k_ITCondMask);
2043    Op->ITMask.Mask = Mask;
2044    Op->StartLoc = S;
2045    Op->EndLoc = S;
2046    return Op;
2047  }
2048
2049  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2050    ARMOperand *Op = new ARMOperand(k_CondCode);
2051    Op->CC.Val = CC;
2052    Op->StartLoc = S;
2053    Op->EndLoc = S;
2054    return Op;
2055  }
2056
2057  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2058    ARMOperand *Op = new ARMOperand(k_CoprocNum);
2059    Op->Cop.Val = CopVal;
2060    Op->StartLoc = S;
2061    Op->EndLoc = S;
2062    return Op;
2063  }
2064
2065  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2066    ARMOperand *Op = new ARMOperand(k_CoprocReg);
2067    Op->Cop.Val = CopVal;
2068    Op->StartLoc = S;
2069    Op->EndLoc = S;
2070    return Op;
2071  }
2072
2073  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2074    ARMOperand *Op = new ARMOperand(k_CoprocOption);
2075    Op->Cop.Val = Val;
2076    Op->StartLoc = S;
2077    Op->EndLoc = E;
2078    return Op;
2079  }
2080
2081  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2082    ARMOperand *Op = new ARMOperand(k_CCOut);
2083    Op->Reg.RegNum = RegNum;
2084    Op->StartLoc = S;
2085    Op->EndLoc = S;
2086    return Op;
2087  }
2088
2089  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2090    ARMOperand *Op = new ARMOperand(k_Token);
2091    Op->Tok.Data = Str.data();
2092    Op->Tok.Length = Str.size();
2093    Op->StartLoc = S;
2094    Op->EndLoc = S;
2095    return Op;
2096  }
2097
2098  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2099    ARMOperand *Op = new ARMOperand(k_Register);
2100    Op->Reg.RegNum = RegNum;
2101    Op->StartLoc = S;
2102    Op->EndLoc = E;
2103    return Op;
2104  }
2105
2106  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2107                                           unsigned SrcReg,
2108                                           unsigned ShiftReg,
2109                                           unsigned ShiftImm,
2110                                           SMLoc S, SMLoc E) {
2111    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2112    Op->RegShiftedReg.ShiftTy = ShTy;
2113    Op->RegShiftedReg.SrcReg = SrcReg;
2114    Op->RegShiftedReg.ShiftReg = ShiftReg;
2115    Op->RegShiftedReg.ShiftImm = ShiftImm;
2116    Op->StartLoc = S;
2117    Op->EndLoc = E;
2118    return Op;
2119  }
2120
2121  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2122                                            unsigned SrcReg,
2123                                            unsigned ShiftImm,
2124                                            SMLoc S, SMLoc E) {
2125    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2126    Op->RegShiftedImm.ShiftTy = ShTy;
2127    Op->RegShiftedImm.SrcReg = SrcReg;
2128    Op->RegShiftedImm.ShiftImm = ShiftImm;
2129    Op->StartLoc = S;
2130    Op->EndLoc = E;
2131    return Op;
2132  }
2133
2134  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2135                                   SMLoc S, SMLoc E) {
2136    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2137    Op->ShifterImm.isASR = isASR;
2138    Op->ShifterImm.Imm = Imm;
2139    Op->StartLoc = S;
2140    Op->EndLoc = E;
2141    return Op;
2142  }
2143
2144  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2145    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2146    Op->RotImm.Imm = Imm;
2147    Op->StartLoc = S;
2148    Op->EndLoc = E;
2149    return Op;
2150  }
2151
2152  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2153                                    SMLoc S, SMLoc E) {
2154    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2155    Op->Bitfield.LSB = LSB;
2156    Op->Bitfield.Width = Width;
2157    Op->StartLoc = S;
2158    Op->EndLoc = E;
2159    return Op;
2160  }
2161
2162  static ARMOperand *
2163  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2164                SMLoc StartLoc, SMLoc EndLoc) {
2165    KindTy Kind = k_RegisterList;
2166
2167    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2168      Kind = k_DPRRegisterList;
2169    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2170             contains(Regs.front().first))
2171      Kind = k_SPRRegisterList;
2172
2173    ARMOperand *Op = new ARMOperand(Kind);
2174    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2175           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2176      Op->Registers.push_back(I->first);
2177    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2178    Op->StartLoc = StartLoc;
2179    Op->EndLoc = EndLoc;
2180    return Op;
2181  }
2182
2183  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2184                                      bool isDoubleSpaced, SMLoc S, SMLoc E) {
2185    ARMOperand *Op = new ARMOperand(k_VectorList);
2186    Op->VectorList.RegNum = RegNum;
2187    Op->VectorList.Count = Count;
2188    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2189    Op->StartLoc = S;
2190    Op->EndLoc = E;
2191    return Op;
2192  }
2193
2194  static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2195                                              bool isDoubleSpaced,
2196                                              SMLoc S, SMLoc E) {
2197    ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2198    Op->VectorList.RegNum = RegNum;
2199    Op->VectorList.Count = Count;
2200    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2201    Op->StartLoc = S;
2202    Op->EndLoc = E;
2203    return Op;
2204  }
2205
2206  static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2207                                             unsigned Index,
2208                                             bool isDoubleSpaced,
2209                                             SMLoc S, SMLoc E) {
2210    ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2211    Op->VectorList.RegNum = RegNum;
2212    Op->VectorList.Count = Count;
2213    Op->VectorList.LaneIndex = Index;
2214    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2215    Op->StartLoc = S;
2216    Op->EndLoc = E;
2217    return Op;
2218  }
2219
2220  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2221                                       MCContext &Ctx) {
2222    ARMOperand *Op = new ARMOperand(k_VectorIndex);
2223    Op->VectorIndex.Val = Idx;
2224    Op->StartLoc = S;
2225    Op->EndLoc = E;
2226    return Op;
2227  }
2228
2229  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2230    ARMOperand *Op = new ARMOperand(k_Immediate);
2231    Op->Imm.Val = Val;
2232    Op->StartLoc = S;
2233    Op->EndLoc = E;
2234    return Op;
2235  }
2236
2237  static ARMOperand *CreateMem(unsigned BaseRegNum,
2238                               const MCConstantExpr *OffsetImm,
2239                               unsigned OffsetRegNum,
2240                               ARM_AM::ShiftOpc ShiftType,
2241                               unsigned ShiftImm,
2242                               unsigned Alignment,
2243                               bool isNegative,
2244                               SMLoc S, SMLoc E) {
2245    ARMOperand *Op = new ARMOperand(k_Memory);
2246    Op->Memory.BaseRegNum = BaseRegNum;
2247    Op->Memory.OffsetImm = OffsetImm;
2248    Op->Memory.OffsetRegNum = OffsetRegNum;
2249    Op->Memory.ShiftType = ShiftType;
2250    Op->Memory.ShiftImm = ShiftImm;
2251    Op->Memory.Alignment = Alignment;
2252    Op->Memory.isNegative = isNegative;
2253    Op->StartLoc = S;
2254    Op->EndLoc = E;
2255    return Op;
2256  }
2257
2258  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2259                                      ARM_AM::ShiftOpc ShiftTy,
2260                                      unsigned ShiftImm,
2261                                      SMLoc S, SMLoc E) {
2262    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2263    Op->PostIdxReg.RegNum = RegNum;
2264    Op->PostIdxReg.isAdd = isAdd;
2265    Op->PostIdxReg.ShiftTy = ShiftTy;
2266    Op->PostIdxReg.ShiftImm = ShiftImm;
2267    Op->StartLoc = S;
2268    Op->EndLoc = E;
2269    return Op;
2270  }
2271
2272  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2273    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2274    Op->MBOpt.Val = Opt;
2275    Op->StartLoc = S;
2276    Op->EndLoc = S;
2277    return Op;
2278  }
2279
2280  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2281    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2282    Op->IFlags.Val = IFlags;
2283    Op->StartLoc = S;
2284    Op->EndLoc = S;
2285    return Op;
2286  }
2287
2288  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2289    ARMOperand *Op = new ARMOperand(k_MSRMask);
2290    Op->MMask.Val = MMask;
2291    Op->StartLoc = S;
2292    Op->EndLoc = S;
2293    return Op;
2294  }
2295};
2296
2297} // end anonymous namespace.
2298
2299void ARMOperand::print(raw_ostream &OS) const {
2300  switch (Kind) {
2301  case k_CondCode:
2302    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2303    break;
2304  case k_CCOut:
2305    OS << "<ccout " << getReg() << ">";
2306    break;
2307  case k_ITCondMask: {
2308    static const char *const MaskStr[] = {
2309      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2310      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2311    };
2312    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2313    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2314    break;
2315  }
2316  case k_CoprocNum:
2317    OS << "<coprocessor number: " << getCoproc() << ">";
2318    break;
2319  case k_CoprocReg:
2320    OS << "<coprocessor register: " << getCoproc() << ">";
2321    break;
2322  case k_CoprocOption:
2323    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2324    break;
2325  case k_MSRMask:
2326    OS << "<mask: " << getMSRMask() << ">";
2327    break;
2328  case k_Immediate:
2329    getImm()->print(OS);
2330    break;
2331  case k_MemBarrierOpt:
2332    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2333    break;
2334  case k_Memory:
2335    OS << "<memory "
2336       << " base:" << Memory.BaseRegNum;
2337    OS << ">";
2338    break;
2339  case k_PostIndexRegister:
2340    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2341       << PostIdxReg.RegNum;
2342    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2343      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2344         << PostIdxReg.ShiftImm;
2345    OS << ">";
2346    break;
2347  case k_ProcIFlags: {
2348    OS << "<ARM_PROC::";
2349    unsigned IFlags = getProcIFlags();
2350    for (int i=2; i >= 0; --i)
2351      if (IFlags & (1 << i))
2352        OS << ARM_PROC::IFlagsToString(1 << i);
2353    OS << ">";
2354    break;
2355  }
2356  case k_Register:
2357    OS << "<register " << getReg() << ">";
2358    break;
2359  case k_ShifterImmediate:
2360    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2361       << " #" << ShifterImm.Imm << ">";
2362    break;
2363  case k_ShiftedRegister:
2364    OS << "<so_reg_reg "
2365       << RegShiftedReg.SrcReg << " "
2366       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2367       << " " << RegShiftedReg.ShiftReg << ">";
2368    break;
2369  case k_ShiftedImmediate:
2370    OS << "<so_reg_imm "
2371       << RegShiftedImm.SrcReg << " "
2372       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2373       << " #" << RegShiftedImm.ShiftImm << ">";
2374    break;
2375  case k_RotateImmediate:
2376    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2377    break;
2378  case k_BitfieldDescriptor:
2379    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2380       << ", width: " << Bitfield.Width << ">";
2381    break;
2382  case k_RegisterList:
2383  case k_DPRRegisterList:
2384  case k_SPRRegisterList: {
2385    OS << "<register_list ";
2386
2387    const SmallVectorImpl<unsigned> &RegList = getRegList();
2388    for (SmallVectorImpl<unsigned>::const_iterator
2389           I = RegList.begin(), E = RegList.end(); I != E; ) {
2390      OS << *I;
2391      if (++I < E) OS << ", ";
2392    }
2393
2394    OS << ">";
2395    break;
2396  }
2397  case k_VectorList:
2398    OS << "<vector_list " << VectorList.Count << " * "
2399       << VectorList.RegNum << ">";
2400    break;
2401  case k_VectorListAllLanes:
2402    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2403       << VectorList.RegNum << ">";
2404    break;
2405  case k_VectorListIndexed:
2406    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2407       << VectorList.Count << " * " << VectorList.RegNum << ">";
2408    break;
2409  case k_Token:
2410    OS << "'" << getToken() << "'";
2411    break;
2412  case k_VectorIndex:
2413    OS << "<vectorindex " << getVectorIndex() << ">";
2414    break;
2415  }
2416}
2417
2418/// @name Auto-generated Match Functions
2419/// {
2420
2421static unsigned MatchRegisterName(StringRef Name);
2422
2423/// }
2424
2425bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2426                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2427  StartLoc = Parser.getTok().getLoc();
2428  RegNo = tryParseRegister();
2429  EndLoc = Parser.getTok().getLoc();
2430
2431  return (RegNo == (unsigned)-1);
2432}
2433
2434/// Try to parse a register name.  The token must be an Identifier when called,
2435/// and if it is a register name the token is eaten and the register number is
2436/// returned.  Otherwise return -1.
2437///
2438int ARMAsmParser::tryParseRegister() {
2439  const AsmToken &Tok = Parser.getTok();
2440  if (Tok.isNot(AsmToken::Identifier)) return -1;
2441
2442  std::string lowerCase = Tok.getString().lower();
2443  unsigned RegNum = MatchRegisterName(lowerCase);
2444  if (!RegNum) {
2445    RegNum = StringSwitch<unsigned>(lowerCase)
2446      .Case("r13", ARM::SP)
2447      .Case("r14", ARM::LR)
2448      .Case("r15", ARM::PC)
2449      .Case("ip", ARM::R12)
2450      // Additional register name aliases for 'gas' compatibility.
2451      .Case("a1", ARM::R0)
2452      .Case("a2", ARM::R1)
2453      .Case("a3", ARM::R2)
2454      .Case("a4", ARM::R3)
2455      .Case("v1", ARM::R4)
2456      .Case("v2", ARM::R5)
2457      .Case("v3", ARM::R6)
2458      .Case("v4", ARM::R7)
2459      .Case("v5", ARM::R8)
2460      .Case("v6", ARM::R9)
2461      .Case("v7", ARM::R10)
2462      .Case("v8", ARM::R11)
2463      .Case("sb", ARM::R9)
2464      .Case("sl", ARM::R10)
2465      .Case("fp", ARM::R11)
2466      .Default(0);
2467  }
2468  if (!RegNum) {
2469    // Check for aliases registered via .req. Canonicalize to lower case.
2470    // That's more consistent since register names are case insensitive, and
2471    // it's how the original entry was passed in from MC/MCParser/AsmParser.
2472    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2473    // If no match, return failure.
2474    if (Entry == RegisterReqs.end())
2475      return -1;
2476    Parser.Lex(); // Eat identifier token.
2477    return Entry->getValue();
2478  }
2479
2480  Parser.Lex(); // Eat identifier token.
2481
2482  return RegNum;
2483}
2484
2485// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2486// If a recoverable error occurs, return 1. If an irrecoverable error
2487// occurs, return -1. An irrecoverable error is one where tokens have been
2488// consumed in the process of trying to parse the shifter (i.e., when it is
2489// indeed a shifter operand, but malformed).
2490int ARMAsmParser::tryParseShiftRegister(
2491                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2492  SMLoc S = Parser.getTok().getLoc();
2493  const AsmToken &Tok = Parser.getTok();
2494  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2495
2496  std::string lowerCase = Tok.getString().lower();
2497  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2498      .Case("asl", ARM_AM::lsl)
2499      .Case("lsl", ARM_AM::lsl)
2500      .Case("lsr", ARM_AM::lsr)
2501      .Case("asr", ARM_AM::asr)
2502      .Case("ror", ARM_AM::ror)
2503      .Case("rrx", ARM_AM::rrx)
2504      .Default(ARM_AM::no_shift);
2505
2506  if (ShiftTy == ARM_AM::no_shift)
2507    return 1;
2508
2509  Parser.Lex(); // Eat the operator.
2510
2511  // The source register for the shift has already been added to the
2512  // operand list, so we need to pop it off and combine it into the shifted
2513  // register operand instead.
2514  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2515  if (!PrevOp->isReg())
2516    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2517  int SrcReg = PrevOp->getReg();
2518  int64_t Imm = 0;
2519  int ShiftReg = 0;
2520  if (ShiftTy == ARM_AM::rrx) {
2521    // RRX Doesn't have an explicit shift amount. The encoder expects
2522    // the shift register to be the same as the source register. Seems odd,
2523    // but OK.
2524    ShiftReg = SrcReg;
2525  } else {
2526    // Figure out if this is shifted by a constant or a register (for non-RRX).
2527    if (Parser.getTok().is(AsmToken::Hash) ||
2528        Parser.getTok().is(AsmToken::Dollar)) {
2529      Parser.Lex(); // Eat hash.
2530      SMLoc ImmLoc = Parser.getTok().getLoc();
2531      const MCExpr *ShiftExpr = 0;
2532      if (getParser().ParseExpression(ShiftExpr)) {
2533        Error(ImmLoc, "invalid immediate shift value");
2534        return -1;
2535      }
2536      // The expression must be evaluatable as an immediate.
2537      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2538      if (!CE) {
2539        Error(ImmLoc, "invalid immediate shift value");
2540        return -1;
2541      }
2542      // Range check the immediate.
2543      // lsl, ror: 0 <= imm <= 31
2544      // lsr, asr: 0 <= imm <= 32
2545      Imm = CE->getValue();
2546      if (Imm < 0 ||
2547          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2548          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2549        Error(ImmLoc, "immediate shift value out of range");
2550        return -1;
2551      }
2552      // shift by zero is a nop. Always send it through as lsl.
2553      // ('as' compatibility)
2554      if (Imm == 0)
2555        ShiftTy = ARM_AM::lsl;
2556    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2557      ShiftReg = tryParseRegister();
2558      SMLoc L = Parser.getTok().getLoc();
2559      if (ShiftReg == -1) {
2560        Error (L, "expected immediate or register in shift operand");
2561        return -1;
2562      }
2563    } else {
2564      Error (Parser.getTok().getLoc(),
2565                    "expected immediate or register in shift operand");
2566      return -1;
2567    }
2568  }
2569
2570  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2571    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2572                                                         ShiftReg, Imm,
2573                                               S, Parser.getTok().getLoc()));
2574  else
2575    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2576                                               S, Parser.getTok().getLoc()));
2577
2578  return 0;
2579}
2580
2581
2582/// Try to parse a register name.  The token must be an Identifier when called.
2583/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2584/// if there is a "writeback". 'true' if it's not a register.
2585///
2586/// TODO this is likely to change to allow different register types and or to
2587/// parse for a specific register type.
2588bool ARMAsmParser::
2589tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2590  SMLoc S = Parser.getTok().getLoc();
2591  int RegNo = tryParseRegister();
2592  if (RegNo == -1)
2593    return true;
2594
2595  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2596
2597  const AsmToken &ExclaimTok = Parser.getTok();
2598  if (ExclaimTok.is(AsmToken::Exclaim)) {
2599    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2600                                               ExclaimTok.getLoc()));
2601    Parser.Lex(); // Eat exclaim token
2602    return false;
2603  }
2604
2605  // Also check for an index operand. This is only legal for vector registers,
2606  // but that'll get caught OK in operand matching, so we don't need to
2607  // explicitly filter everything else out here.
2608  if (Parser.getTok().is(AsmToken::LBrac)) {
2609    SMLoc SIdx = Parser.getTok().getLoc();
2610    Parser.Lex(); // Eat left bracket token.
2611
2612    const MCExpr *ImmVal;
2613    if (getParser().ParseExpression(ImmVal))
2614      return true;
2615    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2616    if (!MCE)
2617      return TokError("immediate value expected for vector index");
2618
2619    SMLoc E = Parser.getTok().getLoc();
2620    if (Parser.getTok().isNot(AsmToken::RBrac))
2621      return Error(E, "']' expected");
2622
2623    Parser.Lex(); // Eat right bracket token.
2624
2625    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2626                                                     SIdx, E,
2627                                                     getContext()));
2628  }
2629
2630  return false;
2631}
2632
2633/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2634/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2635/// "c5", ...
2636static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2637  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2638  // but efficient.
2639  switch (Name.size()) {
2640  default: return -1;
2641  case 2:
2642    if (Name[0] != CoprocOp)
2643      return -1;
2644    switch (Name[1]) {
2645    default:  return -1;
2646    case '0': return 0;
2647    case '1': return 1;
2648    case '2': return 2;
2649    case '3': return 3;
2650    case '4': return 4;
2651    case '5': return 5;
2652    case '6': return 6;
2653    case '7': return 7;
2654    case '8': return 8;
2655    case '9': return 9;
2656    }
2657  case 3:
2658    if (Name[0] != CoprocOp || Name[1] != '1')
2659      return -1;
2660    switch (Name[2]) {
2661    default:  return -1;
2662    case '0': return 10;
2663    case '1': return 11;
2664    case '2': return 12;
2665    case '3': return 13;
2666    case '4': return 14;
2667    case '5': return 15;
2668    }
2669  }
2670}
2671
2672/// parseITCondCode - Try to parse a condition code for an IT instruction.
2673ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2674parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2675  SMLoc S = Parser.getTok().getLoc();
2676  const AsmToken &Tok = Parser.getTok();
2677  if (!Tok.is(AsmToken::Identifier))
2678    return MatchOperand_NoMatch;
2679  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2680    .Case("eq", ARMCC::EQ)
2681    .Case("ne", ARMCC::NE)
2682    .Case("hs", ARMCC::HS)
2683    .Case("cs", ARMCC::HS)
2684    .Case("lo", ARMCC::LO)
2685    .Case("cc", ARMCC::LO)
2686    .Case("mi", ARMCC::MI)
2687    .Case("pl", ARMCC::PL)
2688    .Case("vs", ARMCC::VS)
2689    .Case("vc", ARMCC::VC)
2690    .Case("hi", ARMCC::HI)
2691    .Case("ls", ARMCC::LS)
2692    .Case("ge", ARMCC::GE)
2693    .Case("lt", ARMCC::LT)
2694    .Case("gt", ARMCC::GT)
2695    .Case("le", ARMCC::LE)
2696    .Case("al", ARMCC::AL)
2697    .Default(~0U);
2698  if (CC == ~0U)
2699    return MatchOperand_NoMatch;
2700  Parser.Lex(); // Eat the token.
2701
2702  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2703
2704  return MatchOperand_Success;
2705}
2706
2707/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2708/// token must be an Identifier when called, and if it is a coprocessor
2709/// number, the token is eaten and the operand is added to the operand list.
2710ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2711parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2712  SMLoc S = Parser.getTok().getLoc();
2713  const AsmToken &Tok = Parser.getTok();
2714  if (Tok.isNot(AsmToken::Identifier))
2715    return MatchOperand_NoMatch;
2716
2717  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2718  if (Num == -1)
2719    return MatchOperand_NoMatch;
2720
2721  Parser.Lex(); // Eat identifier token.
2722  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2723  return MatchOperand_Success;
2724}
2725
2726/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2727/// token must be an Identifier when called, and if it is a coprocessor
2728/// number, the token is eaten and the operand is added to the operand list.
2729ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2730parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2731  SMLoc S = Parser.getTok().getLoc();
2732  const AsmToken &Tok = Parser.getTok();
2733  if (Tok.isNot(AsmToken::Identifier))
2734    return MatchOperand_NoMatch;
2735
2736  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2737  if (Reg == -1)
2738    return MatchOperand_NoMatch;
2739
2740  Parser.Lex(); // Eat identifier token.
2741  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2742  return MatchOperand_Success;
2743}
2744
2745/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2746/// coproc_option : '{' imm0_255 '}'
2747ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2748parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2749  SMLoc S = Parser.getTok().getLoc();
2750
2751  // If this isn't a '{', this isn't a coprocessor immediate operand.
2752  if (Parser.getTok().isNot(AsmToken::LCurly))
2753    return MatchOperand_NoMatch;
2754  Parser.Lex(); // Eat the '{'
2755
2756  const MCExpr *Expr;
2757  SMLoc Loc = Parser.getTok().getLoc();
2758  if (getParser().ParseExpression(Expr)) {
2759    Error(Loc, "illegal expression");
2760    return MatchOperand_ParseFail;
2761  }
2762  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2763  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2764    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2765    return MatchOperand_ParseFail;
2766  }
2767  int Val = CE->getValue();
2768
2769  // Check for and consume the closing '}'
2770  if (Parser.getTok().isNot(AsmToken::RCurly))
2771    return MatchOperand_ParseFail;
2772  SMLoc E = Parser.getTok().getLoc();
2773  Parser.Lex(); // Eat the '}'
2774
2775  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2776  return MatchOperand_Success;
2777}
2778
2779// For register list parsing, we need to map from raw GPR register numbering
2780// to the enumeration values. The enumeration values aren't sorted by
2781// register number due to our using "sp", "lr" and "pc" as canonical names.
2782static unsigned getNextRegister(unsigned Reg) {
2783  // If this is a GPR, we need to do it manually, otherwise we can rely
2784  // on the sort ordering of the enumeration since the other reg-classes
2785  // are sane.
2786  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2787    return Reg + 1;
2788  switch(Reg) {
2789  default: llvm_unreachable("Invalid GPR number!");
2790  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2791  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2792  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2793  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2794  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2795  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2796  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2797  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2798  }
2799}
2800
2801// Return the low-subreg of a given Q register.
2802static unsigned getDRegFromQReg(unsigned QReg) {
2803  switch (QReg) {
2804  default: llvm_unreachable("expected a Q register!");
2805  case ARM::Q0:  return ARM::D0;
2806  case ARM::Q1:  return ARM::D2;
2807  case ARM::Q2:  return ARM::D4;
2808  case ARM::Q3:  return ARM::D6;
2809  case ARM::Q4:  return ARM::D8;
2810  case ARM::Q5:  return ARM::D10;
2811  case ARM::Q6:  return ARM::D12;
2812  case ARM::Q7:  return ARM::D14;
2813  case ARM::Q8:  return ARM::D16;
2814  case ARM::Q9:  return ARM::D18;
2815  case ARM::Q10: return ARM::D20;
2816  case ARM::Q11: return ARM::D22;
2817  case ARM::Q12: return ARM::D24;
2818  case ARM::Q13: return ARM::D26;
2819  case ARM::Q14: return ARM::D28;
2820  case ARM::Q15: return ARM::D30;
2821  }
2822}
2823
2824/// Parse a register list.
2825bool ARMAsmParser::
2826parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2827  assert(Parser.getTok().is(AsmToken::LCurly) &&
2828         "Token is not a Left Curly Brace");
2829  SMLoc S = Parser.getTok().getLoc();
2830  Parser.Lex(); // Eat '{' token.
2831  SMLoc RegLoc = Parser.getTok().getLoc();
2832
2833  // Check the first register in the list to see what register class
2834  // this is a list of.
2835  int Reg = tryParseRegister();
2836  if (Reg == -1)
2837    return Error(RegLoc, "register expected");
2838
2839  // The reglist instructions have at most 16 registers, so reserve
2840  // space for that many.
2841  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2842
2843  // Allow Q regs and just interpret them as the two D sub-registers.
2844  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2845    Reg = getDRegFromQReg(Reg);
2846    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2847    ++Reg;
2848  }
2849  const MCRegisterClass *RC;
2850  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2851    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2852  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2853    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2854  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2855    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2856  else
2857    return Error(RegLoc, "invalid register in register list");
2858
2859  // Store the register.
2860  Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2861
2862  // This starts immediately after the first register token in the list,
2863  // so we can see either a comma or a minus (range separator) as a legal
2864  // next token.
2865  while (Parser.getTok().is(AsmToken::Comma) ||
2866         Parser.getTok().is(AsmToken::Minus)) {
2867    if (Parser.getTok().is(AsmToken::Minus)) {
2868      Parser.Lex(); // Eat the minus.
2869      SMLoc EndLoc = Parser.getTok().getLoc();
2870      int EndReg = tryParseRegister();
2871      if (EndReg == -1)
2872        return Error(EndLoc, "register expected");
2873      // Allow Q regs and just interpret them as the two D sub-registers.
2874      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2875        EndReg = getDRegFromQReg(EndReg) + 1;
2876      // If the register is the same as the start reg, there's nothing
2877      // more to do.
2878      if (Reg == EndReg)
2879        continue;
2880      // The register must be in the same register class as the first.
2881      if (!RC->contains(EndReg))
2882        return Error(EndLoc, "invalid register in register list");
2883      // Ranges must go from low to high.
2884      if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2885        return Error(EndLoc, "bad range in register list");
2886
2887      // Add all the registers in the range to the register list.
2888      while (Reg != EndReg) {
2889        Reg = getNextRegister(Reg);
2890        Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2891      }
2892      continue;
2893    }
2894    Parser.Lex(); // Eat the comma.
2895    RegLoc = Parser.getTok().getLoc();
2896    int OldReg = Reg;
2897    const AsmToken RegTok = Parser.getTok();
2898    Reg = tryParseRegister();
2899    if (Reg == -1)
2900      return Error(RegLoc, "register expected");
2901    // Allow Q regs and just interpret them as the two D sub-registers.
2902    bool isQReg = false;
2903    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2904      Reg = getDRegFromQReg(Reg);
2905      isQReg = true;
2906    }
2907    // The register must be in the same register class as the first.
2908    if (!RC->contains(Reg))
2909      return Error(RegLoc, "invalid register in register list");
2910    // List must be monotonically increasing.
2911    if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg)) {
2912      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2913        Warning(RegLoc, "register list not in ascending order");
2914      else
2915        return Error(RegLoc, "register list not in ascending order");
2916    }
2917    if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) {
2918      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2919              ") in register list");
2920      continue;
2921    }
2922    // VFP register lists must also be contiguous.
2923    // It's OK to use the enumeration values directly here rather, as the
2924    // VFP register classes have the enum sorted properly.
2925    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2926        Reg != OldReg + 1)
2927      return Error(RegLoc, "non-contiguous register range");
2928    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2929    if (isQReg)
2930      Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2931  }
2932
2933  SMLoc E = Parser.getTok().getLoc();
2934  if (Parser.getTok().isNot(AsmToken::RCurly))
2935    return Error(E, "'}' expected");
2936  Parser.Lex(); // Eat '}' token.
2937
2938  // Push the register list operand.
2939  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2940
2941  // The ARM system instruction variants for LDM/STM have a '^' token here.
2942  if (Parser.getTok().is(AsmToken::Caret)) {
2943    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2944    Parser.Lex(); // Eat '^' token.
2945  }
2946
2947  return false;
2948}
2949
2950// Helper function to parse the lane index for vector lists.
2951ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2952parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2953  Index = 0; // Always return a defined index value.
2954  if (Parser.getTok().is(AsmToken::LBrac)) {
2955    Parser.Lex(); // Eat the '['.
2956    if (Parser.getTok().is(AsmToken::RBrac)) {
2957      // "Dn[]" is the 'all lanes' syntax.
2958      LaneKind = AllLanes;
2959      Parser.Lex(); // Eat the ']'.
2960      return MatchOperand_Success;
2961    }
2962
2963    // There's an optional '#' token here. Normally there wouldn't be, but
2964    // inline assemble puts one in, and it's friendly to accept that.
2965    if (Parser.getTok().is(AsmToken::Hash))
2966      Parser.Lex(); // Eat the '#'
2967
2968    const MCExpr *LaneIndex;
2969    SMLoc Loc = Parser.getTok().getLoc();
2970    if (getParser().ParseExpression(LaneIndex)) {
2971      Error(Loc, "illegal expression");
2972      return MatchOperand_ParseFail;
2973    }
2974    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
2975    if (!CE) {
2976      Error(Loc, "lane index must be empty or an integer");
2977      return MatchOperand_ParseFail;
2978    }
2979    if (Parser.getTok().isNot(AsmToken::RBrac)) {
2980      Error(Parser.getTok().getLoc(), "']' expected");
2981      return MatchOperand_ParseFail;
2982    }
2983    Parser.Lex(); // Eat the ']'.
2984    int64_t Val = CE->getValue();
2985
2986    // FIXME: Make this range check context sensitive for .8, .16, .32.
2987    if (Val < 0 || Val > 7) {
2988      Error(Parser.getTok().getLoc(), "lane index out of range");
2989      return MatchOperand_ParseFail;
2990    }
2991    Index = Val;
2992    LaneKind = IndexedLane;
2993    return MatchOperand_Success;
2994  }
2995  LaneKind = NoLanes;
2996  return MatchOperand_Success;
2997}
2998
2999// parse a vector register list
3000ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3001parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3002  VectorLaneTy LaneKind;
3003  unsigned LaneIndex;
3004  SMLoc S = Parser.getTok().getLoc();
3005  // As an extension (to match gas), support a plain D register or Q register
3006  // (without encosing curly braces) as a single or double entry list,
3007  // respectively.
3008  if (Parser.getTok().is(AsmToken::Identifier)) {
3009    int Reg = tryParseRegister();
3010    if (Reg == -1)
3011      return MatchOperand_NoMatch;
3012    SMLoc E = Parser.getTok().getLoc();
3013    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3014      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3015      if (Res != MatchOperand_Success)
3016        return Res;
3017      switch (LaneKind) {
3018      case NoLanes:
3019        E = Parser.getTok().getLoc();
3020        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3021        break;
3022      case AllLanes:
3023        E = Parser.getTok().getLoc();
3024        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3025                                                                S, E));
3026        break;
3027      case IndexedLane:
3028        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3029                                                               LaneIndex,
3030                                                               false, S, E));
3031        break;
3032      }
3033      return MatchOperand_Success;
3034    }
3035    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3036      Reg = getDRegFromQReg(Reg);
3037      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3038      if (Res != MatchOperand_Success)
3039        return Res;
3040      switch (LaneKind) {
3041      case NoLanes:
3042        E = Parser.getTok().getLoc();
3043        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3044                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3045        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3046        break;
3047      case AllLanes:
3048        E = Parser.getTok().getLoc();
3049        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3050                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3051        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3052                                                                S, E));
3053        break;
3054      case IndexedLane:
3055        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3056                                                               LaneIndex,
3057                                                               false, S, E));
3058        break;
3059      }
3060      return MatchOperand_Success;
3061    }
3062    Error(S, "vector register expected");
3063    return MatchOperand_ParseFail;
3064  }
3065
3066  if (Parser.getTok().isNot(AsmToken::LCurly))
3067    return MatchOperand_NoMatch;
3068
3069  Parser.Lex(); // Eat '{' token.
3070  SMLoc RegLoc = Parser.getTok().getLoc();
3071
3072  int Reg = tryParseRegister();
3073  if (Reg == -1) {
3074    Error(RegLoc, "register expected");
3075    return MatchOperand_ParseFail;
3076  }
3077  unsigned Count = 1;
3078  int Spacing = 0;
3079  unsigned FirstReg = Reg;
3080  // The list is of D registers, but we also allow Q regs and just interpret
3081  // them as the two D sub-registers.
3082  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3083    FirstReg = Reg = getDRegFromQReg(Reg);
3084    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3085                 // it's ambiguous with four-register single spaced.
3086    ++Reg;
3087    ++Count;
3088  }
3089  if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
3090    return MatchOperand_ParseFail;
3091
3092  while (Parser.getTok().is(AsmToken::Comma) ||
3093         Parser.getTok().is(AsmToken::Minus)) {
3094    if (Parser.getTok().is(AsmToken::Minus)) {
3095      if (!Spacing)
3096        Spacing = 1; // Register range implies a single spaced list.
3097      else if (Spacing == 2) {
3098        Error(Parser.getTok().getLoc(),
3099              "sequential registers in double spaced list");
3100        return MatchOperand_ParseFail;
3101      }
3102      Parser.Lex(); // Eat the minus.
3103      SMLoc EndLoc = Parser.getTok().getLoc();
3104      int EndReg = tryParseRegister();
3105      if (EndReg == -1) {
3106        Error(EndLoc, "register expected");
3107        return MatchOperand_ParseFail;
3108      }
3109      // Allow Q regs and just interpret them as the two D sub-registers.
3110      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3111        EndReg = getDRegFromQReg(EndReg) + 1;
3112      // If the register is the same as the start reg, there's nothing
3113      // more to do.
3114      if (Reg == EndReg)
3115        continue;
3116      // The register must be in the same register class as the first.
3117      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3118        Error(EndLoc, "invalid register in register list");
3119        return MatchOperand_ParseFail;
3120      }
3121      // Ranges must go from low to high.
3122      if (Reg > EndReg) {
3123        Error(EndLoc, "bad range in register list");
3124        return MatchOperand_ParseFail;
3125      }
3126      // Parse the lane specifier if present.
3127      VectorLaneTy NextLaneKind;
3128      unsigned NextLaneIndex;
3129      if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3130        return MatchOperand_ParseFail;
3131      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3132        Error(EndLoc, "mismatched lane index in register list");
3133        return MatchOperand_ParseFail;
3134      }
3135      EndLoc = Parser.getTok().getLoc();
3136
3137      // Add all the registers in the range to the register list.
3138      Count += EndReg - Reg;
3139      Reg = EndReg;
3140      continue;
3141    }
3142    Parser.Lex(); // Eat the comma.
3143    RegLoc = Parser.getTok().getLoc();
3144    int OldReg = Reg;
3145    Reg = tryParseRegister();
3146    if (Reg == -1) {
3147      Error(RegLoc, "register expected");
3148      return MatchOperand_ParseFail;
3149    }
3150    // vector register lists must be contiguous.
3151    // It's OK to use the enumeration values directly here rather, as the
3152    // VFP register classes have the enum sorted properly.
3153    //
3154    // The list is of D registers, but we also allow Q regs and just interpret
3155    // them as the two D sub-registers.
3156    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3157      if (!Spacing)
3158        Spacing = 1; // Register range implies a single spaced list.
3159      else if (Spacing == 2) {
3160        Error(RegLoc,
3161              "invalid register in double-spaced list (must be 'D' register')");
3162        return MatchOperand_ParseFail;
3163      }
3164      Reg = getDRegFromQReg(Reg);
3165      if (Reg != OldReg + 1) {
3166        Error(RegLoc, "non-contiguous register range");
3167        return MatchOperand_ParseFail;
3168      }
3169      ++Reg;
3170      Count += 2;
3171      // Parse the lane specifier if present.
3172      VectorLaneTy NextLaneKind;
3173      unsigned NextLaneIndex;
3174      SMLoc EndLoc = Parser.getTok().getLoc();
3175      if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3176        return MatchOperand_ParseFail;
3177      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3178        Error(EndLoc, "mismatched lane index in register list");
3179        return MatchOperand_ParseFail;
3180      }
3181      continue;
3182    }
3183    // Normal D register.
3184    // Figure out the register spacing (single or double) of the list if
3185    // we don't know it already.
3186    if (!Spacing)
3187      Spacing = 1 + (Reg == OldReg + 2);
3188
3189    // Just check that it's contiguous and keep going.
3190    if (Reg != OldReg + Spacing) {
3191      Error(RegLoc, "non-contiguous register range");
3192      return MatchOperand_ParseFail;
3193    }
3194    ++Count;
3195    // Parse the lane specifier if present.
3196    VectorLaneTy NextLaneKind;
3197    unsigned NextLaneIndex;
3198    SMLoc EndLoc = Parser.getTok().getLoc();
3199    if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3200      return MatchOperand_ParseFail;
3201    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3202      Error(EndLoc, "mismatched lane index in register list");
3203      return MatchOperand_ParseFail;
3204    }
3205  }
3206
3207  SMLoc E = Parser.getTok().getLoc();
3208  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3209    Error(E, "'}' expected");
3210    return MatchOperand_ParseFail;
3211  }
3212  Parser.Lex(); // Eat '}' token.
3213
3214  switch (LaneKind) {
3215  case NoLanes:
3216    // Two-register operands have been converted to the
3217    // composite register classes.
3218    if (Count == 2) {
3219      const MCRegisterClass *RC = (Spacing == 1) ?
3220        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3221        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3222      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3223    }
3224
3225    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3226                                                    (Spacing == 2), S, E));
3227    break;
3228  case AllLanes:
3229    // Two-register operands have been converted to the
3230    // composite register classes.
3231    if (Count == 2) {
3232      const MCRegisterClass *RC = (Spacing == 1) ?
3233        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3234        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3235      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3236    }
3237    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3238                                                            (Spacing == 2),
3239                                                            S, E));
3240    break;
3241  case IndexedLane:
3242    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3243                                                           LaneIndex,
3244                                                           (Spacing == 2),
3245                                                           S, E));
3246    break;
3247  }
3248  return MatchOperand_Success;
3249}
3250
3251/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3252ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3253parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3254  SMLoc S = Parser.getTok().getLoc();
3255  const AsmToken &Tok = Parser.getTok();
3256  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3257  StringRef OptStr = Tok.getString();
3258
3259  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
3260    .Case("sy",    ARM_MB::SY)
3261    .Case("st",    ARM_MB::ST)
3262    .Case("sh",    ARM_MB::ISH)
3263    .Case("ish",   ARM_MB::ISH)
3264    .Case("shst",  ARM_MB::ISHST)
3265    .Case("ishst", ARM_MB::ISHST)
3266    .Case("nsh",   ARM_MB::NSH)
3267    .Case("un",    ARM_MB::NSH)
3268    .Case("nshst", ARM_MB::NSHST)
3269    .Case("unst",  ARM_MB::NSHST)
3270    .Case("osh",   ARM_MB::OSH)
3271    .Case("oshst", ARM_MB::OSHST)
3272    .Default(~0U);
3273
3274  if (Opt == ~0U)
3275    return MatchOperand_NoMatch;
3276
3277  Parser.Lex(); // Eat identifier token.
3278  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3279  return MatchOperand_Success;
3280}
3281
3282/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3283ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3284parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3285  SMLoc S = Parser.getTok().getLoc();
3286  const AsmToken &Tok = Parser.getTok();
3287  if (!Tok.is(AsmToken::Identifier))
3288    return MatchOperand_NoMatch;
3289  StringRef IFlagsStr = Tok.getString();
3290
3291  // An iflags string of "none" is interpreted to mean that none of the AIF
3292  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3293  unsigned IFlags = 0;
3294  if (IFlagsStr != "none") {
3295        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3296      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3297        .Case("a", ARM_PROC::A)
3298        .Case("i", ARM_PROC::I)
3299        .Case("f", ARM_PROC::F)
3300        .Default(~0U);
3301
3302      // If some specific iflag is already set, it means that some letter is
3303      // present more than once, this is not acceptable.
3304      if (Flag == ~0U || (IFlags & Flag))
3305        return MatchOperand_NoMatch;
3306
3307      IFlags |= Flag;
3308    }
3309  }
3310
3311  Parser.Lex(); // Eat identifier token.
3312  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3313  return MatchOperand_Success;
3314}
3315
3316/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3317ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3318parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3319  SMLoc S = Parser.getTok().getLoc();
3320  const AsmToken &Tok = Parser.getTok();
3321  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3322  StringRef Mask = Tok.getString();
3323
3324  if (isMClass()) {
3325    // See ARMv6-M 10.1.1
3326    std::string Name = Mask.lower();
3327    unsigned FlagsVal = StringSwitch<unsigned>(Name)
3328      // Note: in the documentation:
3329      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3330      //  for MSR APSR_nzcvq.
3331      // but we do make it an alias here.  This is so to get the "mask encoding"
3332      // bits correct on MSR APSR writes.
3333      //
3334      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3335      // should really only be allowed when writing a special register.  Note
3336      // they get dropped in the MRS instruction reading a special register as
3337      // the SYSm field is only 8 bits.
3338      //
3339      // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3340      // includes the DSP extension but that is not checked.
3341      .Case("apsr", 0x800)
3342      .Case("apsr_nzcvq", 0x800)
3343      .Case("apsr_g", 0x400)
3344      .Case("apsr_nzcvqg", 0xc00)
3345      .Case("iapsr", 0x801)
3346      .Case("iapsr_nzcvq", 0x801)
3347      .Case("iapsr_g", 0x401)
3348      .Case("iapsr_nzcvqg", 0xc01)
3349      .Case("eapsr", 0x802)
3350      .Case("eapsr_nzcvq", 0x802)
3351      .Case("eapsr_g", 0x402)
3352      .Case("eapsr_nzcvqg", 0xc02)
3353      .Case("xpsr", 0x803)
3354      .Case("xpsr_nzcvq", 0x803)
3355      .Case("xpsr_g", 0x403)
3356      .Case("xpsr_nzcvqg", 0xc03)
3357      .Case("ipsr", 5)
3358      .Case("epsr", 6)
3359      .Case("iepsr", 7)
3360      .Case("msp", 8)
3361      .Case("psp", 9)
3362      .Case("primask", 16)
3363      .Case("basepri", 17)
3364      .Case("basepri_max", 18)
3365      .Case("faultmask", 19)
3366      .Case("control", 20)
3367      .Default(~0U);
3368
3369    if (FlagsVal == ~0U)
3370      return MatchOperand_NoMatch;
3371
3372    if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
3373      // basepri, basepri_max and faultmask only valid for V7m.
3374      return MatchOperand_NoMatch;
3375
3376    Parser.Lex(); // Eat identifier token.
3377    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3378    return MatchOperand_Success;
3379  }
3380
3381  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3382  size_t Start = 0, Next = Mask.find('_');
3383  StringRef Flags = "";
3384  std::string SpecReg = Mask.slice(Start, Next).lower();
3385  if (Next != StringRef::npos)
3386    Flags = Mask.slice(Next+1, Mask.size());
3387
3388  // FlagsVal contains the complete mask:
3389  // 3-0: Mask
3390  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3391  unsigned FlagsVal = 0;
3392
3393  if (SpecReg == "apsr") {
3394    FlagsVal = StringSwitch<unsigned>(Flags)
3395    .Case("nzcvq",  0x8) // same as CPSR_f
3396    .Case("g",      0x4) // same as CPSR_s
3397    .Case("nzcvqg", 0xc) // same as CPSR_fs
3398    .Default(~0U);
3399
3400    if (FlagsVal == ~0U) {
3401      if (!Flags.empty())
3402        return MatchOperand_NoMatch;
3403      else
3404        FlagsVal = 8; // No flag
3405    }
3406  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3407    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3408    if (Flags == "all" || Flags == "")
3409      Flags = "fc";
3410    for (int i = 0, e = Flags.size(); i != e; ++i) {
3411      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3412      .Case("c", 1)
3413      .Case("x", 2)
3414      .Case("s", 4)
3415      .Case("f", 8)
3416      .Default(~0U);
3417
3418      // If some specific flag is already set, it means that some letter is
3419      // present more than once, this is not acceptable.
3420      if (FlagsVal == ~0U || (FlagsVal & Flag))
3421        return MatchOperand_NoMatch;
3422      FlagsVal |= Flag;
3423    }
3424  } else // No match for special register.
3425    return MatchOperand_NoMatch;
3426
3427  // Special register without flags is NOT equivalent to "fc" flags.
3428  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3429  // two lines would enable gas compatibility at the expense of breaking
3430  // round-tripping.
3431  //
3432  // if (!FlagsVal)
3433  //  FlagsVal = 0x9;
3434
3435  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3436  if (SpecReg == "spsr")
3437    FlagsVal |= 16;
3438
3439  Parser.Lex(); // Eat identifier token.
3440  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3441  return MatchOperand_Success;
3442}
3443
3444ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3445parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3446            int Low, int High) {
3447  const AsmToken &Tok = Parser.getTok();
3448  if (Tok.isNot(AsmToken::Identifier)) {
3449    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3450    return MatchOperand_ParseFail;
3451  }
3452  StringRef ShiftName = Tok.getString();
3453  std::string LowerOp = Op.lower();
3454  std::string UpperOp = Op.upper();
3455  if (ShiftName != LowerOp && ShiftName != UpperOp) {
3456    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3457    return MatchOperand_ParseFail;
3458  }
3459  Parser.Lex(); // Eat shift type token.
3460
3461  // There must be a '#' and a shift amount.
3462  if (Parser.getTok().isNot(AsmToken::Hash) &&
3463      Parser.getTok().isNot(AsmToken::Dollar)) {
3464    Error(Parser.getTok().getLoc(), "'#' expected");
3465    return MatchOperand_ParseFail;
3466  }
3467  Parser.Lex(); // Eat hash token.
3468
3469  const MCExpr *ShiftAmount;
3470  SMLoc Loc = Parser.getTok().getLoc();
3471  if (getParser().ParseExpression(ShiftAmount)) {
3472    Error(Loc, "illegal expression");
3473    return MatchOperand_ParseFail;
3474  }
3475  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3476  if (!CE) {
3477    Error(Loc, "constant expression expected");
3478    return MatchOperand_ParseFail;
3479  }
3480  int Val = CE->getValue();
3481  if (Val < Low || Val > High) {
3482    Error(Loc, "immediate value out of range");
3483    return MatchOperand_ParseFail;
3484  }
3485
3486  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3487
3488  return MatchOperand_Success;
3489}
3490
3491ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3492parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3493  const AsmToken &Tok = Parser.getTok();
3494  SMLoc S = Tok.getLoc();
3495  if (Tok.isNot(AsmToken::Identifier)) {
3496    Error(Tok.getLoc(), "'be' or 'le' operand expected");
3497    return MatchOperand_ParseFail;
3498  }
3499  int Val = StringSwitch<int>(Tok.getString())
3500    .Case("be", 1)
3501    .Case("le", 0)
3502    .Default(-1);
3503  Parser.Lex(); // Eat the token.
3504
3505  if (Val == -1) {
3506    Error(Tok.getLoc(), "'be' or 'le' operand expected");
3507    return MatchOperand_ParseFail;
3508  }
3509  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3510                                                                  getContext()),
3511                                           S, Parser.getTok().getLoc()));
3512  return MatchOperand_Success;
3513}
3514
3515/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3516/// instructions. Legal values are:
3517///     lsl #n  'n' in [0,31]
3518///     asr #n  'n' in [1,32]
3519///             n == 32 encoded as n == 0.
3520ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3521parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3522  const AsmToken &Tok = Parser.getTok();
3523  SMLoc S = Tok.getLoc();
3524  if (Tok.isNot(AsmToken::Identifier)) {
3525    Error(S, "shift operator 'asr' or 'lsl' expected");
3526    return MatchOperand_ParseFail;
3527  }
3528  StringRef ShiftName = Tok.getString();
3529  bool isASR;
3530  if (ShiftName == "lsl" || ShiftName == "LSL")
3531    isASR = false;
3532  else if (ShiftName == "asr" || ShiftName == "ASR")
3533    isASR = true;
3534  else {
3535    Error(S, "shift operator 'asr' or 'lsl' expected");
3536    return MatchOperand_ParseFail;
3537  }
3538  Parser.Lex(); // Eat the operator.
3539
3540  // A '#' and a shift amount.
3541  if (Parser.getTok().isNot(AsmToken::Hash) &&
3542      Parser.getTok().isNot(AsmToken::Dollar)) {
3543    Error(Parser.getTok().getLoc(), "'#' expected");
3544    return MatchOperand_ParseFail;
3545  }
3546  Parser.Lex(); // Eat hash token.
3547
3548  const MCExpr *ShiftAmount;
3549  SMLoc E = Parser.getTok().getLoc();
3550  if (getParser().ParseExpression(ShiftAmount)) {
3551    Error(E, "malformed shift expression");
3552    return MatchOperand_ParseFail;
3553  }
3554  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3555  if (!CE) {
3556    Error(E, "shift amount must be an immediate");
3557    return MatchOperand_ParseFail;
3558  }
3559
3560  int64_t Val = CE->getValue();
3561  if (isASR) {
3562    // Shift amount must be in [1,32]
3563    if (Val < 1 || Val > 32) {
3564      Error(E, "'asr' shift amount must be in range [1,32]");
3565      return MatchOperand_ParseFail;
3566    }
3567    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3568    if (isThumb() && Val == 32) {
3569      Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3570      return MatchOperand_ParseFail;
3571    }
3572    if (Val == 32) Val = 0;
3573  } else {
3574    // Shift amount must be in [1,32]
3575    if (Val < 0 || Val > 31) {
3576      Error(E, "'lsr' shift amount must be in range [0,31]");
3577      return MatchOperand_ParseFail;
3578    }
3579  }
3580
3581  E = Parser.getTok().getLoc();
3582  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3583
3584  return MatchOperand_Success;
3585}
3586
3587/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3588/// of instructions. Legal values are:
3589///     ror #n  'n' in {0, 8, 16, 24}
3590ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3591parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3592  const AsmToken &Tok = Parser.getTok();
3593  SMLoc S = Tok.getLoc();
3594  if (Tok.isNot(AsmToken::Identifier))
3595    return MatchOperand_NoMatch;
3596  StringRef ShiftName = Tok.getString();
3597  if (ShiftName != "ror" && ShiftName != "ROR")
3598    return MatchOperand_NoMatch;
3599  Parser.Lex(); // Eat the operator.
3600
3601  // A '#' and a rotate amount.
3602  if (Parser.getTok().isNot(AsmToken::Hash) &&
3603      Parser.getTok().isNot(AsmToken::Dollar)) {
3604    Error(Parser.getTok().getLoc(), "'#' expected");
3605    return MatchOperand_ParseFail;
3606  }
3607  Parser.Lex(); // Eat hash token.
3608
3609  const MCExpr *ShiftAmount;
3610  SMLoc E = Parser.getTok().getLoc();
3611  if (getParser().ParseExpression(ShiftAmount)) {
3612    Error(E, "malformed rotate expression");
3613    return MatchOperand_ParseFail;
3614  }
3615  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3616  if (!CE) {
3617    Error(E, "rotate amount must be an immediate");
3618    return MatchOperand_ParseFail;
3619  }
3620
3621  int64_t Val = CE->getValue();
3622  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3623  // normally, zero is represented in asm by omitting the rotate operand
3624  // entirely.
3625  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3626    Error(E, "'ror' rotate amount must be 8, 16, or 24");
3627    return MatchOperand_ParseFail;
3628  }
3629
3630  E = Parser.getTok().getLoc();
3631  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3632
3633  return MatchOperand_Success;
3634}
3635
3636ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3637parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3638  SMLoc S = Parser.getTok().getLoc();
3639  // The bitfield descriptor is really two operands, the LSB and the width.
3640  if (Parser.getTok().isNot(AsmToken::Hash) &&
3641      Parser.getTok().isNot(AsmToken::Dollar)) {
3642    Error(Parser.getTok().getLoc(), "'#' expected");
3643    return MatchOperand_ParseFail;
3644  }
3645  Parser.Lex(); // Eat hash token.
3646
3647  const MCExpr *LSBExpr;
3648  SMLoc E = Parser.getTok().getLoc();
3649  if (getParser().ParseExpression(LSBExpr)) {
3650    Error(E, "malformed immediate expression");
3651    return MatchOperand_ParseFail;
3652  }
3653  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3654  if (!CE) {
3655    Error(E, "'lsb' operand must be an immediate");
3656    return MatchOperand_ParseFail;
3657  }
3658
3659  int64_t LSB = CE->getValue();
3660  // The LSB must be in the range [0,31]
3661  if (LSB < 0 || LSB > 31) {
3662    Error(E, "'lsb' operand must be in the range [0,31]");
3663    return MatchOperand_ParseFail;
3664  }
3665  E = Parser.getTok().getLoc();
3666
3667  // Expect another immediate operand.
3668  if (Parser.getTok().isNot(AsmToken::Comma)) {
3669    Error(Parser.getTok().getLoc(), "too few operands");
3670    return MatchOperand_ParseFail;
3671  }
3672  Parser.Lex(); // Eat hash token.
3673  if (Parser.getTok().isNot(AsmToken::Hash) &&
3674      Parser.getTok().isNot(AsmToken::Dollar)) {
3675    Error(Parser.getTok().getLoc(), "'#' expected");
3676    return MatchOperand_ParseFail;
3677  }
3678  Parser.Lex(); // Eat hash token.
3679
3680  const MCExpr *WidthExpr;
3681  if (getParser().ParseExpression(WidthExpr)) {
3682    Error(E, "malformed immediate expression");
3683    return MatchOperand_ParseFail;
3684  }
3685  CE = dyn_cast<MCConstantExpr>(WidthExpr);
3686  if (!CE) {
3687    Error(E, "'width' operand must be an immediate");
3688    return MatchOperand_ParseFail;
3689  }
3690
3691  int64_t Width = CE->getValue();
3692  // The LSB must be in the range [1,32-lsb]
3693  if (Width < 1 || Width > 32 - LSB) {
3694    Error(E, "'width' operand must be in the range [1,32-lsb]");
3695    return MatchOperand_ParseFail;
3696  }
3697  E = Parser.getTok().getLoc();
3698
3699  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3700
3701  return MatchOperand_Success;
3702}
3703
3704ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3705parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3706  // Check for a post-index addressing register operand. Specifically:
3707  // postidx_reg := '+' register {, shift}
3708  //              | '-' register {, shift}
3709  //              | register {, shift}
3710
3711  // This method must return MatchOperand_NoMatch without consuming any tokens
3712  // in the case where there is no match, as other alternatives take other
3713  // parse methods.
3714  AsmToken Tok = Parser.getTok();
3715  SMLoc S = Tok.getLoc();
3716  bool haveEaten = false;
3717  bool isAdd = true;
3718  int Reg = -1;
3719  if (Tok.is(AsmToken::Plus)) {
3720    Parser.Lex(); // Eat the '+' token.
3721    haveEaten = true;
3722  } else if (Tok.is(AsmToken::Minus)) {
3723    Parser.Lex(); // Eat the '-' token.
3724    isAdd = false;
3725    haveEaten = true;
3726  }
3727  if (Parser.getTok().is(AsmToken::Identifier))
3728    Reg = tryParseRegister();
3729  if (Reg == -1) {
3730    if (!haveEaten)
3731      return MatchOperand_NoMatch;
3732    Error(Parser.getTok().getLoc(), "register expected");
3733    return MatchOperand_ParseFail;
3734  }
3735  SMLoc E = Parser.getTok().getLoc();
3736
3737  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3738  unsigned ShiftImm = 0;
3739  if (Parser.getTok().is(AsmToken::Comma)) {
3740    Parser.Lex(); // Eat the ','.
3741    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3742      return MatchOperand_ParseFail;
3743  }
3744
3745  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3746                                                  ShiftImm, S, E));
3747
3748  return MatchOperand_Success;
3749}
3750
3751ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3752parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3753  // Check for a post-index addressing register operand. Specifically:
3754  // am3offset := '+' register
3755  //              | '-' register
3756  //              | register
3757  //              | # imm
3758  //              | # + imm
3759  //              | # - imm
3760
3761  // This method must return MatchOperand_NoMatch without consuming any tokens
3762  // in the case where there is no match, as other alternatives take other
3763  // parse methods.
3764  AsmToken Tok = Parser.getTok();
3765  SMLoc S = Tok.getLoc();
3766
3767  // Do immediates first, as we always parse those if we have a '#'.
3768  if (Parser.getTok().is(AsmToken::Hash) ||
3769      Parser.getTok().is(AsmToken::Dollar)) {
3770    Parser.Lex(); // Eat the '#'.
3771    // Explicitly look for a '-', as we need to encode negative zero
3772    // differently.
3773    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3774    const MCExpr *Offset;
3775    if (getParser().ParseExpression(Offset))
3776      return MatchOperand_ParseFail;
3777    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3778    if (!CE) {
3779      Error(S, "constant expression expected");
3780      return MatchOperand_ParseFail;
3781    }
3782    SMLoc E = Tok.getLoc();
3783    // Negative zero is encoded as the flag value INT32_MIN.
3784    int32_t Val = CE->getValue();
3785    if (isNegative && Val == 0)
3786      Val = INT32_MIN;
3787
3788    Operands.push_back(
3789      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3790
3791    return MatchOperand_Success;
3792  }
3793
3794
3795  bool haveEaten = false;
3796  bool isAdd = true;
3797  int Reg = -1;
3798  if (Tok.is(AsmToken::Plus)) {
3799    Parser.Lex(); // Eat the '+' token.
3800    haveEaten = true;
3801  } else if (Tok.is(AsmToken::Minus)) {
3802    Parser.Lex(); // Eat the '-' token.
3803    isAdd = false;
3804    haveEaten = true;
3805  }
3806  if (Parser.getTok().is(AsmToken::Identifier))
3807    Reg = tryParseRegister();
3808  if (Reg == -1) {
3809    if (!haveEaten)
3810      return MatchOperand_NoMatch;
3811    Error(Parser.getTok().getLoc(), "register expected");
3812    return MatchOperand_ParseFail;
3813  }
3814  SMLoc E = Parser.getTok().getLoc();
3815
3816  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3817                                                  0, S, E));
3818
3819  return MatchOperand_Success;
3820}
3821
3822/// cvtT2LdrdPre - Convert parsed operands to MCInst.
3823/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3824/// when they refer multiple MIOperands inside a single one.
3825bool ARMAsmParser::
3826cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3827             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3828  // Rt, Rt2
3829  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3830  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3831  // Create a writeback register dummy placeholder.
3832  Inst.addOperand(MCOperand::CreateReg(0));
3833  // addr
3834  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3835  // pred
3836  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3837  return true;
3838}
3839
3840/// cvtT2StrdPre - Convert parsed operands to MCInst.
3841/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3842/// when they refer multiple MIOperands inside a single one.
3843bool ARMAsmParser::
3844cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3845             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3846  // Create a writeback register dummy placeholder.
3847  Inst.addOperand(MCOperand::CreateReg(0));
3848  // Rt, Rt2
3849  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3850  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3851  // addr
3852  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3853  // pred
3854  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3855  return true;
3856}
3857
3858/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3859/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3860/// when they refer multiple MIOperands inside a single one.
3861bool ARMAsmParser::
3862cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3863                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3864  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3865
3866  // Create a writeback register dummy placeholder.
3867  Inst.addOperand(MCOperand::CreateImm(0));
3868
3869  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3870  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3871  return true;
3872}
3873
3874/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3875/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3876/// when they refer multiple MIOperands inside a single one.
3877bool ARMAsmParser::
3878cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3879                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3880  // Create a writeback register dummy placeholder.
3881  Inst.addOperand(MCOperand::CreateImm(0));
3882  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3883  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3884  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3885  return true;
3886}
3887
3888/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3889/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3890/// when they refer multiple MIOperands inside a single one.
3891bool ARMAsmParser::
3892cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3893                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3894  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3895
3896  // Create a writeback register dummy placeholder.
3897  Inst.addOperand(MCOperand::CreateImm(0));
3898
3899  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3900  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3901  return true;
3902}
3903
3904/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3905/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3906/// when they refer multiple MIOperands inside a single one.
3907bool ARMAsmParser::
3908cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3909                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3910  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3911
3912  // Create a writeback register dummy placeholder.
3913  Inst.addOperand(MCOperand::CreateImm(0));
3914
3915  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3916  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3917  return true;
3918}
3919
3920
3921/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3922/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3923/// when they refer multiple MIOperands inside a single one.
3924bool ARMAsmParser::
3925cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3926                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3927  // Create a writeback register dummy placeholder.
3928  Inst.addOperand(MCOperand::CreateImm(0));
3929  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3930  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3931  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3932  return true;
3933}
3934
3935/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3936/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3937/// when they refer multiple MIOperands inside a single one.
3938bool ARMAsmParser::
3939cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3940                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3941  // Create a writeback register dummy placeholder.
3942  Inst.addOperand(MCOperand::CreateImm(0));
3943  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3944  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3945  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3946  return true;
3947}
3948
3949/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3950/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3951/// when they refer multiple MIOperands inside a single one.
3952bool ARMAsmParser::
3953cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3954                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3955  // Create a writeback register dummy placeholder.
3956  Inst.addOperand(MCOperand::CreateImm(0));
3957  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3958  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3959  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3960  return true;
3961}
3962
3963/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3964/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3965/// when they refer multiple MIOperands inside a single one.
3966bool ARMAsmParser::
3967cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3968                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3969  // Rt
3970  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3971  // Create a writeback register dummy placeholder.
3972  Inst.addOperand(MCOperand::CreateImm(0));
3973  // addr
3974  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3975  // offset
3976  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3977  // pred
3978  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3979  return true;
3980}
3981
3982/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3983/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3984/// when they refer multiple MIOperands inside a single one.
3985bool ARMAsmParser::
3986cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3987                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3988  // Rt
3989  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3990  // Create a writeback register dummy placeholder.
3991  Inst.addOperand(MCOperand::CreateImm(0));
3992  // addr
3993  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3994  // offset
3995  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3996  // pred
3997  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3998  return true;
3999}
4000
4001/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4002/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4003/// when they refer multiple MIOperands inside a single one.
4004bool ARMAsmParser::
4005cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
4006                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4007  // Create a writeback register dummy placeholder.
4008  Inst.addOperand(MCOperand::CreateImm(0));
4009  // Rt
4010  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4011  // addr
4012  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4013  // offset
4014  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4015  // pred
4016  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4017  return true;
4018}
4019
4020/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4021/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4022/// when they refer multiple MIOperands inside a single one.
4023bool ARMAsmParser::
4024cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
4025                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4026  // Create a writeback register dummy placeholder.
4027  Inst.addOperand(MCOperand::CreateImm(0));
4028  // Rt
4029  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4030  // addr
4031  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4032  // offset
4033  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4034  // pred
4035  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4036  return true;
4037}
4038
4039/// cvtLdrdPre - Convert parsed operands to MCInst.
4040/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4041/// when they refer multiple MIOperands inside a single one.
4042bool ARMAsmParser::
4043cvtLdrdPre(MCInst &Inst, unsigned Opcode,
4044           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4045  // Rt, Rt2
4046  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4047  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4048  // Create a writeback register dummy placeholder.
4049  Inst.addOperand(MCOperand::CreateImm(0));
4050  // addr
4051  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4052  // pred
4053  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4054  return true;
4055}
4056
4057/// cvtStrdPre - Convert parsed operands to MCInst.
4058/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4059/// when they refer multiple MIOperands inside a single one.
4060bool ARMAsmParser::
4061cvtStrdPre(MCInst &Inst, unsigned Opcode,
4062           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4063  // Create a writeback register dummy placeholder.
4064  Inst.addOperand(MCOperand::CreateImm(0));
4065  // Rt, Rt2
4066  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4067  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4068  // addr
4069  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4070  // pred
4071  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4072  return true;
4073}
4074
4075/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4076/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4077/// when they refer multiple MIOperands inside a single one.
4078bool ARMAsmParser::
4079cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4080                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4081  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4082  // Create a writeback register dummy placeholder.
4083  Inst.addOperand(MCOperand::CreateImm(0));
4084  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4085  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4086  return true;
4087}
4088
4089/// cvtThumbMultiple- Convert parsed operands to MCInst.
4090/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4091/// when they refer multiple MIOperands inside a single one.
4092bool ARMAsmParser::
4093cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
4094           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4095  // The second source operand must be the same register as the destination
4096  // operand.
4097  if (Operands.size() == 6 &&
4098      (((ARMOperand*)Operands[3])->getReg() !=
4099       ((ARMOperand*)Operands[5])->getReg()) &&
4100      (((ARMOperand*)Operands[3])->getReg() !=
4101       ((ARMOperand*)Operands[4])->getReg())) {
4102    Error(Operands[3]->getStartLoc(),
4103          "destination register must match source register");
4104    return false;
4105  }
4106  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4107  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4108  // If we have a three-operand form, make sure to set Rn to be the operand
4109  // that isn't the same as Rd.
4110  unsigned RegOp = 4;
4111  if (Operands.size() == 6 &&
4112      ((ARMOperand*)Operands[4])->getReg() ==
4113        ((ARMOperand*)Operands[3])->getReg())
4114    RegOp = 5;
4115  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4116  Inst.addOperand(Inst.getOperand(0));
4117  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4118
4119  return true;
4120}
4121
4122bool ARMAsmParser::
4123cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
4124              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4125  // Vd
4126  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4127  // Create a writeback register dummy placeholder.
4128  Inst.addOperand(MCOperand::CreateImm(0));
4129  // Vn
4130  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4131  // pred
4132  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4133  return true;
4134}
4135
4136bool ARMAsmParser::
4137cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
4138                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4139  // Vd
4140  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4141  // Create a writeback register dummy placeholder.
4142  Inst.addOperand(MCOperand::CreateImm(0));
4143  // Vn
4144  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4145  // Vm
4146  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4147  // pred
4148  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4149  return true;
4150}
4151
4152bool ARMAsmParser::
4153cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
4154              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4155  // Create a writeback register dummy placeholder.
4156  Inst.addOperand(MCOperand::CreateImm(0));
4157  // Vn
4158  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4159  // Vt
4160  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4161  // pred
4162  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4163  return true;
4164}
4165
4166bool ARMAsmParser::
4167cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
4168                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4169  // Create a writeback register dummy placeholder.
4170  Inst.addOperand(MCOperand::CreateImm(0));
4171  // Vn
4172  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4173  // Vm
4174  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4175  // Vt
4176  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4177  // pred
4178  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4179  return true;
4180}
4181
4182/// Parse an ARM memory expression, return false if successful else return true
4183/// or an error.  The first token must be a '[' when called.
4184bool ARMAsmParser::
4185parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4186  SMLoc S, E;
4187  assert(Parser.getTok().is(AsmToken::LBrac) &&
4188         "Token is not a Left Bracket");
4189  S = Parser.getTok().getLoc();
4190  Parser.Lex(); // Eat left bracket token.
4191
4192  const AsmToken &BaseRegTok = Parser.getTok();
4193  int BaseRegNum = tryParseRegister();
4194  if (BaseRegNum == -1)
4195    return Error(BaseRegTok.getLoc(), "register expected");
4196
4197  // The next token must either be a comma or a closing bracket.
4198  const AsmToken &Tok = Parser.getTok();
4199  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4200    return Error(Tok.getLoc(), "malformed memory operand");
4201
4202  if (Tok.is(AsmToken::RBrac)) {
4203    E = Tok.getLoc();
4204    Parser.Lex(); // Eat right bracket token.
4205
4206    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4207                                             0, 0, false, S, E));
4208
4209    // If there's a pre-indexing writeback marker, '!', just add it as a token
4210    // operand. It's rather odd, but syntactically valid.
4211    if (Parser.getTok().is(AsmToken::Exclaim)) {
4212      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4213      Parser.Lex(); // Eat the '!'.
4214    }
4215
4216    return false;
4217  }
4218
4219  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4220  Parser.Lex(); // Eat the comma.
4221
4222  // If we have a ':', it's an alignment specifier.
4223  if (Parser.getTok().is(AsmToken::Colon)) {
4224    Parser.Lex(); // Eat the ':'.
4225    E = Parser.getTok().getLoc();
4226
4227    const MCExpr *Expr;
4228    if (getParser().ParseExpression(Expr))
4229     return true;
4230
4231    // The expression has to be a constant. Memory references with relocations
4232    // don't come through here, as they use the <label> forms of the relevant
4233    // instructions.
4234    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4235    if (!CE)
4236      return Error (E, "constant expression expected");
4237
4238    unsigned Align = 0;
4239    switch (CE->getValue()) {
4240    default:
4241      return Error(E,
4242                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4243    case 16:  Align = 2; break;
4244    case 32:  Align = 4; break;
4245    case 64:  Align = 8; break;
4246    case 128: Align = 16; break;
4247    case 256: Align = 32; break;
4248    }
4249
4250    // Now we should have the closing ']'
4251    E = Parser.getTok().getLoc();
4252    if (Parser.getTok().isNot(AsmToken::RBrac))
4253      return Error(E, "']' expected");
4254    Parser.Lex(); // Eat right bracket token.
4255
4256    // Don't worry about range checking the value here. That's handled by
4257    // the is*() predicates.
4258    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4259                                             ARM_AM::no_shift, 0, Align,
4260                                             false, S, E));
4261
4262    // If there's a pre-indexing writeback marker, '!', just add it as a token
4263    // operand.
4264    if (Parser.getTok().is(AsmToken::Exclaim)) {
4265      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4266      Parser.Lex(); // Eat the '!'.
4267    }
4268
4269    return false;
4270  }
4271
4272  // If we have a '#', it's an immediate offset, else assume it's a register
4273  // offset. Be friendly and also accept a plain integer (without a leading
4274  // hash) for gas compatibility.
4275  if (Parser.getTok().is(AsmToken::Hash) ||
4276      Parser.getTok().is(AsmToken::Dollar) ||
4277      Parser.getTok().is(AsmToken::Integer)) {
4278    if (Parser.getTok().isNot(AsmToken::Integer))
4279      Parser.Lex(); // Eat the '#'.
4280    E = Parser.getTok().getLoc();
4281
4282    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4283    const MCExpr *Offset;
4284    if (getParser().ParseExpression(Offset))
4285     return true;
4286
4287    // The expression has to be a constant. Memory references with relocations
4288    // don't come through here, as they use the <label> forms of the relevant
4289    // instructions.
4290    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4291    if (!CE)
4292      return Error (E, "constant expression expected");
4293
4294    // If the constant was #-0, represent it as INT32_MIN.
4295    int32_t Val = CE->getValue();
4296    if (isNegative && Val == 0)
4297      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4298
4299    // Now we should have the closing ']'
4300    E = Parser.getTok().getLoc();
4301    if (Parser.getTok().isNot(AsmToken::RBrac))
4302      return Error(E, "']' expected");
4303    Parser.Lex(); // Eat right bracket token.
4304
4305    // Don't worry about range checking the value here. That's handled by
4306    // the is*() predicates.
4307    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4308                                             ARM_AM::no_shift, 0, 0,
4309                                             false, S, E));
4310
4311    // If there's a pre-indexing writeback marker, '!', just add it as a token
4312    // operand.
4313    if (Parser.getTok().is(AsmToken::Exclaim)) {
4314      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4315      Parser.Lex(); // Eat the '!'.
4316    }
4317
4318    return false;
4319  }
4320
4321  // The register offset is optionally preceded by a '+' or '-'
4322  bool isNegative = false;
4323  if (Parser.getTok().is(AsmToken::Minus)) {
4324    isNegative = true;
4325    Parser.Lex(); // Eat the '-'.
4326  } else if (Parser.getTok().is(AsmToken::Plus)) {
4327    // Nothing to do.
4328    Parser.Lex(); // Eat the '+'.
4329  }
4330
4331  E = Parser.getTok().getLoc();
4332  int OffsetRegNum = tryParseRegister();
4333  if (OffsetRegNum == -1)
4334    return Error(E, "register expected");
4335
4336  // If there's a shift operator, handle it.
4337  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4338  unsigned ShiftImm = 0;
4339  if (Parser.getTok().is(AsmToken::Comma)) {
4340    Parser.Lex(); // Eat the ','.
4341    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4342      return true;
4343  }
4344
4345  // Now we should have the closing ']'
4346  E = Parser.getTok().getLoc();
4347  if (Parser.getTok().isNot(AsmToken::RBrac))
4348    return Error(E, "']' expected");
4349  Parser.Lex(); // Eat right bracket token.
4350
4351  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4352                                           ShiftType, ShiftImm, 0, isNegative,
4353                                           S, E));
4354
4355  // If there's a pre-indexing writeback marker, '!', just add it as a token
4356  // operand.
4357  if (Parser.getTok().is(AsmToken::Exclaim)) {
4358    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4359    Parser.Lex(); // Eat the '!'.
4360  }
4361
4362  return false;
4363}
4364
4365/// parseMemRegOffsetShift - one of these two:
4366///   ( lsl | lsr | asr | ror ) , # shift_amount
4367///   rrx
4368/// return true if it parses a shift otherwise it returns false.
4369bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4370                                          unsigned &Amount) {
4371  SMLoc Loc = Parser.getTok().getLoc();
4372  const AsmToken &Tok = Parser.getTok();
4373  if (Tok.isNot(AsmToken::Identifier))
4374    return true;
4375  StringRef ShiftName = Tok.getString();
4376  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4377      ShiftName == "asl" || ShiftName == "ASL")
4378    St = ARM_AM::lsl;
4379  else if (ShiftName == "lsr" || ShiftName == "LSR")
4380    St = ARM_AM::lsr;
4381  else if (ShiftName == "asr" || ShiftName == "ASR")
4382    St = ARM_AM::asr;
4383  else if (ShiftName == "ror" || ShiftName == "ROR")
4384    St = ARM_AM::ror;
4385  else if (ShiftName == "rrx" || ShiftName == "RRX")
4386    St = ARM_AM::rrx;
4387  else
4388    return Error(Loc, "illegal shift operator");
4389  Parser.Lex(); // Eat shift type token.
4390
4391  // rrx stands alone.
4392  Amount = 0;
4393  if (St != ARM_AM::rrx) {
4394    Loc = Parser.getTok().getLoc();
4395    // A '#' and a shift amount.
4396    const AsmToken &HashTok = Parser.getTok();
4397    if (HashTok.isNot(AsmToken::Hash) &&
4398        HashTok.isNot(AsmToken::Dollar))
4399      return Error(HashTok.getLoc(), "'#' expected");
4400    Parser.Lex(); // Eat hash token.
4401
4402    const MCExpr *Expr;
4403    if (getParser().ParseExpression(Expr))
4404      return true;
4405    // Range check the immediate.
4406    // lsl, ror: 0 <= imm <= 31
4407    // lsr, asr: 0 <= imm <= 32
4408    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4409    if (!CE)
4410      return Error(Loc, "shift amount must be an immediate");
4411    int64_t Imm = CE->getValue();
4412    if (Imm < 0 ||
4413        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4414        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4415      return Error(Loc, "immediate shift value out of range");
4416    Amount = Imm;
4417  }
4418
4419  return false;
4420}
4421
4422/// parseFPImm - A floating point immediate expression operand.
4423ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4424parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4425  // Anything that can accept a floating point constant as an operand
4426  // needs to go through here, as the regular ParseExpression is
4427  // integer only.
4428  //
4429  // This routine still creates a generic Immediate operand, containing
4430  // a bitcast of the 64-bit floating point value. The various operands
4431  // that accept floats can check whether the value is valid for them
4432  // via the standard is*() predicates.
4433
4434  SMLoc S = Parser.getTok().getLoc();
4435
4436  if (Parser.getTok().isNot(AsmToken::Hash) &&
4437      Parser.getTok().isNot(AsmToken::Dollar))
4438    return MatchOperand_NoMatch;
4439
4440  // Disambiguate the VMOV forms that can accept an FP immediate.
4441  // vmov.f32 <sreg>, #imm
4442  // vmov.f64 <dreg>, #imm
4443  // vmov.f32 <dreg>, #imm  @ vector f32x2
4444  // vmov.f32 <qreg>, #imm  @ vector f32x4
4445  //
4446  // There are also the NEON VMOV instructions which expect an
4447  // integer constant. Make sure we don't try to parse an FPImm
4448  // for these:
4449  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4450  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4451  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4452                           TyOp->getToken() != ".f64"))
4453    return MatchOperand_NoMatch;
4454
4455  Parser.Lex(); // Eat the '#'.
4456
4457  // Handle negation, as that still comes through as a separate token.
4458  bool isNegative = false;
4459  if (Parser.getTok().is(AsmToken::Minus)) {
4460    isNegative = true;
4461    Parser.Lex();
4462  }
4463  const AsmToken &Tok = Parser.getTok();
4464  SMLoc Loc = Tok.getLoc();
4465  if (Tok.is(AsmToken::Real)) {
4466    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4467    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4468    // If we had a '-' in front, toggle the sign bit.
4469    IntVal ^= (uint64_t)isNegative << 31;
4470    Parser.Lex(); // Eat the token.
4471    Operands.push_back(ARMOperand::CreateImm(
4472          MCConstantExpr::Create(IntVal, getContext()),
4473          S, Parser.getTok().getLoc()));
4474    return MatchOperand_Success;
4475  }
4476  // Also handle plain integers. Instructions which allow floating point
4477  // immediates also allow a raw encoded 8-bit value.
4478  if (Tok.is(AsmToken::Integer)) {
4479    int64_t Val = Tok.getIntVal();
4480    Parser.Lex(); // Eat the token.
4481    if (Val > 255 || Val < 0) {
4482      Error(Loc, "encoded floating point value out of range");
4483      return MatchOperand_ParseFail;
4484    }
4485    double RealVal = ARM_AM::getFPImmFloat(Val);
4486    Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4487    Operands.push_back(ARMOperand::CreateImm(
4488        MCConstantExpr::Create(Val, getContext()), S,
4489        Parser.getTok().getLoc()));
4490    return MatchOperand_Success;
4491  }
4492
4493  Error(Loc, "invalid floating point immediate");
4494  return MatchOperand_ParseFail;
4495}
4496
4497/// Parse a arm instruction operand.  For now this parses the operand regardless
4498/// of the mnemonic.
4499bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4500                                StringRef Mnemonic) {
4501  SMLoc S, E;
4502
4503  // Check if the current operand has a custom associated parser, if so, try to
4504  // custom parse the operand, or fallback to the general approach.
4505  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4506  if (ResTy == MatchOperand_Success)
4507    return false;
4508  // If there wasn't a custom match, try the generic matcher below. Otherwise,
4509  // there was a match, but an error occurred, in which case, just return that
4510  // the operand parsing failed.
4511  if (ResTy == MatchOperand_ParseFail)
4512    return true;
4513
4514  switch (getLexer().getKind()) {
4515  default:
4516    Error(Parser.getTok().getLoc(), "unexpected token in operand");
4517    return true;
4518  case AsmToken::Identifier: {
4519    if (!tryParseRegisterWithWriteBack(Operands))
4520      return false;
4521    int Res = tryParseShiftRegister(Operands);
4522    if (Res == 0) // success
4523      return false;
4524    else if (Res == -1) // irrecoverable error
4525      return true;
4526    // If this is VMRS, check for the apsr_nzcv operand.
4527    if (Mnemonic == "vmrs" &&
4528        Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4529      S = Parser.getTok().getLoc();
4530      Parser.Lex();
4531      Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4532      return false;
4533    }
4534
4535    // Fall though for the Identifier case that is not a register or a
4536    // special name.
4537  }
4538  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4539  case AsmToken::Integer: // things like 1f and 2b as a branch targets
4540  case AsmToken::String:  // quoted label names.
4541  case AsmToken::Dot: {   // . as a branch target
4542    // This was not a register so parse other operands that start with an
4543    // identifier (like labels) as expressions and create them as immediates.
4544    const MCExpr *IdVal;
4545    S = Parser.getTok().getLoc();
4546    if (getParser().ParseExpression(IdVal))
4547      return true;
4548    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4549    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4550    return false;
4551  }
4552  case AsmToken::LBrac:
4553    return parseMemory(Operands);
4554  case AsmToken::LCurly:
4555    return parseRegisterList(Operands);
4556  case AsmToken::Dollar:
4557  case AsmToken::Hash: {
4558    // #42 -> immediate.
4559    S = Parser.getTok().getLoc();
4560    Parser.Lex();
4561
4562    if (Parser.getTok().isNot(AsmToken::Colon)) {
4563      bool isNegative = Parser.getTok().is(AsmToken::Minus);
4564      const MCExpr *ImmVal;
4565      if (getParser().ParseExpression(ImmVal))
4566        return true;
4567      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4568      if (CE) {
4569        int32_t Val = CE->getValue();
4570        if (isNegative && Val == 0)
4571          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4572      }
4573      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4574      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4575      return false;
4576    }
4577    // w/ a ':' after the '#', it's just like a plain ':'.
4578    // FALLTHROUGH
4579  }
4580  case AsmToken::Colon: {
4581    // ":lower16:" and ":upper16:" expression prefixes
4582    // FIXME: Check it's an expression prefix,
4583    // e.g. (FOO - :lower16:BAR) isn't legal.
4584    ARMMCExpr::VariantKind RefKind;
4585    if (parsePrefix(RefKind))
4586      return true;
4587
4588    const MCExpr *SubExprVal;
4589    if (getParser().ParseExpression(SubExprVal))
4590      return true;
4591
4592    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4593                                                   getContext());
4594    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4595    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4596    return false;
4597  }
4598  }
4599}
4600
4601// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4602//  :lower16: and :upper16:.
4603bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4604  RefKind = ARMMCExpr::VK_ARM_None;
4605
4606  // :lower16: and :upper16: modifiers
4607  assert(getLexer().is(AsmToken::Colon) && "expected a :");
4608  Parser.Lex(); // Eat ':'
4609
4610  if (getLexer().isNot(AsmToken::Identifier)) {
4611    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4612    return true;
4613  }
4614
4615  StringRef IDVal = Parser.getTok().getIdentifier();
4616  if (IDVal == "lower16") {
4617    RefKind = ARMMCExpr::VK_ARM_LO16;
4618  } else if (IDVal == "upper16") {
4619    RefKind = ARMMCExpr::VK_ARM_HI16;
4620  } else {
4621    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4622    return true;
4623  }
4624  Parser.Lex();
4625
4626  if (getLexer().isNot(AsmToken::Colon)) {
4627    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4628    return true;
4629  }
4630  Parser.Lex(); // Eat the last ':'
4631  return false;
4632}
4633
4634/// \brief Given a mnemonic, split out possible predication code and carry
4635/// setting letters to form a canonical mnemonic and flags.
4636//
4637// FIXME: Would be nice to autogen this.
4638// FIXME: This is a bit of a maze of special cases.
4639StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4640                                      unsigned &PredicationCode,
4641                                      bool &CarrySetting,
4642                                      unsigned &ProcessorIMod,
4643                                      StringRef &ITMask) {
4644  PredicationCode = ARMCC::AL;
4645  CarrySetting = false;
4646  ProcessorIMod = 0;
4647
4648  // Ignore some mnemonics we know aren't predicated forms.
4649  //
4650  // FIXME: Would be nice to autogen this.
4651  if ((Mnemonic == "movs" && isThumb()) ||
4652      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4653      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4654      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4655      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4656      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4657      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4658      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4659      Mnemonic == "fmuls")
4660    return Mnemonic;
4661
4662  // First, split out any predication code. Ignore mnemonics we know aren't
4663  // predicated but do have a carry-set and so weren't caught above.
4664  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4665      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4666      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4667      Mnemonic != "sbcs" && Mnemonic != "rscs") {
4668    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4669      .Case("eq", ARMCC::EQ)
4670      .Case("ne", ARMCC::NE)
4671      .Case("hs", ARMCC::HS)
4672      .Case("cs", ARMCC::HS)
4673      .Case("lo", ARMCC::LO)
4674      .Case("cc", ARMCC::LO)
4675      .Case("mi", ARMCC::MI)
4676      .Case("pl", ARMCC::PL)
4677      .Case("vs", ARMCC::VS)
4678      .Case("vc", ARMCC::VC)
4679      .Case("hi", ARMCC::HI)
4680      .Case("ls", ARMCC::LS)
4681      .Case("ge", ARMCC::GE)
4682      .Case("lt", ARMCC::LT)
4683      .Case("gt", ARMCC::GT)
4684      .Case("le", ARMCC::LE)
4685      .Case("al", ARMCC::AL)
4686      .Default(~0U);
4687    if (CC != ~0U) {
4688      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4689      PredicationCode = CC;
4690    }
4691  }
4692
4693  // Next, determine if we have a carry setting bit. We explicitly ignore all
4694  // the instructions we know end in 's'.
4695  if (Mnemonic.endswith("s") &&
4696      !(Mnemonic == "cps" || Mnemonic == "mls" ||
4697        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4698        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4699        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4700        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4701        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4702        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4703        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4704        Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4705        (Mnemonic == "movs" && isThumb()))) {
4706    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4707    CarrySetting = true;
4708  }
4709
4710  // The "cps" instruction can have a interrupt mode operand which is glued into
4711  // the mnemonic. Check if this is the case, split it and parse the imod op
4712  if (Mnemonic.startswith("cps")) {
4713    // Split out any imod code.
4714    unsigned IMod =
4715      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4716      .Case("ie", ARM_PROC::IE)
4717      .Case("id", ARM_PROC::ID)
4718      .Default(~0U);
4719    if (IMod != ~0U) {
4720      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4721      ProcessorIMod = IMod;
4722    }
4723  }
4724
4725  // The "it" instruction has the condition mask on the end of the mnemonic.
4726  if (Mnemonic.startswith("it")) {
4727    ITMask = Mnemonic.slice(2, Mnemonic.size());
4728    Mnemonic = Mnemonic.slice(0, 2);
4729  }
4730
4731  return Mnemonic;
4732}
4733
4734/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4735/// inclusion of carry set or predication code operands.
4736//
4737// FIXME: It would be nice to autogen this.
4738void ARMAsmParser::
4739getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4740                      bool &CanAcceptPredicationCode) {
4741  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4742      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4743      Mnemonic == "add" || Mnemonic == "adc" ||
4744      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4745      Mnemonic == "orr" || Mnemonic == "mvn" ||
4746      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4747      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4748      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4749      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4750                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4751                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4752    CanAcceptCarrySet = true;
4753  } else
4754    CanAcceptCarrySet = false;
4755
4756  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4757      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4758      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4759      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4760      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4761      (Mnemonic == "clrex" && !isThumb()) ||
4762      (Mnemonic == "nop" && isThumbOne()) ||
4763      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4764        Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4765        Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4766      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4767       !isThumb()) ||
4768      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4769    CanAcceptPredicationCode = false;
4770  } else
4771    CanAcceptPredicationCode = true;
4772
4773  if (isThumb()) {
4774    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4775        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4776      CanAcceptPredicationCode = false;
4777  }
4778}
4779
4780bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4781                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4782  // FIXME: This is all horribly hacky. We really need a better way to deal
4783  // with optional operands like this in the matcher table.
4784
4785  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4786  // another does not. Specifically, the MOVW instruction does not. So we
4787  // special case it here and remove the defaulted (non-setting) cc_out
4788  // operand if that's the instruction we're trying to match.
4789  //
4790  // We do this as post-processing of the explicit operands rather than just
4791  // conditionally adding the cc_out in the first place because we need
4792  // to check the type of the parsed immediate operand.
4793  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4794      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4795      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4796      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4797    return true;
4798
4799  // Register-register 'add' for thumb does not have a cc_out operand
4800  // when there are only two register operands.
4801  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4802      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4803      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4804      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4805    return true;
4806  // Register-register 'add' for thumb does not have a cc_out operand
4807  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4808  // have to check the immediate range here since Thumb2 has a variant
4809  // that can handle a different range and has a cc_out operand.
4810  if (((isThumb() && Mnemonic == "add") ||
4811       (isThumbTwo() && Mnemonic == "sub")) &&
4812      Operands.size() == 6 &&
4813      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4814      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4815      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4816      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4817      ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4818       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4819    return true;
4820  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4821  // imm0_4095 variant. That's the least-preferred variant when
4822  // selecting via the generic "add" mnemonic, so to know that we
4823  // should remove the cc_out operand, we have to explicitly check that
4824  // it's not one of the other variants. Ugh.
4825  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4826      Operands.size() == 6 &&
4827      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4828      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4829      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4830    // Nest conditions rather than one big 'if' statement for readability.
4831    //
4832    // If either register is a high reg, it's either one of the SP
4833    // variants (handled above) or a 32-bit encoding, so we just
4834    // check against T3. If the second register is the PC, this is an
4835    // alternate form of ADR, which uses encoding T4, so check for that too.
4836    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4837         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4838        static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4839        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4840      return false;
4841    // If both registers are low, we're in an IT block, and the immediate is
4842    // in range, we should use encoding T1 instead, which has a cc_out.
4843    if (inITBlock() &&
4844        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4845        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4846        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4847      return false;
4848
4849    // Otherwise, we use encoding T4, which does not have a cc_out
4850    // operand.
4851    return true;
4852  }
4853
4854  // The thumb2 multiply instruction doesn't have a CCOut register, so
4855  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4856  // use the 16-bit encoding or not.
4857  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4858      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4859      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4860      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4861      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4862      // If the registers aren't low regs, the destination reg isn't the
4863      // same as one of the source regs, or the cc_out operand is zero
4864      // outside of an IT block, we have to use the 32-bit encoding, so
4865      // remove the cc_out operand.
4866      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4867       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4868       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4869       !inITBlock() ||
4870       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4871        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4872        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4873        static_cast<ARMOperand*>(Operands[4])->getReg())))
4874    return true;
4875
4876  // Also check the 'mul' syntax variant that doesn't specify an explicit
4877  // destination register.
4878  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4879      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4880      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4881      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4882      // If the registers aren't low regs  or the cc_out operand is zero
4883      // outside of an IT block, we have to use the 32-bit encoding, so
4884      // remove the cc_out operand.
4885      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4886       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4887       !inITBlock()))
4888    return true;
4889
4890
4891
4892  // Register-register 'add/sub' for thumb does not have a cc_out operand
4893  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4894  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4895  // right, this will result in better diagnostics (which operand is off)
4896  // anyway.
4897  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4898      (Operands.size() == 5 || Operands.size() == 6) &&
4899      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4900      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4901      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4902      (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4903       (Operands.size() == 6 &&
4904        static_cast<ARMOperand*>(Operands[5])->isImm())))
4905    return true;
4906
4907  return false;
4908}
4909
4910static bool isDataTypeToken(StringRef Tok) {
4911  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4912    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4913    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4914    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4915    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4916    Tok == ".f" || Tok == ".d";
4917}
4918
4919// FIXME: This bit should probably be handled via an explicit match class
4920// in the .td files that matches the suffix instead of having it be
4921// a literal string token the way it is now.
4922static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4923  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4924}
4925
4926static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4927/// Parse an arm instruction mnemonic followed by its operands.
4928bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4929                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4930  // Apply mnemonic aliases before doing anything else, as the destination
4931  // mnemnonic may include suffices and we want to handle them normally.
4932  // The generic tblgen'erated code does this later, at the start of
4933  // MatchInstructionImpl(), but that's too late for aliases that include
4934  // any sort of suffix.
4935  unsigned AvailableFeatures = getAvailableFeatures();
4936  applyMnemonicAliases(Name, AvailableFeatures);
4937
4938  // First check for the ARM-specific .req directive.
4939  if (Parser.getTok().is(AsmToken::Identifier) &&
4940      Parser.getTok().getIdentifier() == ".req") {
4941    parseDirectiveReq(Name, NameLoc);
4942    // We always return 'error' for this, as we're done with this
4943    // statement and don't need to match the 'instruction."
4944    return true;
4945  }
4946
4947  // Create the leading tokens for the mnemonic, split by '.' characters.
4948  size_t Start = 0, Next = Name.find('.');
4949  StringRef Mnemonic = Name.slice(Start, Next);
4950
4951  // Split out the predication code and carry setting flag from the mnemonic.
4952  unsigned PredicationCode;
4953  unsigned ProcessorIMod;
4954  bool CarrySetting;
4955  StringRef ITMask;
4956  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4957                           ProcessorIMod, ITMask);
4958
4959  // In Thumb1, only the branch (B) instruction can be predicated.
4960  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4961    Parser.EatToEndOfStatement();
4962    return Error(NameLoc, "conditional execution not supported in Thumb1");
4963  }
4964
4965  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4966
4967  // Handle the IT instruction ITMask. Convert it to a bitmask. This
4968  // is the mask as it will be for the IT encoding if the conditional
4969  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4970  // where the conditional bit0 is zero, the instruction post-processing
4971  // will adjust the mask accordingly.
4972  if (Mnemonic == "it") {
4973    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4974    if (ITMask.size() > 3) {
4975      Parser.EatToEndOfStatement();
4976      return Error(Loc, "too many conditions on IT instruction");
4977    }
4978    unsigned Mask = 8;
4979    for (unsigned i = ITMask.size(); i != 0; --i) {
4980      char pos = ITMask[i - 1];
4981      if (pos != 't' && pos != 'e') {
4982        Parser.EatToEndOfStatement();
4983        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4984      }
4985      Mask >>= 1;
4986      if (ITMask[i - 1] == 't')
4987        Mask |= 8;
4988    }
4989    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4990  }
4991
4992  // FIXME: This is all a pretty gross hack. We should automatically handle
4993  // optional operands like this via tblgen.
4994
4995  // Next, add the CCOut and ConditionCode operands, if needed.
4996  //
4997  // For mnemonics which can ever incorporate a carry setting bit or predication
4998  // code, our matching model involves us always generating CCOut and
4999  // ConditionCode operands to match the mnemonic "as written" and then we let
5000  // the matcher deal with finding the right instruction or generating an
5001  // appropriate error.
5002  bool CanAcceptCarrySet, CanAcceptPredicationCode;
5003  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5004
5005  // If we had a carry-set on an instruction that can't do that, issue an
5006  // error.
5007  if (!CanAcceptCarrySet && CarrySetting) {
5008    Parser.EatToEndOfStatement();
5009    return Error(NameLoc, "instruction '" + Mnemonic +
5010                 "' can not set flags, but 's' suffix specified");
5011  }
5012  // If we had a predication code on an instruction that can't do that, issue an
5013  // error.
5014  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5015    Parser.EatToEndOfStatement();
5016    return Error(NameLoc, "instruction '" + Mnemonic +
5017                 "' is not predicable, but condition code specified");
5018  }
5019
5020  // Add the carry setting operand, if necessary.
5021  if (CanAcceptCarrySet) {
5022    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5023    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5024                                               Loc));
5025  }
5026
5027  // Add the predication code operand, if necessary.
5028  if (CanAcceptPredicationCode) {
5029    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5030                                      CarrySetting);
5031    Operands.push_back(ARMOperand::CreateCondCode(
5032                         ARMCC::CondCodes(PredicationCode), Loc));
5033  }
5034
5035  // Add the processor imod operand, if necessary.
5036  if (ProcessorIMod) {
5037    Operands.push_back(ARMOperand::CreateImm(
5038          MCConstantExpr::Create(ProcessorIMod, getContext()),
5039                                 NameLoc, NameLoc));
5040  }
5041
5042  // Add the remaining tokens in the mnemonic.
5043  while (Next != StringRef::npos) {
5044    Start = Next;
5045    Next = Name.find('.', Start + 1);
5046    StringRef ExtraToken = Name.slice(Start, Next);
5047
5048    // Some NEON instructions have an optional datatype suffix that is
5049    // completely ignored. Check for that.
5050    if (isDataTypeToken(ExtraToken) &&
5051        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5052      continue;
5053
5054    if (ExtraToken != ".n") {
5055      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5056      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5057    }
5058  }
5059
5060  // Read the remaining operands.
5061  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5062    // Read the first operand.
5063    if (parseOperand(Operands, Mnemonic)) {
5064      Parser.EatToEndOfStatement();
5065      return true;
5066    }
5067
5068    while (getLexer().is(AsmToken::Comma)) {
5069      Parser.Lex();  // Eat the comma.
5070
5071      // Parse and remember the operand.
5072      if (parseOperand(Operands, Mnemonic)) {
5073        Parser.EatToEndOfStatement();
5074        return true;
5075      }
5076    }
5077  }
5078
5079  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5080    SMLoc Loc = getLexer().getLoc();
5081    Parser.EatToEndOfStatement();
5082    return Error(Loc, "unexpected token in argument list");
5083  }
5084
5085  Parser.Lex(); // Consume the EndOfStatement
5086
5087  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5088  // do and don't have a cc_out optional-def operand. With some spot-checks
5089  // of the operand list, we can figure out which variant we're trying to
5090  // parse and adjust accordingly before actually matching. We shouldn't ever
5091  // try to remove a cc_out operand that was explicitly set on the the
5092  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5093  // table driven matcher doesn't fit well with the ARM instruction set.
5094  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5095    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5096    Operands.erase(Operands.begin() + 1);
5097    delete Op;
5098  }
5099
5100  // ARM mode 'blx' need special handling, as the register operand version
5101  // is predicable, but the label operand version is not. So, we can't rely
5102  // on the Mnemonic based checking to correctly figure out when to put
5103  // a k_CondCode operand in the list. If we're trying to match the label
5104  // version, remove the k_CondCode operand here.
5105  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5106      static_cast<ARMOperand*>(Operands[2])->isImm()) {
5107    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5108    Operands.erase(Operands.begin() + 1);
5109    delete Op;
5110  }
5111
5112  // The vector-compare-to-zero instructions have a literal token "#0" at
5113  // the end that comes to here as an immediate operand. Convert it to a
5114  // token to play nicely with the matcher.
5115  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5116      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5117      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5118    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5119    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5120    if (CE && CE->getValue() == 0) {
5121      Operands.erase(Operands.begin() + 5);
5122      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5123      delete Op;
5124    }
5125  }
5126  // VCMP{E} does the same thing, but with a different operand count.
5127  if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5128      static_cast<ARMOperand*>(Operands[4])->isImm()) {
5129    ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5130    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5131    if (CE && CE->getValue() == 0) {
5132      Operands.erase(Operands.begin() + 4);
5133      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5134      delete Op;
5135    }
5136  }
5137  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5138  // end. Convert it to a token here. Take care not to convert those
5139  // that should hit the Thumb2 encoding.
5140  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5141      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5142      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5143      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5144    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5145    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5146    if (CE && CE->getValue() == 0 &&
5147        (isThumbOne() ||
5148         // The cc_out operand matches the IT block.
5149         ((inITBlock() != CarrySetting) &&
5150         // Neither register operand is a high register.
5151         (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5152          isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5153      Operands.erase(Operands.begin() + 5);
5154      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5155      delete Op;
5156    }
5157  }
5158
5159  return false;
5160}
5161
5162// Validate context-sensitive operand constraints.
5163
5164// return 'true' if register list contains non-low GPR registers,
5165// 'false' otherwise. If Reg is in the register list or is HiReg, set
5166// 'containsReg' to true.
5167static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5168                                 unsigned HiReg, bool &containsReg) {
5169  containsReg = false;
5170  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5171    unsigned OpReg = Inst.getOperand(i).getReg();
5172    if (OpReg == Reg)
5173      containsReg = true;
5174    // Anything other than a low register isn't legal here.
5175    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5176      return true;
5177  }
5178  return false;
5179}
5180
5181// Check if the specified regisgter is in the register list of the inst,
5182// starting at the indicated operand number.
5183static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5184  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5185    unsigned OpReg = Inst.getOperand(i).getReg();
5186    if (OpReg == Reg)
5187      return true;
5188  }
5189  return false;
5190}
5191
5192// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5193// the ARMInsts array) instead. Getting that here requires awkward
5194// API changes, though. Better way?
5195namespace llvm {
5196extern const MCInstrDesc ARMInsts[];
5197}
5198static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5199  return ARMInsts[Opcode];
5200}
5201
5202// FIXME: We would really like to be able to tablegen'erate this.
5203bool ARMAsmParser::
5204validateInstruction(MCInst &Inst,
5205                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5206  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5207  SMLoc Loc = Operands[0]->getStartLoc();
5208  // Check the IT block state first.
5209  // NOTE: BKPT instruction has the interesting property of being
5210  // allowed in IT blocks, but not being predicable.  It just always
5211  // executes.
5212  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5213      Inst.getOpcode() != ARM::BKPT) {
5214    unsigned bit = 1;
5215    if (ITState.FirstCond)
5216      ITState.FirstCond = false;
5217    else
5218      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5219    // The instruction must be predicable.
5220    if (!MCID.isPredicable())
5221      return Error(Loc, "instructions in IT block must be predicable");
5222    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5223    unsigned ITCond = bit ? ITState.Cond :
5224      ARMCC::getOppositeCondition(ITState.Cond);
5225    if (Cond != ITCond) {
5226      // Find the condition code Operand to get its SMLoc information.
5227      SMLoc CondLoc;
5228      for (unsigned i = 1; i < Operands.size(); ++i)
5229        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5230          CondLoc = Operands[i]->getStartLoc();
5231      return Error(CondLoc, "incorrect condition in IT block; got '" +
5232                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5233                   "', but expected '" +
5234                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5235    }
5236  // Check for non-'al' condition codes outside of the IT block.
5237  } else if (isThumbTwo() && MCID.isPredicable() &&
5238             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5239             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5240             Inst.getOpcode() != ARM::t2B)
5241    return Error(Loc, "predicated instructions must be in IT block");
5242
5243  switch (Inst.getOpcode()) {
5244  case ARM::LDRD:
5245  case ARM::LDRD_PRE:
5246  case ARM::LDRD_POST:
5247  case ARM::LDREXD: {
5248    // Rt2 must be Rt + 1.
5249    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5250    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5251    if (Rt2 != Rt + 1)
5252      return Error(Operands[3]->getStartLoc(),
5253                   "destination operands must be sequential");
5254    return false;
5255  }
5256  case ARM::STRD: {
5257    // Rt2 must be Rt + 1.
5258    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5259    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5260    if (Rt2 != Rt + 1)
5261      return Error(Operands[3]->getStartLoc(),
5262                   "source operands must be sequential");
5263    return false;
5264  }
5265  case ARM::STRD_PRE:
5266  case ARM::STRD_POST:
5267  case ARM::STREXD: {
5268    // Rt2 must be Rt + 1.
5269    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5270    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
5271    if (Rt2 != Rt + 1)
5272      return Error(Operands[3]->getStartLoc(),
5273                   "source operands must be sequential");
5274    return false;
5275  }
5276  case ARM::SBFX:
5277  case ARM::UBFX: {
5278    // width must be in range [1, 32-lsb]
5279    unsigned lsb = Inst.getOperand(2).getImm();
5280    unsigned widthm1 = Inst.getOperand(3).getImm();
5281    if (widthm1 >= 32 - lsb)
5282      return Error(Operands[5]->getStartLoc(),
5283                   "bitfield width must be in range [1,32-lsb]");
5284    return false;
5285  }
5286  case ARM::tLDMIA: {
5287    // If we're parsing Thumb2, the .w variant is available and handles
5288    // most cases that are normally illegal for a Thumb1 LDM
5289    // instruction. We'll make the transformation in processInstruction()
5290    // if necessary.
5291    //
5292    // Thumb LDM instructions are writeback iff the base register is not
5293    // in the register list.
5294    unsigned Rn = Inst.getOperand(0).getReg();
5295    bool hasWritebackToken =
5296      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5297       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5298    bool listContainsBase;
5299    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5300      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5301                   "registers must be in range r0-r7");
5302    // If we should have writeback, then there should be a '!' token.
5303    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5304      return Error(Operands[2]->getStartLoc(),
5305                   "writeback operator '!' expected");
5306    // If we should not have writeback, there must not be a '!'. This is
5307    // true even for the 32-bit wide encodings.
5308    if (listContainsBase && hasWritebackToken)
5309      return Error(Operands[3]->getStartLoc(),
5310                   "writeback operator '!' not allowed when base register "
5311                   "in register list");
5312
5313    break;
5314  }
5315  case ARM::t2LDMIA_UPD: {
5316    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5317      return Error(Operands[4]->getStartLoc(),
5318                   "writeback operator '!' not allowed when base register "
5319                   "in register list");
5320    break;
5321  }
5322  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5323  // so only issue a diagnostic for thumb1. The instructions will be
5324  // switched to the t2 encodings in processInstruction() if necessary.
5325  case ARM::tPOP: {
5326    bool listContainsBase;
5327    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5328        !isThumbTwo())
5329      return Error(Operands[2]->getStartLoc(),
5330                   "registers must be in range r0-r7 or pc");
5331    break;
5332  }
5333  case ARM::tPUSH: {
5334    bool listContainsBase;
5335    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5336        !isThumbTwo())
5337      return Error(Operands[2]->getStartLoc(),
5338                   "registers must be in range r0-r7 or lr");
5339    break;
5340  }
5341  case ARM::tSTMIA_UPD: {
5342    bool listContainsBase;
5343    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5344      return Error(Operands[4]->getStartLoc(),
5345                   "registers must be in range r0-r7");
5346    break;
5347  }
5348  case ARM::tADDrSP: {
5349    // If the non-SP source operand and the destination operand are not the
5350    // same, we need thumb2 (for the wide encoding), or we have an error.
5351    if (!isThumbTwo() &&
5352        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5353      return Error(Operands[4]->getStartLoc(),
5354                   "source register must be the same as destination");
5355    }
5356    break;
5357  }
5358  }
5359
5360  return false;
5361}
5362
5363static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5364  switch(Opc) {
5365  default: llvm_unreachable("unexpected opcode!");
5366  // VST1LN
5367  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5368  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5369  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5370  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5371  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5372  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5373  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5374  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5375  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5376
5377  // VST2LN
5378  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5379  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5380  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5381  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5382  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5383
5384  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5385  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5386  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5387  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5388  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5389
5390  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5391  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5392  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5393  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5394  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5395
5396  // VST3LN
5397  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5398  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5399  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5400  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5401  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5402  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5403  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5404  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5405  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5406  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5407  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5408  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5409  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5410  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5411  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5412
5413  // VST3
5414  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5415  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5416  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5417  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5418  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5419  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5420  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5421  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5422  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5423  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5424  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5425  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5426  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5427  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5428  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5429  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5430  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5431  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5432
5433  // VST4LN
5434  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5435  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5436  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5437  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5438  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5439  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5440  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5441  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5442  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5443  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5444  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5445  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5446  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5447  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5448  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5449
5450  // VST4
5451  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5452  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5453  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5454  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5455  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5456  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5457  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5458  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5459  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5460  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5461  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5462  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5463  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5464  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5465  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5466  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5467  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5468  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5469  }
5470}
5471
5472static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5473  switch(Opc) {
5474  default: llvm_unreachable("unexpected opcode!");
5475  // VLD1LN
5476  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5477  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5478  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5479  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5480  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5481  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5482  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5483  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5484  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5485
5486  // VLD2LN
5487  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5488  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5489  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5490  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5491  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5492  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5493  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5494  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5495  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5496  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5497  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5498  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5499  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5500  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5501  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5502
5503  // VLD3DUP
5504  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5505  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5506  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5507  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5508  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5509  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5510  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5511  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5512  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5513  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5514  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5515  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5516  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5517  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5518  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5519  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5520  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5521  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5522
5523  // VLD3LN
5524  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5525  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5526  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5527  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5528  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5529  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5530  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5531  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5532  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5533  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5534  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5535  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5536  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5537  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5538  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5539
5540  // VLD3
5541  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5542  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5543  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5544  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5545  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5546  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5547  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5548  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5549  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5550  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5551  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5552  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5553  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5554  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5555  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5556  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5557  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5558  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5559
5560  // VLD4LN
5561  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5562  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5563  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5564  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5565  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5566  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5567  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5568  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5569  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5570  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5571  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5572  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5573  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5574  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5575  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5576
5577  // VLD4DUP
5578  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5579  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5580  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5581  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5582  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5583  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5584  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5585  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5586  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5587  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5588  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5589  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5590  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5591  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5592  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5593  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5594  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5595  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5596
5597  // VLD4
5598  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5599  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5600  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5601  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5602  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5603  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5604  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5605  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5606  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5607  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5608  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5609  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5610  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5611  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5612  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5613  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5614  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5615  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5616  }
5617}
5618
5619bool ARMAsmParser::
5620processInstruction(MCInst &Inst,
5621                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5622  switch (Inst.getOpcode()) {
5623  // Aliases for alternate PC+imm syntax of LDR instructions.
5624  case ARM::t2LDRpcrel:
5625    Inst.setOpcode(ARM::t2LDRpci);
5626    return true;
5627  case ARM::t2LDRBpcrel:
5628    Inst.setOpcode(ARM::t2LDRBpci);
5629    return true;
5630  case ARM::t2LDRHpcrel:
5631    Inst.setOpcode(ARM::t2LDRHpci);
5632    return true;
5633  case ARM::t2LDRSBpcrel:
5634    Inst.setOpcode(ARM::t2LDRSBpci);
5635    return true;
5636  case ARM::t2LDRSHpcrel:
5637    Inst.setOpcode(ARM::t2LDRSHpci);
5638    return true;
5639  // Handle NEON VST complex aliases.
5640  case ARM::VST1LNdWB_register_Asm_8:
5641  case ARM::VST1LNdWB_register_Asm_16:
5642  case ARM::VST1LNdWB_register_Asm_32: {
5643    MCInst TmpInst;
5644    // Shuffle the operands around so the lane index operand is in the
5645    // right place.
5646    unsigned Spacing;
5647    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5648    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5649    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5650    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5651    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5652    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5653    TmpInst.addOperand(Inst.getOperand(1)); // lane
5654    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5655    TmpInst.addOperand(Inst.getOperand(6));
5656    Inst = TmpInst;
5657    return true;
5658  }
5659
5660  case ARM::VST2LNdWB_register_Asm_8:
5661  case ARM::VST2LNdWB_register_Asm_16:
5662  case ARM::VST2LNdWB_register_Asm_32:
5663  case ARM::VST2LNqWB_register_Asm_16:
5664  case ARM::VST2LNqWB_register_Asm_32: {
5665    MCInst TmpInst;
5666    // Shuffle the operands around so the lane index operand is in the
5667    // right place.
5668    unsigned Spacing;
5669    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5670    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5671    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5672    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5673    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5674    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5675    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5676                                            Spacing));
5677    TmpInst.addOperand(Inst.getOperand(1)); // lane
5678    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5679    TmpInst.addOperand(Inst.getOperand(6));
5680    Inst = TmpInst;
5681    return true;
5682  }
5683
5684  case ARM::VST3LNdWB_register_Asm_8:
5685  case ARM::VST3LNdWB_register_Asm_16:
5686  case ARM::VST3LNdWB_register_Asm_32:
5687  case ARM::VST3LNqWB_register_Asm_16:
5688  case ARM::VST3LNqWB_register_Asm_32: {
5689    MCInst TmpInst;
5690    // Shuffle the operands around so the lane index operand is in the
5691    // right place.
5692    unsigned Spacing;
5693    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5694    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5695    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5696    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5697    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5698    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5699    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5700                                            Spacing));
5701    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5702                                            Spacing * 2));
5703    TmpInst.addOperand(Inst.getOperand(1)); // lane
5704    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5705    TmpInst.addOperand(Inst.getOperand(6));
5706    Inst = TmpInst;
5707    return true;
5708  }
5709
5710  case ARM::VST4LNdWB_register_Asm_8:
5711  case ARM::VST4LNdWB_register_Asm_16:
5712  case ARM::VST4LNdWB_register_Asm_32:
5713  case ARM::VST4LNqWB_register_Asm_16:
5714  case ARM::VST4LNqWB_register_Asm_32: {
5715    MCInst TmpInst;
5716    // Shuffle the operands around so the lane index operand is in the
5717    // right place.
5718    unsigned Spacing;
5719    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5720    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5721    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5722    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5723    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5724    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5725    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5726                                            Spacing));
5727    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5728                                            Spacing * 2));
5729    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5730                                            Spacing * 3));
5731    TmpInst.addOperand(Inst.getOperand(1)); // lane
5732    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5733    TmpInst.addOperand(Inst.getOperand(6));
5734    Inst = TmpInst;
5735    return true;
5736  }
5737
5738  case ARM::VST1LNdWB_fixed_Asm_8:
5739  case ARM::VST1LNdWB_fixed_Asm_16:
5740  case ARM::VST1LNdWB_fixed_Asm_32: {
5741    MCInst TmpInst;
5742    // Shuffle the operands around so the lane index operand is in the
5743    // right place.
5744    unsigned Spacing;
5745    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5746    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5747    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5748    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5749    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5750    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5751    TmpInst.addOperand(Inst.getOperand(1)); // lane
5752    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5753    TmpInst.addOperand(Inst.getOperand(5));
5754    Inst = TmpInst;
5755    return true;
5756  }
5757
5758  case ARM::VST2LNdWB_fixed_Asm_8:
5759  case ARM::VST2LNdWB_fixed_Asm_16:
5760  case ARM::VST2LNdWB_fixed_Asm_32:
5761  case ARM::VST2LNqWB_fixed_Asm_16:
5762  case ARM::VST2LNqWB_fixed_Asm_32: {
5763    MCInst TmpInst;
5764    // Shuffle the operands around so the lane index operand is in the
5765    // right place.
5766    unsigned Spacing;
5767    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5768    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5769    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5770    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5771    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5772    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5773    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5774                                            Spacing));
5775    TmpInst.addOperand(Inst.getOperand(1)); // lane
5776    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5777    TmpInst.addOperand(Inst.getOperand(5));
5778    Inst = TmpInst;
5779    return true;
5780  }
5781
5782  case ARM::VST3LNdWB_fixed_Asm_8:
5783  case ARM::VST3LNdWB_fixed_Asm_16:
5784  case ARM::VST3LNdWB_fixed_Asm_32:
5785  case ARM::VST3LNqWB_fixed_Asm_16:
5786  case ARM::VST3LNqWB_fixed_Asm_32: {
5787    MCInst TmpInst;
5788    // Shuffle the operands around so the lane index operand is in the
5789    // right place.
5790    unsigned Spacing;
5791    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5792    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5793    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5794    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5795    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5796    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5797    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5798                                            Spacing));
5799    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5800                                            Spacing * 2));
5801    TmpInst.addOperand(Inst.getOperand(1)); // lane
5802    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5803    TmpInst.addOperand(Inst.getOperand(5));
5804    Inst = TmpInst;
5805    return true;
5806  }
5807
5808  case ARM::VST4LNdWB_fixed_Asm_8:
5809  case ARM::VST4LNdWB_fixed_Asm_16:
5810  case ARM::VST4LNdWB_fixed_Asm_32:
5811  case ARM::VST4LNqWB_fixed_Asm_16:
5812  case ARM::VST4LNqWB_fixed_Asm_32: {
5813    MCInst TmpInst;
5814    // Shuffle the operands around so the lane index operand is in the
5815    // right place.
5816    unsigned Spacing;
5817    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5818    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5819    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5820    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5821    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5822    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5823    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5824                                            Spacing));
5825    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5826                                            Spacing * 2));
5827    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5828                                            Spacing * 3));
5829    TmpInst.addOperand(Inst.getOperand(1)); // lane
5830    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5831    TmpInst.addOperand(Inst.getOperand(5));
5832    Inst = TmpInst;
5833    return true;
5834  }
5835
5836  case ARM::VST1LNdAsm_8:
5837  case ARM::VST1LNdAsm_16:
5838  case ARM::VST1LNdAsm_32: {
5839    MCInst TmpInst;
5840    // Shuffle the operands around so the lane index operand is in the
5841    // right place.
5842    unsigned Spacing;
5843    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5844    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5845    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5846    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5847    TmpInst.addOperand(Inst.getOperand(1)); // lane
5848    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5849    TmpInst.addOperand(Inst.getOperand(5));
5850    Inst = TmpInst;
5851    return true;
5852  }
5853
5854  case ARM::VST2LNdAsm_8:
5855  case ARM::VST2LNdAsm_16:
5856  case ARM::VST2LNdAsm_32:
5857  case ARM::VST2LNqAsm_16:
5858  case ARM::VST2LNqAsm_32: {
5859    MCInst TmpInst;
5860    // Shuffle the operands around so the lane index operand is in the
5861    // right place.
5862    unsigned Spacing;
5863    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5864    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5865    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5866    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5867    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5868                                            Spacing));
5869    TmpInst.addOperand(Inst.getOperand(1)); // lane
5870    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5871    TmpInst.addOperand(Inst.getOperand(5));
5872    Inst = TmpInst;
5873    return true;
5874  }
5875
5876  case ARM::VST3LNdAsm_8:
5877  case ARM::VST3LNdAsm_16:
5878  case ARM::VST3LNdAsm_32:
5879  case ARM::VST3LNqAsm_16:
5880  case ARM::VST3LNqAsm_32: {
5881    MCInst TmpInst;
5882    // Shuffle the operands around so the lane index operand is in the
5883    // right place.
5884    unsigned Spacing;
5885    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5886    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5887    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5888    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5889    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5890                                            Spacing));
5891    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5892                                            Spacing * 2));
5893    TmpInst.addOperand(Inst.getOperand(1)); // lane
5894    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5895    TmpInst.addOperand(Inst.getOperand(5));
5896    Inst = TmpInst;
5897    return true;
5898  }
5899
5900  case ARM::VST4LNdAsm_8:
5901  case ARM::VST4LNdAsm_16:
5902  case ARM::VST4LNdAsm_32:
5903  case ARM::VST4LNqAsm_16:
5904  case ARM::VST4LNqAsm_32: {
5905    MCInst TmpInst;
5906    // Shuffle the operands around so the lane index operand is in the
5907    // right place.
5908    unsigned Spacing;
5909    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5910    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5911    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5912    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5913    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5914                                            Spacing));
5915    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5916                                            Spacing * 2));
5917    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5918                                            Spacing * 3));
5919    TmpInst.addOperand(Inst.getOperand(1)); // lane
5920    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5921    TmpInst.addOperand(Inst.getOperand(5));
5922    Inst = TmpInst;
5923    return true;
5924  }
5925
5926  // Handle NEON VLD complex aliases.
5927  case ARM::VLD1LNdWB_register_Asm_8:
5928  case ARM::VLD1LNdWB_register_Asm_16:
5929  case ARM::VLD1LNdWB_register_Asm_32: {
5930    MCInst TmpInst;
5931    // Shuffle the operands around so the lane index operand is in the
5932    // right place.
5933    unsigned Spacing;
5934    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5935    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5936    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5937    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5938    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5939    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5940    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5941    TmpInst.addOperand(Inst.getOperand(1)); // lane
5942    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5943    TmpInst.addOperand(Inst.getOperand(6));
5944    Inst = TmpInst;
5945    return true;
5946  }
5947
5948  case ARM::VLD2LNdWB_register_Asm_8:
5949  case ARM::VLD2LNdWB_register_Asm_16:
5950  case ARM::VLD2LNdWB_register_Asm_32:
5951  case ARM::VLD2LNqWB_register_Asm_16:
5952  case ARM::VLD2LNqWB_register_Asm_32: {
5953    MCInst TmpInst;
5954    // Shuffle the operands around so the lane index operand is in the
5955    // right place.
5956    unsigned Spacing;
5957    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5958    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5959    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5960                                            Spacing));
5961    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5962    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5963    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5964    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5965    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5966    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5967                                            Spacing));
5968    TmpInst.addOperand(Inst.getOperand(1)); // lane
5969    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5970    TmpInst.addOperand(Inst.getOperand(6));
5971    Inst = TmpInst;
5972    return true;
5973  }
5974
5975  case ARM::VLD3LNdWB_register_Asm_8:
5976  case ARM::VLD3LNdWB_register_Asm_16:
5977  case ARM::VLD3LNdWB_register_Asm_32:
5978  case ARM::VLD3LNqWB_register_Asm_16:
5979  case ARM::VLD3LNqWB_register_Asm_32: {
5980    MCInst TmpInst;
5981    // Shuffle the operands around so the lane index operand is in the
5982    // right place.
5983    unsigned Spacing;
5984    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5985    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5986    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5987                                            Spacing));
5988    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5989                                            Spacing * 2));
5990    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5991    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5992    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5993    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5994    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5995    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5996                                            Spacing));
5997    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5998                                            Spacing * 2));
5999    TmpInst.addOperand(Inst.getOperand(1)); // lane
6000    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6001    TmpInst.addOperand(Inst.getOperand(6));
6002    Inst = TmpInst;
6003    return true;
6004  }
6005
6006  case ARM::VLD4LNdWB_register_Asm_8:
6007  case ARM::VLD4LNdWB_register_Asm_16:
6008  case ARM::VLD4LNdWB_register_Asm_32:
6009  case ARM::VLD4LNqWB_register_Asm_16:
6010  case ARM::VLD4LNqWB_register_Asm_32: {
6011    MCInst TmpInst;
6012    // Shuffle the operands around so the lane index operand is in the
6013    // right place.
6014    unsigned Spacing;
6015    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6016    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6017    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6018                                            Spacing));
6019    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6020                                            Spacing * 2));
6021    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6022                                            Spacing * 3));
6023    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6024    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6025    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6026    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6027    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6028    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6029                                            Spacing));
6030    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6031                                            Spacing * 2));
6032    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6033                                            Spacing * 3));
6034    TmpInst.addOperand(Inst.getOperand(1)); // lane
6035    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6036    TmpInst.addOperand(Inst.getOperand(6));
6037    Inst = TmpInst;
6038    return true;
6039  }
6040
6041  case ARM::VLD1LNdWB_fixed_Asm_8:
6042  case ARM::VLD1LNdWB_fixed_Asm_16:
6043  case ARM::VLD1LNdWB_fixed_Asm_32: {
6044    MCInst TmpInst;
6045    // Shuffle the operands around so the lane index operand is in the
6046    // right place.
6047    unsigned Spacing;
6048    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6049    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6050    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6051    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6052    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6053    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6054    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6055    TmpInst.addOperand(Inst.getOperand(1)); // lane
6056    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6057    TmpInst.addOperand(Inst.getOperand(5));
6058    Inst = TmpInst;
6059    return true;
6060  }
6061
6062  case ARM::VLD2LNdWB_fixed_Asm_8:
6063  case ARM::VLD2LNdWB_fixed_Asm_16:
6064  case ARM::VLD2LNdWB_fixed_Asm_32:
6065  case ARM::VLD2LNqWB_fixed_Asm_16:
6066  case ARM::VLD2LNqWB_fixed_Asm_32: {
6067    MCInst TmpInst;
6068    // Shuffle the operands around so the lane index operand is in the
6069    // right place.
6070    unsigned Spacing;
6071    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6072    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6073    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6074                                            Spacing));
6075    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6076    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6077    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6078    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6079    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6080    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6081                                            Spacing));
6082    TmpInst.addOperand(Inst.getOperand(1)); // lane
6083    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6084    TmpInst.addOperand(Inst.getOperand(5));
6085    Inst = TmpInst;
6086    return true;
6087  }
6088
6089  case ARM::VLD3LNdWB_fixed_Asm_8:
6090  case ARM::VLD3LNdWB_fixed_Asm_16:
6091  case ARM::VLD3LNdWB_fixed_Asm_32:
6092  case ARM::VLD3LNqWB_fixed_Asm_16:
6093  case ARM::VLD3LNqWB_fixed_Asm_32: {
6094    MCInst TmpInst;
6095    // Shuffle the operands around so the lane index operand is in the
6096    // right place.
6097    unsigned Spacing;
6098    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6099    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6100    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6101                                            Spacing));
6102    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6103                                            Spacing * 2));
6104    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6105    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6106    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6107    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6108    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6109    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6110                                            Spacing));
6111    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6112                                            Spacing * 2));
6113    TmpInst.addOperand(Inst.getOperand(1)); // lane
6114    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6115    TmpInst.addOperand(Inst.getOperand(5));
6116    Inst = TmpInst;
6117    return true;
6118  }
6119
6120  case ARM::VLD4LNdWB_fixed_Asm_8:
6121  case ARM::VLD4LNdWB_fixed_Asm_16:
6122  case ARM::VLD4LNdWB_fixed_Asm_32:
6123  case ARM::VLD4LNqWB_fixed_Asm_16:
6124  case ARM::VLD4LNqWB_fixed_Asm_32: {
6125    MCInst TmpInst;
6126    // Shuffle the operands around so the lane index operand is in the
6127    // right place.
6128    unsigned Spacing;
6129    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6130    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6131    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6132                                            Spacing));
6133    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6134                                            Spacing * 2));
6135    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6136                                            Spacing * 3));
6137    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6138    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6139    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6140    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6141    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6142    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6143                                            Spacing));
6144    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6145                                            Spacing * 2));
6146    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6147                                            Spacing * 3));
6148    TmpInst.addOperand(Inst.getOperand(1)); // lane
6149    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6150    TmpInst.addOperand(Inst.getOperand(5));
6151    Inst = TmpInst;
6152    return true;
6153  }
6154
6155  case ARM::VLD1LNdAsm_8:
6156  case ARM::VLD1LNdAsm_16:
6157  case ARM::VLD1LNdAsm_32: {
6158    MCInst TmpInst;
6159    // Shuffle the operands around so the lane index operand is in the
6160    // right place.
6161    unsigned Spacing;
6162    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6163    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6164    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6165    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6166    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6167    TmpInst.addOperand(Inst.getOperand(1)); // lane
6168    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6169    TmpInst.addOperand(Inst.getOperand(5));
6170    Inst = TmpInst;
6171    return true;
6172  }
6173
6174  case ARM::VLD2LNdAsm_8:
6175  case ARM::VLD2LNdAsm_16:
6176  case ARM::VLD2LNdAsm_32:
6177  case ARM::VLD2LNqAsm_16:
6178  case ARM::VLD2LNqAsm_32: {
6179    MCInst TmpInst;
6180    // Shuffle the operands around so the lane index operand is in the
6181    // right place.
6182    unsigned Spacing;
6183    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6184    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6185    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6186                                            Spacing));
6187    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6188    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6189    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6190    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6191                                            Spacing));
6192    TmpInst.addOperand(Inst.getOperand(1)); // lane
6193    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6194    TmpInst.addOperand(Inst.getOperand(5));
6195    Inst = TmpInst;
6196    return true;
6197  }
6198
6199  case ARM::VLD3LNdAsm_8:
6200  case ARM::VLD3LNdAsm_16:
6201  case ARM::VLD3LNdAsm_32:
6202  case ARM::VLD3LNqAsm_16:
6203  case ARM::VLD3LNqAsm_32: {
6204    MCInst TmpInst;
6205    // Shuffle the operands around so the lane index operand is in the
6206    // right place.
6207    unsigned Spacing;
6208    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6209    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6210    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6211                                            Spacing));
6212    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6213                                            Spacing * 2));
6214    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6215    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6216    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6217    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6218                                            Spacing));
6219    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6220                                            Spacing * 2));
6221    TmpInst.addOperand(Inst.getOperand(1)); // lane
6222    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6223    TmpInst.addOperand(Inst.getOperand(5));
6224    Inst = TmpInst;
6225    return true;
6226  }
6227
6228  case ARM::VLD4LNdAsm_8:
6229  case ARM::VLD4LNdAsm_16:
6230  case ARM::VLD4LNdAsm_32:
6231  case ARM::VLD4LNqAsm_16:
6232  case ARM::VLD4LNqAsm_32: {
6233    MCInst TmpInst;
6234    // Shuffle the operands around so the lane index operand is in the
6235    // right place.
6236    unsigned Spacing;
6237    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6238    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6239    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6240                                            Spacing));
6241    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6242                                            Spacing * 2));
6243    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6244                                            Spacing * 3));
6245    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6246    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6247    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6248    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6249                                            Spacing));
6250    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6251                                            Spacing * 2));
6252    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6253                                            Spacing * 3));
6254    TmpInst.addOperand(Inst.getOperand(1)); // lane
6255    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6256    TmpInst.addOperand(Inst.getOperand(5));
6257    Inst = TmpInst;
6258    return true;
6259  }
6260
6261  // VLD3DUP single 3-element structure to all lanes instructions.
6262  case ARM::VLD3DUPdAsm_8:
6263  case ARM::VLD3DUPdAsm_16:
6264  case ARM::VLD3DUPdAsm_32:
6265  case ARM::VLD3DUPqAsm_8:
6266  case ARM::VLD3DUPqAsm_16:
6267  case ARM::VLD3DUPqAsm_32: {
6268    MCInst TmpInst;
6269    unsigned Spacing;
6270    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6271    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6272    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6273                                            Spacing));
6274    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6275                                            Spacing * 2));
6276    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6277    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6278    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6279    TmpInst.addOperand(Inst.getOperand(4));
6280    Inst = TmpInst;
6281    return true;
6282  }
6283
6284  case ARM::VLD3DUPdWB_fixed_Asm_8:
6285  case ARM::VLD3DUPdWB_fixed_Asm_16:
6286  case ARM::VLD3DUPdWB_fixed_Asm_32:
6287  case ARM::VLD3DUPqWB_fixed_Asm_8:
6288  case ARM::VLD3DUPqWB_fixed_Asm_16:
6289  case ARM::VLD3DUPqWB_fixed_Asm_32: {
6290    MCInst TmpInst;
6291    unsigned Spacing;
6292    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6293    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6294    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6295                                            Spacing));
6296    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6297                                            Spacing * 2));
6298    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6299    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6300    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6301    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6302    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6303    TmpInst.addOperand(Inst.getOperand(4));
6304    Inst = TmpInst;
6305    return true;
6306  }
6307
6308  case ARM::VLD3DUPdWB_register_Asm_8:
6309  case ARM::VLD3DUPdWB_register_Asm_16:
6310  case ARM::VLD3DUPdWB_register_Asm_32:
6311  case ARM::VLD3DUPqWB_register_Asm_8:
6312  case ARM::VLD3DUPqWB_register_Asm_16:
6313  case ARM::VLD3DUPqWB_register_Asm_32: {
6314    MCInst TmpInst;
6315    unsigned Spacing;
6316    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6317    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6318    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6319                                            Spacing));
6320    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6321                                            Spacing * 2));
6322    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6323    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6324    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6325    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6326    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6327    TmpInst.addOperand(Inst.getOperand(5));
6328    Inst = TmpInst;
6329    return true;
6330  }
6331
6332  // VLD3 multiple 3-element structure instructions.
6333  case ARM::VLD3dAsm_8:
6334  case ARM::VLD3dAsm_16:
6335  case ARM::VLD3dAsm_32:
6336  case ARM::VLD3qAsm_8:
6337  case ARM::VLD3qAsm_16:
6338  case ARM::VLD3qAsm_32: {
6339    MCInst TmpInst;
6340    unsigned Spacing;
6341    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6342    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6343    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6344                                            Spacing));
6345    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6346                                            Spacing * 2));
6347    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6348    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6349    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6350    TmpInst.addOperand(Inst.getOperand(4));
6351    Inst = TmpInst;
6352    return true;
6353  }
6354
6355  case ARM::VLD3dWB_fixed_Asm_8:
6356  case ARM::VLD3dWB_fixed_Asm_16:
6357  case ARM::VLD3dWB_fixed_Asm_32:
6358  case ARM::VLD3qWB_fixed_Asm_8:
6359  case ARM::VLD3qWB_fixed_Asm_16:
6360  case ARM::VLD3qWB_fixed_Asm_32: {
6361    MCInst TmpInst;
6362    unsigned Spacing;
6363    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6364    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6365    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6366                                            Spacing));
6367    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6368                                            Spacing * 2));
6369    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6370    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6371    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6372    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6373    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6374    TmpInst.addOperand(Inst.getOperand(4));
6375    Inst = TmpInst;
6376    return true;
6377  }
6378
6379  case ARM::VLD3dWB_register_Asm_8:
6380  case ARM::VLD3dWB_register_Asm_16:
6381  case ARM::VLD3dWB_register_Asm_32:
6382  case ARM::VLD3qWB_register_Asm_8:
6383  case ARM::VLD3qWB_register_Asm_16:
6384  case ARM::VLD3qWB_register_Asm_32: {
6385    MCInst TmpInst;
6386    unsigned Spacing;
6387    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6388    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6389    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6390                                            Spacing));
6391    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6392                                            Spacing * 2));
6393    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6394    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6395    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6396    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6397    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6398    TmpInst.addOperand(Inst.getOperand(5));
6399    Inst = TmpInst;
6400    return true;
6401  }
6402
6403  // VLD4DUP single 3-element structure to all lanes instructions.
6404  case ARM::VLD4DUPdAsm_8:
6405  case ARM::VLD4DUPdAsm_16:
6406  case ARM::VLD4DUPdAsm_32:
6407  case ARM::VLD4DUPqAsm_8:
6408  case ARM::VLD4DUPqAsm_16:
6409  case ARM::VLD4DUPqAsm_32: {
6410    MCInst TmpInst;
6411    unsigned Spacing;
6412    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6413    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6414    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6415                                            Spacing));
6416    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6417                                            Spacing * 2));
6418    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6419                                            Spacing * 3));
6420    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6421    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6422    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6423    TmpInst.addOperand(Inst.getOperand(4));
6424    Inst = TmpInst;
6425    return true;
6426  }
6427
6428  case ARM::VLD4DUPdWB_fixed_Asm_8:
6429  case ARM::VLD4DUPdWB_fixed_Asm_16:
6430  case ARM::VLD4DUPdWB_fixed_Asm_32:
6431  case ARM::VLD4DUPqWB_fixed_Asm_8:
6432  case ARM::VLD4DUPqWB_fixed_Asm_16:
6433  case ARM::VLD4DUPqWB_fixed_Asm_32: {
6434    MCInst TmpInst;
6435    unsigned Spacing;
6436    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6437    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6438    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6439                                            Spacing));
6440    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6441                                            Spacing * 2));
6442    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6443                                            Spacing * 3));
6444    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6445    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6446    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6447    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6448    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6449    TmpInst.addOperand(Inst.getOperand(4));
6450    Inst = TmpInst;
6451    return true;
6452  }
6453
6454  case ARM::VLD4DUPdWB_register_Asm_8:
6455  case ARM::VLD4DUPdWB_register_Asm_16:
6456  case ARM::VLD4DUPdWB_register_Asm_32:
6457  case ARM::VLD4DUPqWB_register_Asm_8:
6458  case ARM::VLD4DUPqWB_register_Asm_16:
6459  case ARM::VLD4DUPqWB_register_Asm_32: {
6460    MCInst TmpInst;
6461    unsigned Spacing;
6462    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6463    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6464    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6465                                            Spacing));
6466    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6467                                            Spacing * 2));
6468    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6469                                            Spacing * 3));
6470    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6471    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6472    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6473    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6474    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6475    TmpInst.addOperand(Inst.getOperand(5));
6476    Inst = TmpInst;
6477    return true;
6478  }
6479
6480  // VLD4 multiple 4-element structure instructions.
6481  case ARM::VLD4dAsm_8:
6482  case ARM::VLD4dAsm_16:
6483  case ARM::VLD4dAsm_32:
6484  case ARM::VLD4qAsm_8:
6485  case ARM::VLD4qAsm_16:
6486  case ARM::VLD4qAsm_32: {
6487    MCInst TmpInst;
6488    unsigned Spacing;
6489    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6490    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6491    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6492                                            Spacing));
6493    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6494                                            Spacing * 2));
6495    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6496                                            Spacing * 3));
6497    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6498    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6499    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6500    TmpInst.addOperand(Inst.getOperand(4));
6501    Inst = TmpInst;
6502    return true;
6503  }
6504
6505  case ARM::VLD4dWB_fixed_Asm_8:
6506  case ARM::VLD4dWB_fixed_Asm_16:
6507  case ARM::VLD4dWB_fixed_Asm_32:
6508  case ARM::VLD4qWB_fixed_Asm_8:
6509  case ARM::VLD4qWB_fixed_Asm_16:
6510  case ARM::VLD4qWB_fixed_Asm_32: {
6511    MCInst TmpInst;
6512    unsigned Spacing;
6513    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6514    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6515    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6516                                            Spacing));
6517    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6518                                            Spacing * 2));
6519    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6520                                            Spacing * 3));
6521    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6522    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6523    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6524    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6525    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6526    TmpInst.addOperand(Inst.getOperand(4));
6527    Inst = TmpInst;
6528    return true;
6529  }
6530
6531  case ARM::VLD4dWB_register_Asm_8:
6532  case ARM::VLD4dWB_register_Asm_16:
6533  case ARM::VLD4dWB_register_Asm_32:
6534  case ARM::VLD4qWB_register_Asm_8:
6535  case ARM::VLD4qWB_register_Asm_16:
6536  case ARM::VLD4qWB_register_Asm_32: {
6537    MCInst TmpInst;
6538    unsigned Spacing;
6539    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6540    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6541    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6542                                            Spacing));
6543    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6544                                            Spacing * 2));
6545    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6546                                            Spacing * 3));
6547    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6548    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6549    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6550    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6551    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6552    TmpInst.addOperand(Inst.getOperand(5));
6553    Inst = TmpInst;
6554    return true;
6555  }
6556
6557  // VST3 multiple 3-element structure instructions.
6558  case ARM::VST3dAsm_8:
6559  case ARM::VST3dAsm_16:
6560  case ARM::VST3dAsm_32:
6561  case ARM::VST3qAsm_8:
6562  case ARM::VST3qAsm_16:
6563  case ARM::VST3qAsm_32: {
6564    MCInst TmpInst;
6565    unsigned Spacing;
6566    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6567    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6568    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6569    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6570    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6571                                            Spacing));
6572    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6573                                            Spacing * 2));
6574    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6575    TmpInst.addOperand(Inst.getOperand(4));
6576    Inst = TmpInst;
6577    return true;
6578  }
6579
6580  case ARM::VST3dWB_fixed_Asm_8:
6581  case ARM::VST3dWB_fixed_Asm_16:
6582  case ARM::VST3dWB_fixed_Asm_32:
6583  case ARM::VST3qWB_fixed_Asm_8:
6584  case ARM::VST3qWB_fixed_Asm_16:
6585  case ARM::VST3qWB_fixed_Asm_32: {
6586    MCInst TmpInst;
6587    unsigned Spacing;
6588    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6589    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6590    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6591    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6592    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6593    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6594    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6595                                            Spacing));
6596    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6597                                            Spacing * 2));
6598    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6599    TmpInst.addOperand(Inst.getOperand(4));
6600    Inst = TmpInst;
6601    return true;
6602  }
6603
6604  case ARM::VST3dWB_register_Asm_8:
6605  case ARM::VST3dWB_register_Asm_16:
6606  case ARM::VST3dWB_register_Asm_32:
6607  case ARM::VST3qWB_register_Asm_8:
6608  case ARM::VST3qWB_register_Asm_16:
6609  case ARM::VST3qWB_register_Asm_32: {
6610    MCInst TmpInst;
6611    unsigned Spacing;
6612    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6613    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6614    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6615    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6616    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6617    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6618    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6619                                            Spacing));
6620    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6621                                            Spacing * 2));
6622    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6623    TmpInst.addOperand(Inst.getOperand(5));
6624    Inst = TmpInst;
6625    return true;
6626  }
6627
6628  // VST4 multiple 3-element structure instructions.
6629  case ARM::VST4dAsm_8:
6630  case ARM::VST4dAsm_16:
6631  case ARM::VST4dAsm_32:
6632  case ARM::VST4qAsm_8:
6633  case ARM::VST4qAsm_16:
6634  case ARM::VST4qAsm_32: {
6635    MCInst TmpInst;
6636    unsigned Spacing;
6637    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6638    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6639    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6640    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6641    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6642                                            Spacing));
6643    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6644                                            Spacing * 2));
6645    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6646                                            Spacing * 3));
6647    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6648    TmpInst.addOperand(Inst.getOperand(4));
6649    Inst = TmpInst;
6650    return true;
6651  }
6652
6653  case ARM::VST4dWB_fixed_Asm_8:
6654  case ARM::VST4dWB_fixed_Asm_16:
6655  case ARM::VST4dWB_fixed_Asm_32:
6656  case ARM::VST4qWB_fixed_Asm_8:
6657  case ARM::VST4qWB_fixed_Asm_16:
6658  case ARM::VST4qWB_fixed_Asm_32: {
6659    MCInst TmpInst;
6660    unsigned Spacing;
6661    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6662    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6663    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6664    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6665    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6666    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6667    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6668                                            Spacing));
6669    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6670                                            Spacing * 2));
6671    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6672                                            Spacing * 3));
6673    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6674    TmpInst.addOperand(Inst.getOperand(4));
6675    Inst = TmpInst;
6676    return true;
6677  }
6678
6679  case ARM::VST4dWB_register_Asm_8:
6680  case ARM::VST4dWB_register_Asm_16:
6681  case ARM::VST4dWB_register_Asm_32:
6682  case ARM::VST4qWB_register_Asm_8:
6683  case ARM::VST4qWB_register_Asm_16:
6684  case ARM::VST4qWB_register_Asm_32: {
6685    MCInst TmpInst;
6686    unsigned Spacing;
6687    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6688    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6689    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6690    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6691    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6692    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6693    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6694                                            Spacing));
6695    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6696                                            Spacing * 2));
6697    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6698                                            Spacing * 3));
6699    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6700    TmpInst.addOperand(Inst.getOperand(5));
6701    Inst = TmpInst;
6702    return true;
6703  }
6704
6705  // Handle encoding choice for the shift-immediate instructions.
6706  case ARM::t2LSLri:
6707  case ARM::t2LSRri:
6708  case ARM::t2ASRri: {
6709    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6710        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6711        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6712        !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6713         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6714      unsigned NewOpc;
6715      switch (Inst.getOpcode()) {
6716      default: llvm_unreachable("unexpected opcode");
6717      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6718      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6719      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6720      }
6721      // The Thumb1 operands aren't in the same order. Awesome, eh?
6722      MCInst TmpInst;
6723      TmpInst.setOpcode(NewOpc);
6724      TmpInst.addOperand(Inst.getOperand(0));
6725      TmpInst.addOperand(Inst.getOperand(5));
6726      TmpInst.addOperand(Inst.getOperand(1));
6727      TmpInst.addOperand(Inst.getOperand(2));
6728      TmpInst.addOperand(Inst.getOperand(3));
6729      TmpInst.addOperand(Inst.getOperand(4));
6730      Inst = TmpInst;
6731      return true;
6732    }
6733    return false;
6734  }
6735
6736  // Handle the Thumb2 mode MOV complex aliases.
6737  case ARM::t2MOVsr:
6738  case ARM::t2MOVSsr: {
6739    // Which instruction to expand to depends on the CCOut operand and
6740    // whether we're in an IT block if the register operands are low
6741    // registers.
6742    bool isNarrow = false;
6743    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6744        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6745        isARMLowRegister(Inst.getOperand(2).getReg()) &&
6746        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6747        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6748      isNarrow = true;
6749    MCInst TmpInst;
6750    unsigned newOpc;
6751    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6752    default: llvm_unreachable("unexpected opcode!");
6753    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6754    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6755    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6756    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
6757    }
6758    TmpInst.setOpcode(newOpc);
6759    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6760    if (isNarrow)
6761      TmpInst.addOperand(MCOperand::CreateReg(
6762          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6763    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6764    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6765    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6766    TmpInst.addOperand(Inst.getOperand(5));
6767    if (!isNarrow)
6768      TmpInst.addOperand(MCOperand::CreateReg(
6769          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6770    Inst = TmpInst;
6771    return true;
6772  }
6773  case ARM::t2MOVsi:
6774  case ARM::t2MOVSsi: {
6775    // Which instruction to expand to depends on the CCOut operand and
6776    // whether we're in an IT block if the register operands are low
6777    // registers.
6778    bool isNarrow = false;
6779    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6780        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6781        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6782      isNarrow = true;
6783    MCInst TmpInst;
6784    unsigned newOpc;
6785    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6786    default: llvm_unreachable("unexpected opcode!");
6787    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6788    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6789    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6790    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6791    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6792    }
6793    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6794    if (Amount == 32) Amount = 0;
6795    TmpInst.setOpcode(newOpc);
6796    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6797    if (isNarrow)
6798      TmpInst.addOperand(MCOperand::CreateReg(
6799          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6800    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6801    if (newOpc != ARM::t2RRX)
6802      TmpInst.addOperand(MCOperand::CreateImm(Amount));
6803    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6804    TmpInst.addOperand(Inst.getOperand(4));
6805    if (!isNarrow)
6806      TmpInst.addOperand(MCOperand::CreateReg(
6807          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6808    Inst = TmpInst;
6809    return true;
6810  }
6811  // Handle the ARM mode MOV complex aliases.
6812  case ARM::ASRr:
6813  case ARM::LSRr:
6814  case ARM::LSLr:
6815  case ARM::RORr: {
6816    ARM_AM::ShiftOpc ShiftTy;
6817    switch(Inst.getOpcode()) {
6818    default: llvm_unreachable("unexpected opcode!");
6819    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6820    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6821    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6822    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6823    }
6824    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6825    MCInst TmpInst;
6826    TmpInst.setOpcode(ARM::MOVsr);
6827    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6828    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6829    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6830    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6831    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6832    TmpInst.addOperand(Inst.getOperand(4));
6833    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6834    Inst = TmpInst;
6835    return true;
6836  }
6837  case ARM::ASRi:
6838  case ARM::LSRi:
6839  case ARM::LSLi:
6840  case ARM::RORi: {
6841    ARM_AM::ShiftOpc ShiftTy;
6842    switch(Inst.getOpcode()) {
6843    default: llvm_unreachable("unexpected opcode!");
6844    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6845    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6846    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6847    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6848    }
6849    // A shift by zero is a plain MOVr, not a MOVsi.
6850    unsigned Amt = Inst.getOperand(2).getImm();
6851    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6852    // A shift by 32 should be encoded as 0 when permitted
6853    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6854      Amt = 0;
6855    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6856    MCInst TmpInst;
6857    TmpInst.setOpcode(Opc);
6858    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6859    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6860    if (Opc == ARM::MOVsi)
6861      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6862    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6863    TmpInst.addOperand(Inst.getOperand(4));
6864    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6865    Inst = TmpInst;
6866    return true;
6867  }
6868  case ARM::RRXi: {
6869    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6870    MCInst TmpInst;
6871    TmpInst.setOpcode(ARM::MOVsi);
6872    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6873    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6874    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6875    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6876    TmpInst.addOperand(Inst.getOperand(3));
6877    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6878    Inst = TmpInst;
6879    return true;
6880  }
6881  case ARM::t2LDMIA_UPD: {
6882    // If this is a load of a single register, then we should use
6883    // a post-indexed LDR instruction instead, per the ARM ARM.
6884    if (Inst.getNumOperands() != 5)
6885      return false;
6886    MCInst TmpInst;
6887    TmpInst.setOpcode(ARM::t2LDR_POST);
6888    TmpInst.addOperand(Inst.getOperand(4)); // Rt
6889    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6890    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6891    TmpInst.addOperand(MCOperand::CreateImm(4));
6892    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6893    TmpInst.addOperand(Inst.getOperand(3));
6894    Inst = TmpInst;
6895    return true;
6896  }
6897  case ARM::t2STMDB_UPD: {
6898    // If this is a store of a single register, then we should use
6899    // a pre-indexed STR instruction instead, per the ARM ARM.
6900    if (Inst.getNumOperands() != 5)
6901      return false;
6902    MCInst TmpInst;
6903    TmpInst.setOpcode(ARM::t2STR_PRE);
6904    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6905    TmpInst.addOperand(Inst.getOperand(4)); // Rt
6906    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6907    TmpInst.addOperand(MCOperand::CreateImm(-4));
6908    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6909    TmpInst.addOperand(Inst.getOperand(3));
6910    Inst = TmpInst;
6911    return true;
6912  }
6913  case ARM::LDMIA_UPD:
6914    // If this is a load of a single register via a 'pop', then we should use
6915    // a post-indexed LDR instruction instead, per the ARM ARM.
6916    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
6917        Inst.getNumOperands() == 5) {
6918      MCInst TmpInst;
6919      TmpInst.setOpcode(ARM::LDR_POST_IMM);
6920      TmpInst.addOperand(Inst.getOperand(4)); // Rt
6921      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6922      TmpInst.addOperand(Inst.getOperand(1)); // Rn
6923      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
6924      TmpInst.addOperand(MCOperand::CreateImm(4));
6925      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6926      TmpInst.addOperand(Inst.getOperand(3));
6927      Inst = TmpInst;
6928      return true;
6929    }
6930    break;
6931  case ARM::STMDB_UPD:
6932    // If this is a store of a single register via a 'push', then we should use
6933    // a pre-indexed STR instruction instead, per the ARM ARM.
6934    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
6935        Inst.getNumOperands() == 5) {
6936      MCInst TmpInst;
6937      TmpInst.setOpcode(ARM::STR_PRE_IMM);
6938      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6939      TmpInst.addOperand(Inst.getOperand(4)); // Rt
6940      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
6941      TmpInst.addOperand(MCOperand::CreateImm(-4));
6942      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6943      TmpInst.addOperand(Inst.getOperand(3));
6944      Inst = TmpInst;
6945    }
6946    break;
6947  case ARM::t2ADDri12:
6948    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
6949    // mnemonic was used (not "addw"), encoding T3 is preferred.
6950    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
6951        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
6952      break;
6953    Inst.setOpcode(ARM::t2ADDri);
6954    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
6955    break;
6956  case ARM::t2SUBri12:
6957    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
6958    // mnemonic was used (not "subw"), encoding T3 is preferred.
6959    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
6960        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
6961      break;
6962    Inst.setOpcode(ARM::t2SUBri);
6963    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
6964    break;
6965  case ARM::tADDi8:
6966    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
6967    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
6968    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
6969    // to encoding T1 if <Rd> is omitted."
6970    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
6971      Inst.setOpcode(ARM::tADDi3);
6972      return true;
6973    }
6974    break;
6975  case ARM::tSUBi8:
6976    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
6977    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
6978    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
6979    // to encoding T1 if <Rd> is omitted."
6980    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
6981      Inst.setOpcode(ARM::tSUBi3);
6982      return true;
6983    }
6984    break;
6985  case ARM::t2ADDri:
6986  case ARM::t2SUBri: {
6987    // If the destination and first source operand are the same, and
6988    // the flags are compatible with the current IT status, use encoding T2
6989    // instead of T3. For compatibility with the system 'as'. Make sure the
6990    // wide encoding wasn't explicit.
6991    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
6992        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
6993        (unsigned)Inst.getOperand(2).getImm() > 255 ||
6994        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
6995        (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
6996        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
6997         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
6998      break;
6999    MCInst TmpInst;
7000    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7001                      ARM::tADDi8 : ARM::tSUBi8);
7002    TmpInst.addOperand(Inst.getOperand(0));
7003    TmpInst.addOperand(Inst.getOperand(5));
7004    TmpInst.addOperand(Inst.getOperand(0));
7005    TmpInst.addOperand(Inst.getOperand(2));
7006    TmpInst.addOperand(Inst.getOperand(3));
7007    TmpInst.addOperand(Inst.getOperand(4));
7008    Inst = TmpInst;
7009    return true;
7010  }
7011  case ARM::t2ADDrr: {
7012    // If the destination and first source operand are the same, and
7013    // there's no setting of the flags, use encoding T2 instead of T3.
7014    // Note that this is only for ADD, not SUB. This mirrors the system
7015    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7016    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7017        Inst.getOperand(5).getReg() != 0 ||
7018        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7019         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7020      break;
7021    MCInst TmpInst;
7022    TmpInst.setOpcode(ARM::tADDhirr);
7023    TmpInst.addOperand(Inst.getOperand(0));
7024    TmpInst.addOperand(Inst.getOperand(0));
7025    TmpInst.addOperand(Inst.getOperand(2));
7026    TmpInst.addOperand(Inst.getOperand(3));
7027    TmpInst.addOperand(Inst.getOperand(4));
7028    Inst = TmpInst;
7029    return true;
7030  }
7031  case ARM::tADDrSP: {
7032    // If the non-SP source operand and the destination operand are not the
7033    // same, we need to use the 32-bit encoding if it's available.
7034    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7035      Inst.setOpcode(ARM::t2ADDrr);
7036      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7037      return true;
7038    }
7039    break;
7040  }
7041  case ARM::tB:
7042    // A Thumb conditional branch outside of an IT block is a tBcc.
7043    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7044      Inst.setOpcode(ARM::tBcc);
7045      return true;
7046    }
7047    break;
7048  case ARM::t2B:
7049    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7050    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7051      Inst.setOpcode(ARM::t2Bcc);
7052      return true;
7053    }
7054    break;
7055  case ARM::t2Bcc:
7056    // If the conditional is AL or we're in an IT block, we really want t2B.
7057    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7058      Inst.setOpcode(ARM::t2B);
7059      return true;
7060    }
7061    break;
7062  case ARM::tBcc:
7063    // If the conditional is AL, we really want tB.
7064    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7065      Inst.setOpcode(ARM::tB);
7066      return true;
7067    }
7068    break;
7069  case ARM::tLDMIA: {
7070    // If the register list contains any high registers, or if the writeback
7071    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7072    // instead if we're in Thumb2. Otherwise, this should have generated
7073    // an error in validateInstruction().
7074    unsigned Rn = Inst.getOperand(0).getReg();
7075    bool hasWritebackToken =
7076      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7077       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7078    bool listContainsBase;
7079    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7080        (!listContainsBase && !hasWritebackToken) ||
7081        (listContainsBase && hasWritebackToken)) {
7082      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7083      assert (isThumbTwo());
7084      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7085      // If we're switching to the updating version, we need to insert
7086      // the writeback tied operand.
7087      if (hasWritebackToken)
7088        Inst.insert(Inst.begin(),
7089                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7090      return true;
7091    }
7092    break;
7093  }
7094  case ARM::tSTMIA_UPD: {
7095    // If the register list contains any high registers, we need to use
7096    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7097    // should have generated an error in validateInstruction().
7098    unsigned Rn = Inst.getOperand(0).getReg();
7099    bool listContainsBase;
7100    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7101      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7102      assert (isThumbTwo());
7103      Inst.setOpcode(ARM::t2STMIA_UPD);
7104      return true;
7105    }
7106    break;
7107  }
7108  case ARM::tPOP: {
7109    bool listContainsBase;
7110    // If the register list contains any high registers, we need to use
7111    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7112    // should have generated an error in validateInstruction().
7113    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7114      return false;
7115    assert (isThumbTwo());
7116    Inst.setOpcode(ARM::t2LDMIA_UPD);
7117    // Add the base register and writeback operands.
7118    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7119    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7120    return true;
7121  }
7122  case ARM::tPUSH: {
7123    bool listContainsBase;
7124    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7125      return false;
7126    assert (isThumbTwo());
7127    Inst.setOpcode(ARM::t2STMDB_UPD);
7128    // Add the base register and writeback operands.
7129    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7130    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7131    return true;
7132  }
7133  case ARM::t2MOVi: {
7134    // If we can use the 16-bit encoding and the user didn't explicitly
7135    // request the 32-bit variant, transform it here.
7136    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7137        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7138        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7139         Inst.getOperand(4).getReg() == ARM::CPSR) ||
7140        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7141        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7142         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7143      // The operands aren't in the same order for tMOVi8...
7144      MCInst TmpInst;
7145      TmpInst.setOpcode(ARM::tMOVi8);
7146      TmpInst.addOperand(Inst.getOperand(0));
7147      TmpInst.addOperand(Inst.getOperand(4));
7148      TmpInst.addOperand(Inst.getOperand(1));
7149      TmpInst.addOperand(Inst.getOperand(2));
7150      TmpInst.addOperand(Inst.getOperand(3));
7151      Inst = TmpInst;
7152      return true;
7153    }
7154    break;
7155  }
7156  case ARM::t2MOVr: {
7157    // If we can use the 16-bit encoding and the user didn't explicitly
7158    // request the 32-bit variant, transform it here.
7159    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7160        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7161        Inst.getOperand(2).getImm() == ARMCC::AL &&
7162        Inst.getOperand(4).getReg() == ARM::CPSR &&
7163        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7164         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7165      // The operands aren't the same for tMOV[S]r... (no cc_out)
7166      MCInst TmpInst;
7167      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7168      TmpInst.addOperand(Inst.getOperand(0));
7169      TmpInst.addOperand(Inst.getOperand(1));
7170      TmpInst.addOperand(Inst.getOperand(2));
7171      TmpInst.addOperand(Inst.getOperand(3));
7172      Inst = TmpInst;
7173      return true;
7174    }
7175    break;
7176  }
7177  case ARM::t2SXTH:
7178  case ARM::t2SXTB:
7179  case ARM::t2UXTH:
7180  case ARM::t2UXTB: {
7181    // If we can use the 16-bit encoding and the user didn't explicitly
7182    // request the 32-bit variant, transform it here.
7183    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7184        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7185        Inst.getOperand(2).getImm() == 0 &&
7186        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7187         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7188      unsigned NewOpc;
7189      switch (Inst.getOpcode()) {
7190      default: llvm_unreachable("Illegal opcode!");
7191      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7192      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7193      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7194      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7195      }
7196      // The operands aren't the same for thumb1 (no rotate operand).
7197      MCInst TmpInst;
7198      TmpInst.setOpcode(NewOpc);
7199      TmpInst.addOperand(Inst.getOperand(0));
7200      TmpInst.addOperand(Inst.getOperand(1));
7201      TmpInst.addOperand(Inst.getOperand(3));
7202      TmpInst.addOperand(Inst.getOperand(4));
7203      Inst = TmpInst;
7204      return true;
7205    }
7206    break;
7207  }
7208  case ARM::MOVsi: {
7209    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7210    // rrx shifts and asr/lsr of #32 is encoded as 0
7211    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7212      return false;
7213    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7214      // Shifting by zero is accepted as a vanilla 'MOVr'
7215      MCInst TmpInst;
7216      TmpInst.setOpcode(ARM::MOVr);
7217      TmpInst.addOperand(Inst.getOperand(0));
7218      TmpInst.addOperand(Inst.getOperand(1));
7219      TmpInst.addOperand(Inst.getOperand(3));
7220      TmpInst.addOperand(Inst.getOperand(4));
7221      TmpInst.addOperand(Inst.getOperand(5));
7222      Inst = TmpInst;
7223      return true;
7224    }
7225    return false;
7226  }
7227  case ARM::ANDrsi:
7228  case ARM::ORRrsi:
7229  case ARM::EORrsi:
7230  case ARM::BICrsi:
7231  case ARM::SUBrsi:
7232  case ARM::ADDrsi: {
7233    unsigned newOpc;
7234    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7235    if (SOpc == ARM_AM::rrx) return false;
7236    switch (Inst.getOpcode()) {
7237    default: llvm_unreachable("unexpected opcode!");
7238    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7239    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7240    case ARM::EORrsi: newOpc = ARM::EORrr; break;
7241    case ARM::BICrsi: newOpc = ARM::BICrr; break;
7242    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7243    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7244    }
7245    // If the shift is by zero, use the non-shifted instruction definition.
7246    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) {
7247      MCInst TmpInst;
7248      TmpInst.setOpcode(newOpc);
7249      TmpInst.addOperand(Inst.getOperand(0));
7250      TmpInst.addOperand(Inst.getOperand(1));
7251      TmpInst.addOperand(Inst.getOperand(2));
7252      TmpInst.addOperand(Inst.getOperand(4));
7253      TmpInst.addOperand(Inst.getOperand(5));
7254      TmpInst.addOperand(Inst.getOperand(6));
7255      Inst = TmpInst;
7256      return true;
7257    }
7258    return false;
7259  }
7260  case ARM::ITasm:
7261  case ARM::t2IT: {
7262    // The mask bits for all but the first condition are represented as
7263    // the low bit of the condition code value implies 't'. We currently
7264    // always have 1 implies 't', so XOR toggle the bits if the low bit
7265    // of the condition code is zero.
7266    MCOperand &MO = Inst.getOperand(1);
7267    unsigned Mask = MO.getImm();
7268    unsigned OrigMask = Mask;
7269    unsigned TZ = CountTrailingZeros_32(Mask);
7270    if ((Inst.getOperand(0).getImm() & 1) == 0) {
7271      assert(Mask && TZ <= 3 && "illegal IT mask value!");
7272      for (unsigned i = 3; i != TZ; --i)
7273        Mask ^= 1 << i;
7274    }
7275    MO.setImm(Mask);
7276
7277    // Set up the IT block state according to the IT instruction we just
7278    // matched.
7279    assert(!inITBlock() && "nested IT blocks?!");
7280    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7281    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7282    ITState.CurPosition = 0;
7283    ITState.FirstCond = true;
7284    break;
7285  }
7286  }
7287  return false;
7288}
7289
7290unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7291  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7292  // suffix depending on whether they're in an IT block or not.
7293  unsigned Opc = Inst.getOpcode();
7294  const MCInstrDesc &MCID = getInstDesc(Opc);
7295  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7296    assert(MCID.hasOptionalDef() &&
7297           "optionally flag setting instruction missing optional def operand");
7298    assert(MCID.NumOperands == Inst.getNumOperands() &&
7299           "operand count mismatch!");
7300    // Find the optional-def operand (cc_out).
7301    unsigned OpNo;
7302    for (OpNo = 0;
7303         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7304         ++OpNo)
7305      ;
7306    // If we're parsing Thumb1, reject it completely.
7307    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7308      return Match_MnemonicFail;
7309    // If we're parsing Thumb2, which form is legal depends on whether we're
7310    // in an IT block.
7311    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7312        !inITBlock())
7313      return Match_RequiresITBlock;
7314    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7315        inITBlock())
7316      return Match_RequiresNotITBlock;
7317  }
7318  // Some high-register supporting Thumb1 encodings only allow both registers
7319  // to be from r0-r7 when in Thumb2.
7320  else if (Opc == ARM::tADDhirr && isThumbOne() &&
7321           isARMLowRegister(Inst.getOperand(1).getReg()) &&
7322           isARMLowRegister(Inst.getOperand(2).getReg()))
7323    return Match_RequiresThumb2;
7324  // Others only require ARMv6 or later.
7325  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7326           isARMLowRegister(Inst.getOperand(0).getReg()) &&
7327           isARMLowRegister(Inst.getOperand(1).getReg()))
7328    return Match_RequiresV6;
7329  return Match_Success;
7330}
7331
7332static const char *getSubtargetFeatureName(unsigned Val);
7333bool ARMAsmParser::
7334MatchAndEmitInstruction(SMLoc IDLoc,
7335                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7336                        MCStreamer &Out) {
7337  MCInst Inst;
7338  unsigned ErrorInfo;
7339  unsigned MatchResult;
7340  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
7341  switch (MatchResult) {
7342  default: break;
7343  case Match_Success:
7344    // Context sensitive operand constraints aren't handled by the matcher,
7345    // so check them here.
7346    if (validateInstruction(Inst, Operands)) {
7347      // Still progress the IT block, otherwise one wrong condition causes
7348      // nasty cascading errors.
7349      forwardITPosition();
7350      return true;
7351    }
7352
7353    // Some instructions need post-processing to, for example, tweak which
7354    // encoding is selected. Loop on it while changes happen so the
7355    // individual transformations can chain off each other. E.g.,
7356    // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7357    while (processInstruction(Inst, Operands))
7358      ;
7359
7360    // Only move forward at the very end so that everything in validate
7361    // and process gets a consistent answer about whether we're in an IT
7362    // block.
7363    forwardITPosition();
7364
7365    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7366    // doesn't actually encode.
7367    if (Inst.getOpcode() == ARM::ITasm)
7368      return false;
7369
7370    Inst.setLoc(IDLoc);
7371    Out.EmitInstruction(Inst);
7372    return false;
7373  case Match_MissingFeature: {
7374    assert(ErrorInfo && "Unknown missing feature!");
7375    // Special case the error message for the very common case where only
7376    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7377    std::string Msg = "instruction requires:";
7378    unsigned Mask = 1;
7379    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7380      if (ErrorInfo & Mask) {
7381        Msg += " ";
7382        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7383      }
7384      Mask <<= 1;
7385    }
7386    return Error(IDLoc, Msg);
7387  }
7388  case Match_InvalidOperand: {
7389    SMLoc ErrorLoc = IDLoc;
7390    if (ErrorInfo != ~0U) {
7391      if (ErrorInfo >= Operands.size())
7392        return Error(IDLoc, "too few operands for instruction");
7393
7394      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7395      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7396    }
7397
7398    return Error(ErrorLoc, "invalid operand for instruction");
7399  }
7400  case Match_MnemonicFail:
7401    return Error(IDLoc, "invalid instruction",
7402                 ((ARMOperand*)Operands[0])->getLocRange());
7403  case Match_ConversionFail:
7404    // The converter function will have already emitted a diagnostic.
7405    return true;
7406  case Match_RequiresNotITBlock:
7407    return Error(IDLoc, "flag setting instruction only valid outside IT block");
7408  case Match_RequiresITBlock:
7409    return Error(IDLoc, "instruction only valid inside IT block");
7410  case Match_RequiresV6:
7411    return Error(IDLoc, "instruction variant requires ARMv6 or later");
7412  case Match_RequiresThumb2:
7413    return Error(IDLoc, "instruction variant requires Thumb2");
7414  }
7415
7416  llvm_unreachable("Implement any new match types added!");
7417}
7418
7419/// parseDirective parses the arm specific directives
7420bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7421  StringRef IDVal = DirectiveID.getIdentifier();
7422  if (IDVal == ".word")
7423    return parseDirectiveWord(4, DirectiveID.getLoc());
7424  else if (IDVal == ".thumb")
7425    return parseDirectiveThumb(DirectiveID.getLoc());
7426  else if (IDVal == ".arm")
7427    return parseDirectiveARM(DirectiveID.getLoc());
7428  else if (IDVal == ".thumb_func")
7429    return parseDirectiveThumbFunc(DirectiveID.getLoc());
7430  else if (IDVal == ".code")
7431    return parseDirectiveCode(DirectiveID.getLoc());
7432  else if (IDVal == ".syntax")
7433    return parseDirectiveSyntax(DirectiveID.getLoc());
7434  else if (IDVal == ".unreq")
7435    return parseDirectiveUnreq(DirectiveID.getLoc());
7436  else if (IDVal == ".arch")
7437    return parseDirectiveArch(DirectiveID.getLoc());
7438  else if (IDVal == ".eabi_attribute")
7439    return parseDirectiveEabiAttr(DirectiveID.getLoc());
7440  return true;
7441}
7442
7443/// parseDirectiveWord
7444///  ::= .word [ expression (, expression)* ]
7445bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7446  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7447    for (;;) {
7448      const MCExpr *Value;
7449      if (getParser().ParseExpression(Value))
7450        return true;
7451
7452      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
7453
7454      if (getLexer().is(AsmToken::EndOfStatement))
7455        break;
7456
7457      // FIXME: Improve diagnostic.
7458      if (getLexer().isNot(AsmToken::Comma))
7459        return Error(L, "unexpected token in directive");
7460      Parser.Lex();
7461    }
7462  }
7463
7464  Parser.Lex();
7465  return false;
7466}
7467
7468/// parseDirectiveThumb
7469///  ::= .thumb
7470bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7471  if (getLexer().isNot(AsmToken::EndOfStatement))
7472    return Error(L, "unexpected token in directive");
7473  Parser.Lex();
7474
7475  if (!isThumb())
7476    SwitchMode();
7477  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7478  return false;
7479}
7480
7481/// parseDirectiveARM
7482///  ::= .arm
7483bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7484  if (getLexer().isNot(AsmToken::EndOfStatement))
7485    return Error(L, "unexpected token in directive");
7486  Parser.Lex();
7487
7488  if (isThumb())
7489    SwitchMode();
7490  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7491  return false;
7492}
7493
7494/// parseDirectiveThumbFunc
7495///  ::= .thumbfunc symbol_name
7496bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7497  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7498  bool isMachO = MAI.hasSubsectionsViaSymbols();
7499  StringRef Name;
7500  bool needFuncName = true;
7501
7502  // Darwin asm has (optionally) function name after .thumb_func direction
7503  // ELF doesn't
7504  if (isMachO) {
7505    const AsmToken &Tok = Parser.getTok();
7506    if (Tok.isNot(AsmToken::EndOfStatement)) {
7507      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7508        return Error(L, "unexpected token in .thumb_func directive");
7509      Name = Tok.getIdentifier();
7510      Parser.Lex(); // Consume the identifier token.
7511      needFuncName = false;
7512    }
7513  }
7514
7515  if (getLexer().isNot(AsmToken::EndOfStatement))
7516    return Error(L, "unexpected token in directive");
7517
7518  // Eat the end of statement and any blank lines that follow.
7519  while (getLexer().is(AsmToken::EndOfStatement))
7520    Parser.Lex();
7521
7522  // FIXME: assuming function name will be the line following .thumb_func
7523  // We really should be checking the next symbol definition even if there's
7524  // stuff in between.
7525  if (needFuncName) {
7526    Name = Parser.getTok().getIdentifier();
7527  }
7528
7529  // Mark symbol as a thumb symbol.
7530  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7531  getParser().getStreamer().EmitThumbFunc(Func);
7532  return false;
7533}
7534
7535/// parseDirectiveSyntax
7536///  ::= .syntax unified | divided
7537bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7538  const AsmToken &Tok = Parser.getTok();
7539  if (Tok.isNot(AsmToken::Identifier))
7540    return Error(L, "unexpected token in .syntax directive");
7541  StringRef Mode = Tok.getString();
7542  if (Mode == "unified" || Mode == "UNIFIED")
7543    Parser.Lex();
7544  else if (Mode == "divided" || Mode == "DIVIDED")
7545    return Error(L, "'.syntax divided' arm asssembly not supported");
7546  else
7547    return Error(L, "unrecognized syntax mode in .syntax directive");
7548
7549  if (getLexer().isNot(AsmToken::EndOfStatement))
7550    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7551  Parser.Lex();
7552
7553  // TODO tell the MC streamer the mode
7554  // getParser().getStreamer().Emit???();
7555  return false;
7556}
7557
7558/// parseDirectiveCode
7559///  ::= .code 16 | 32
7560bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7561  const AsmToken &Tok = Parser.getTok();
7562  if (Tok.isNot(AsmToken::Integer))
7563    return Error(L, "unexpected token in .code directive");
7564  int64_t Val = Parser.getTok().getIntVal();
7565  if (Val == 16)
7566    Parser.Lex();
7567  else if (Val == 32)
7568    Parser.Lex();
7569  else
7570    return Error(L, "invalid operand to .code directive");
7571
7572  if (getLexer().isNot(AsmToken::EndOfStatement))
7573    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7574  Parser.Lex();
7575
7576  if (Val == 16) {
7577    if (!isThumb())
7578      SwitchMode();
7579    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7580  } else {
7581    if (isThumb())
7582      SwitchMode();
7583    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7584  }
7585
7586  return false;
7587}
7588
7589/// parseDirectiveReq
7590///  ::= name .req registername
7591bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7592  Parser.Lex(); // Eat the '.req' token.
7593  unsigned Reg;
7594  SMLoc SRegLoc, ERegLoc;
7595  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7596    Parser.EatToEndOfStatement();
7597    return Error(SRegLoc, "register name expected");
7598  }
7599
7600  // Shouldn't be anything else.
7601  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7602    Parser.EatToEndOfStatement();
7603    return Error(Parser.getTok().getLoc(),
7604                 "unexpected input in .req directive.");
7605  }
7606
7607  Parser.Lex(); // Consume the EndOfStatement
7608
7609  if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7610    return Error(SRegLoc, "redefinition of '" + Name +
7611                          "' does not match original.");
7612
7613  return false;
7614}
7615
7616/// parseDirectiveUneq
7617///  ::= .unreq registername
7618bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7619  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7620    Parser.EatToEndOfStatement();
7621    return Error(L, "unexpected input in .unreq directive.");
7622  }
7623  RegisterReqs.erase(Parser.getTok().getIdentifier());
7624  Parser.Lex(); // Eat the identifier.
7625  return false;
7626}
7627
7628/// parseDirectiveArch
7629///  ::= .arch token
7630bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7631  return true;
7632}
7633
7634/// parseDirectiveEabiAttr
7635///  ::= .eabi_attribute int, int
7636bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7637  return true;
7638}
7639
7640extern "C" void LLVMInitializeARMAsmLexer();
7641
7642/// Force static initialization.
7643extern "C" void LLVMInitializeARMAsmParser() {
7644  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7645  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7646  LLVMInitializeARMAsmLexer();
7647}
7648
7649#define GET_REGISTER_MATCHER
7650#define GET_SUBTARGET_FEATURE_NAME
7651#define GET_MATCHER_IMPLEMENTATION
7652#include "ARMGenAsmMatcher.inc"
7653