ARMAsmParser.cpp revision a8307dd1c9279cbde1f3497e530d2ed9d014a0c5 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringExtras.h"
34#include "llvm/ADT/StringSwitch.h"
35#include "llvm/ADT/Twine.h"
36
37using namespace llvm;
38
39namespace {
40
41class ARMOperand;
42
43class ARMAsmParser : public MCTargetAsmParser {
44  MCSubtargetInfo &STI;
45  MCAsmParser &Parser;
46
47  struct {
48    ARMCC::CondCodes Cond;    // Condition for IT block.
49    unsigned Mask:4;          // Condition mask for instructions.
50                              // Starting at first 1 (from lsb).
51                              //   '1'  condition as indicated in IT.
52                              //   '0'  inverse of condition (else).
53                              // Count of instructions in IT block is
54                              // 4 - trailingzeroes(mask)
55
56    bool FirstCond;           // Explicit flag for when we're parsing the
57                              // First instruction in the IT block. It's
58                              // implied in the mask, so needs special
59                              // handling.
60
61    unsigned CurPosition;     // Current position in parsing of IT
62                              // block. In range [0,3]. Initialized
63                              // according to count of instructions in block.
64                              // ~0U if no active IT block.
65  } ITState;
66  bool inITBlock() { return ITState.CurPosition != ~0U;}
67  void forwardITPosition() {
68    if (!inITBlock()) return;
69    // Move to the next instruction in the IT block, if there is one. If not,
70    // mark the block as done.
71    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72    if (++ITState.CurPosition == 5 - TZ)
73      ITState.CurPosition = ~0U; // Done with the IT block after this.
74  }
75
76
77  MCAsmParser &getParser() const { return Parser; }
78  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
79
80  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
82
83  int tryParseRegister();
84  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90  const MCExpr *applyPrefixToExpr(const MCExpr *E,
91                                  MCSymbolRefExpr::VariantKind Variant);
92
93
94  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
95                              unsigned &ShiftAmount);
96  bool parseDirectiveWord(unsigned Size, SMLoc L);
97  bool parseDirectiveThumb(SMLoc L);
98  bool parseDirectiveThumbFunc(SMLoc L);
99  bool parseDirectiveCode(SMLoc L);
100  bool parseDirectiveSyntax(SMLoc L);
101
102  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
103                          bool &CarrySetting, unsigned &ProcessorIMod,
104                          StringRef &ITMask);
105  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
106                             bool &CanAcceptPredicationCode);
107
108  bool isThumb() const {
109    // FIXME: Can tablegen auto-generate this?
110    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
111  }
112  bool isThumbOne() const {
113    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
114  }
115  bool isThumbTwo() const {
116    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
117  }
118  bool hasV6Ops() const {
119    return STI.getFeatureBits() & ARM::HasV6Ops;
120  }
121  void SwitchMode() {
122    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
123    setAvailableFeatures(FB);
124  }
125
126  /// @name Auto-generated Match Functions
127  /// {
128
129#define GET_ASSEMBLER_HEADER
130#include "ARMGenAsmMatcher.inc"
131
132  /// }
133
134  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
135  OperandMatchResultTy parseCoprocNumOperand(
136    SmallVectorImpl<MCParsedAsmOperand*>&);
137  OperandMatchResultTy parseCoprocRegOperand(
138    SmallVectorImpl<MCParsedAsmOperand*>&);
139  OperandMatchResultTy parseMemBarrierOptOperand(
140    SmallVectorImpl<MCParsedAsmOperand*>&);
141  OperandMatchResultTy parseProcIFlagsOperand(
142    SmallVectorImpl<MCParsedAsmOperand*>&);
143  OperandMatchResultTy parseMSRMaskOperand(
144    SmallVectorImpl<MCParsedAsmOperand*>&);
145  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
146                                   StringRef Op, int Low, int High);
147  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
148    return parsePKHImm(O, "lsl", 0, 31);
149  }
150  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
151    return parsePKHImm(O, "asr", 1, 32);
152  }
153  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
154  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
155  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
156  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
157  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
158  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
159
160  // Asm Match Converter Methods
161  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
162                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
163  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
164                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
165  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
166                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
167  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
168                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
169  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
170                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
171  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
172                             const SmallVectorImpl<MCParsedAsmOperand*> &);
173  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
174                             const SmallVectorImpl<MCParsedAsmOperand*> &);
175  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
176                             const SmallVectorImpl<MCParsedAsmOperand*> &);
177  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
178                             const SmallVectorImpl<MCParsedAsmOperand*> &);
179  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
180                  const SmallVectorImpl<MCParsedAsmOperand*> &);
181  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
182                  const SmallVectorImpl<MCParsedAsmOperand*> &);
183  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
184                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
185  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
186                        const SmallVectorImpl<MCParsedAsmOperand*> &);
187
188  bool validateInstruction(MCInst &Inst,
189                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
190  void processInstruction(MCInst &Inst,
191                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
192  bool shouldOmitCCOutOperand(StringRef Mnemonic,
193                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
194
195public:
196  enum ARMMatchResultTy {
197    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
198    Match_RequiresNotITBlock,
199    Match_RequiresV6,
200    Match_RequiresThumb2
201  };
202
203  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
204    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
205    MCAsmParserExtension::Initialize(_Parser);
206
207    // Initialize the set of available features.
208    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
209
210    // Not in an ITBlock to start with.
211    ITState.CurPosition = ~0U;
212  }
213
214  // Implementation of the MCTargetAsmParser interface:
215  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
216  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
217                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
218  bool ParseDirective(AsmToken DirectiveID);
219
220  unsigned checkTargetMatchPredicate(MCInst &Inst);
221
222  bool MatchAndEmitInstruction(SMLoc IDLoc,
223                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
224                               MCStreamer &Out);
225};
226} // end anonymous namespace
227
228namespace {
229
230/// ARMOperand - Instances of this class represent a parsed ARM machine
231/// instruction.
232class ARMOperand : public MCParsedAsmOperand {
233  enum KindTy {
234    CondCode,
235    CCOut,
236    ITCondMask,
237    CoprocNum,
238    CoprocReg,
239    Immediate,
240    MemBarrierOpt,
241    Memory,
242    PostIndexRegister,
243    MSRMask,
244    ProcIFlags,
245    Register,
246    RegisterList,
247    DPRRegisterList,
248    SPRRegisterList,
249    ShiftedRegister,
250    ShiftedImmediate,
251    ShifterImmediate,
252    RotateImmediate,
253    BitfieldDescriptor,
254    Token
255  } Kind;
256
257  SMLoc StartLoc, EndLoc;
258  SmallVector<unsigned, 8> Registers;
259
260  union {
261    struct {
262      ARMCC::CondCodes Val;
263    } CC;
264
265    struct {
266      unsigned Val;
267    } Cop;
268
269    struct {
270      unsigned Mask:4;
271    } ITMask;
272
273    struct {
274      ARM_MB::MemBOpt Val;
275    } MBOpt;
276
277    struct {
278      ARM_PROC::IFlags Val;
279    } IFlags;
280
281    struct {
282      unsigned Val;
283    } MMask;
284
285    struct {
286      const char *Data;
287      unsigned Length;
288    } Tok;
289
290    struct {
291      unsigned RegNum;
292    } Reg;
293
294    struct {
295      const MCExpr *Val;
296    } Imm;
297
298    /// Combined record for all forms of ARM address expressions.
299    struct {
300      unsigned BaseRegNum;
301      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
302      // was specified.
303      const MCConstantExpr *OffsetImm;  // Offset immediate value
304      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
305      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
306      unsigned ShiftImm;      // shift for OffsetReg.
307      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
308    } Mem;
309
310    struct {
311      unsigned RegNum;
312      bool isAdd;
313      ARM_AM::ShiftOpc ShiftTy;
314      unsigned ShiftImm;
315    } PostIdxReg;
316
317    struct {
318      bool isASR;
319      unsigned Imm;
320    } ShifterImm;
321    struct {
322      ARM_AM::ShiftOpc ShiftTy;
323      unsigned SrcReg;
324      unsigned ShiftReg;
325      unsigned ShiftImm;
326    } RegShiftedReg;
327    struct {
328      ARM_AM::ShiftOpc ShiftTy;
329      unsigned SrcReg;
330      unsigned ShiftImm;
331    } RegShiftedImm;
332    struct {
333      unsigned Imm;
334    } RotImm;
335    struct {
336      unsigned LSB;
337      unsigned Width;
338    } Bitfield;
339  };
340
341  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
342public:
343  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
344    Kind = o.Kind;
345    StartLoc = o.StartLoc;
346    EndLoc = o.EndLoc;
347    switch (Kind) {
348    case CondCode:
349      CC = o.CC;
350      break;
351    case ITCondMask:
352      ITMask = o.ITMask;
353      break;
354    case Token:
355      Tok = o.Tok;
356      break;
357    case CCOut:
358    case Register:
359      Reg = o.Reg;
360      break;
361    case RegisterList:
362    case DPRRegisterList:
363    case SPRRegisterList:
364      Registers = o.Registers;
365      break;
366    case CoprocNum:
367    case CoprocReg:
368      Cop = o.Cop;
369      break;
370    case Immediate:
371      Imm = o.Imm;
372      break;
373    case MemBarrierOpt:
374      MBOpt = o.MBOpt;
375      break;
376    case Memory:
377      Mem = o.Mem;
378      break;
379    case PostIndexRegister:
380      PostIdxReg = o.PostIdxReg;
381      break;
382    case MSRMask:
383      MMask = o.MMask;
384      break;
385    case ProcIFlags:
386      IFlags = o.IFlags;
387      break;
388    case ShifterImmediate:
389      ShifterImm = o.ShifterImm;
390      break;
391    case ShiftedRegister:
392      RegShiftedReg = o.RegShiftedReg;
393      break;
394    case ShiftedImmediate:
395      RegShiftedImm = o.RegShiftedImm;
396      break;
397    case RotateImmediate:
398      RotImm = o.RotImm;
399      break;
400    case BitfieldDescriptor:
401      Bitfield = o.Bitfield;
402      break;
403    }
404  }
405
406  /// getStartLoc - Get the location of the first token of this operand.
407  SMLoc getStartLoc() const { return StartLoc; }
408  /// getEndLoc - Get the location of the last token of this operand.
409  SMLoc getEndLoc() const { return EndLoc; }
410
411  ARMCC::CondCodes getCondCode() const {
412    assert(Kind == CondCode && "Invalid access!");
413    return CC.Val;
414  }
415
416  unsigned getCoproc() const {
417    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
418    return Cop.Val;
419  }
420
421  StringRef getToken() const {
422    assert(Kind == Token && "Invalid access!");
423    return StringRef(Tok.Data, Tok.Length);
424  }
425
426  unsigned getReg() const {
427    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
428    return Reg.RegNum;
429  }
430
431  const SmallVectorImpl<unsigned> &getRegList() const {
432    assert((Kind == RegisterList || Kind == DPRRegisterList ||
433            Kind == SPRRegisterList) && "Invalid access!");
434    return Registers;
435  }
436
437  const MCExpr *getImm() const {
438    assert(Kind == Immediate && "Invalid access!");
439    return Imm.Val;
440  }
441
442  ARM_MB::MemBOpt getMemBarrierOpt() const {
443    assert(Kind == MemBarrierOpt && "Invalid access!");
444    return MBOpt.Val;
445  }
446
447  ARM_PROC::IFlags getProcIFlags() const {
448    assert(Kind == ProcIFlags && "Invalid access!");
449    return IFlags.Val;
450  }
451
452  unsigned getMSRMask() const {
453    assert(Kind == MSRMask && "Invalid access!");
454    return MMask.Val;
455  }
456
457  bool isCoprocNum() const { return Kind == CoprocNum; }
458  bool isCoprocReg() const { return Kind == CoprocReg; }
459  bool isCondCode() const { return Kind == CondCode; }
460  bool isCCOut() const { return Kind == CCOut; }
461  bool isITMask() const { return Kind == ITCondMask; }
462  bool isITCondCode() const { return Kind == CondCode; }
463  bool isImm() const { return Kind == Immediate; }
464  bool isImm0_1020s4() const {
465    if (Kind != Immediate)
466      return false;
467    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
468    if (!CE) return false;
469    int64_t Value = CE->getValue();
470    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
471  }
472  bool isImm0_508s4() const {
473    if (Kind != Immediate)
474      return false;
475    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
476    if (!CE) return false;
477    int64_t Value = CE->getValue();
478    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
479  }
480  bool isImm0_255() const {
481    if (Kind != Immediate)
482      return false;
483    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
484    if (!CE) return false;
485    int64_t Value = CE->getValue();
486    return Value >= 0 && Value < 256;
487  }
488  bool isImm0_7() const {
489    if (Kind != Immediate)
490      return false;
491    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
492    if (!CE) return false;
493    int64_t Value = CE->getValue();
494    return Value >= 0 && Value < 8;
495  }
496  bool isImm0_15() const {
497    if (Kind != Immediate)
498      return false;
499    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
500    if (!CE) return false;
501    int64_t Value = CE->getValue();
502    return Value >= 0 && Value < 16;
503  }
504  bool isImm0_31() const {
505    if (Kind != Immediate)
506      return false;
507    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
508    if (!CE) return false;
509    int64_t Value = CE->getValue();
510    return Value >= 0 && Value < 32;
511  }
512  bool isImm1_16() const {
513    if (Kind != Immediate)
514      return false;
515    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
516    if (!CE) return false;
517    int64_t Value = CE->getValue();
518    return Value > 0 && Value < 17;
519  }
520  bool isImm1_32() const {
521    if (Kind != Immediate)
522      return false;
523    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
524    if (!CE) return false;
525    int64_t Value = CE->getValue();
526    return Value > 0 && Value < 33;
527  }
528  bool isImm0_65535() const {
529    if (Kind != Immediate)
530      return false;
531    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
532    if (!CE) return false;
533    int64_t Value = CE->getValue();
534    return Value >= 0 && Value < 65536;
535  }
536  bool isImm0_65535Expr() const {
537    if (Kind != Immediate)
538      return false;
539    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
540    // If it's not a constant expression, it'll generate a fixup and be
541    // handled later.
542    if (!CE) return true;
543    int64_t Value = CE->getValue();
544    return Value >= 0 && Value < 65536;
545  }
546  bool isImm24bit() const {
547    if (Kind != Immediate)
548      return false;
549    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
550    if (!CE) return false;
551    int64_t Value = CE->getValue();
552    return Value >= 0 && Value <= 0xffffff;
553  }
554  bool isImmThumbSR() const {
555    if (Kind != Immediate)
556      return false;
557    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
558    if (!CE) return false;
559    int64_t Value = CE->getValue();
560    return Value > 0 && Value < 33;
561  }
562  bool isPKHLSLImm() const {
563    if (Kind != Immediate)
564      return false;
565    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
566    if (!CE) return false;
567    int64_t Value = CE->getValue();
568    return Value >= 0 && Value < 32;
569  }
570  bool isPKHASRImm() const {
571    if (Kind != Immediate)
572      return false;
573    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
574    if (!CE) return false;
575    int64_t Value = CE->getValue();
576    return Value > 0 && Value <= 32;
577  }
578  bool isARMSOImm() const {
579    if (Kind != Immediate)
580      return false;
581    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
582    if (!CE) return false;
583    int64_t Value = CE->getValue();
584    return ARM_AM::getSOImmVal(Value) != -1;
585  }
586  bool isT2SOImm() const {
587    if (Kind != Immediate)
588      return false;
589    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
590    if (!CE) return false;
591    int64_t Value = CE->getValue();
592    return ARM_AM::getT2SOImmVal(Value) != -1;
593  }
594  bool isSetEndImm() const {
595    if (Kind != Immediate)
596      return false;
597    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
598    if (!CE) return false;
599    int64_t Value = CE->getValue();
600    return Value == 1 || Value == 0;
601  }
602  bool isReg() const { return Kind == Register; }
603  bool isRegList() const { return Kind == RegisterList; }
604  bool isDPRRegList() const { return Kind == DPRRegisterList; }
605  bool isSPRRegList() const { return Kind == SPRRegisterList; }
606  bool isToken() const { return Kind == Token; }
607  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
608  bool isMemory() const { return Kind == Memory; }
609  bool isShifterImm() const { return Kind == ShifterImmediate; }
610  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
611  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
612  bool isRotImm() const { return Kind == RotateImmediate; }
613  bool isBitfield() const { return Kind == BitfieldDescriptor; }
614  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
615  bool isPostIdxReg() const {
616    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
617  }
618  bool isMemNoOffset() const {
619    if (Kind != Memory)
620      return false;
621    // No offset of any kind.
622    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
623  }
624  bool isAddrMode2() const {
625    if (Kind != Memory)
626      return false;
627    // Check for register offset.
628    if (Mem.OffsetRegNum) return true;
629    // Immediate offset in range [-4095, 4095].
630    if (!Mem.OffsetImm) return true;
631    int64_t Val = Mem.OffsetImm->getValue();
632    return Val > -4096 && Val < 4096;
633  }
634  bool isAM2OffsetImm() const {
635    if (Kind != Immediate)
636      return false;
637    // Immediate offset in range [-4095, 4095].
638    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
639    if (!CE) return false;
640    int64_t Val = CE->getValue();
641    return Val > -4096 && Val < 4096;
642  }
643  bool isAddrMode3() const {
644    if (Kind != Memory)
645      return false;
646    // No shifts are legal for AM3.
647    if (Mem.ShiftType != ARM_AM::no_shift) return false;
648    // Check for register offset.
649    if (Mem.OffsetRegNum) return true;
650    // Immediate offset in range [-255, 255].
651    if (!Mem.OffsetImm) return true;
652    int64_t Val = Mem.OffsetImm->getValue();
653    return Val > -256 && Val < 256;
654  }
655  bool isAM3Offset() const {
656    if (Kind != Immediate && Kind != PostIndexRegister)
657      return false;
658    if (Kind == PostIndexRegister)
659      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
660    // Immediate offset in range [-255, 255].
661    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
662    if (!CE) return false;
663    int64_t Val = CE->getValue();
664    // Special case, #-0 is INT32_MIN.
665    return (Val > -256 && Val < 256) || Val == INT32_MIN;
666  }
667  bool isAddrMode5() const {
668    if (Kind != Memory)
669      return false;
670    // Check for register offset.
671    if (Mem.OffsetRegNum) return false;
672    // Immediate offset in range [-1020, 1020] and a multiple of 4.
673    if (!Mem.OffsetImm) return true;
674    int64_t Val = Mem.OffsetImm->getValue();
675    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
676           Val == INT32_MIN;
677  }
678  bool isMemRegOffset() const {
679    if (Kind != Memory || !Mem.OffsetRegNum)
680      return false;
681    return true;
682  }
683  bool isMemThumbRR() const {
684    // Thumb reg+reg addressing is simple. Just two registers, a base and
685    // an offset. No shifts, negations or any other complicating factors.
686    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
687        Mem.ShiftType != ARM_AM::no_shift)
688      return false;
689    return isARMLowRegister(Mem.BaseRegNum) &&
690      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
691  }
692  bool isMemThumbRIs4() const {
693    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
694        !isARMLowRegister(Mem.BaseRegNum))
695      return false;
696    // Immediate offset, multiple of 4 in range [0, 124].
697    if (!Mem.OffsetImm) return true;
698    int64_t Val = Mem.OffsetImm->getValue();
699    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
700  }
701  bool isMemThumbRIs2() const {
702    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
703        !isARMLowRegister(Mem.BaseRegNum))
704      return false;
705    // Immediate offset, multiple of 4 in range [0, 62].
706    if (!Mem.OffsetImm) return true;
707    int64_t Val = Mem.OffsetImm->getValue();
708    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
709  }
710  bool isMemThumbRIs1() const {
711    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
712        !isARMLowRegister(Mem.BaseRegNum))
713      return false;
714    // Immediate offset in range [0, 31].
715    if (!Mem.OffsetImm) return true;
716    int64_t Val = Mem.OffsetImm->getValue();
717    return Val >= 0 && Val <= 31;
718  }
719  bool isMemThumbSPI() const {
720    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
721      return false;
722    // Immediate offset, multiple of 4 in range [0, 1020].
723    if (!Mem.OffsetImm) return true;
724    int64_t Val = Mem.OffsetImm->getValue();
725    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
726  }
727  bool isMemImm8Offset() const {
728    if (Kind != Memory || Mem.OffsetRegNum != 0)
729      return false;
730    // Immediate offset in range [-255, 255].
731    if (!Mem.OffsetImm) return true;
732    int64_t Val = Mem.OffsetImm->getValue();
733    return Val > -256 && Val < 256;
734  }
735  bool isMemNegImm8Offset() const {
736    if (Kind != Memory || Mem.OffsetRegNum != 0)
737      return false;
738    // Immediate offset in range [-255, -1].
739    if (!Mem.OffsetImm) return true;
740    int64_t Val = Mem.OffsetImm->getValue();
741    return Val > -256 && Val < 0;
742  }
743  bool isMemUImm12Offset() const {
744    // If we have an immediate that's not a constant, treat it as a label
745    // reference needing a fixup. If it is a constant, it's something else
746    // and we reject it.
747    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
748      return true;
749
750    if (Kind != Memory || Mem.OffsetRegNum != 0)
751      return false;
752    // Immediate offset in range [0, 4095].
753    if (!Mem.OffsetImm) return true;
754    int64_t Val = Mem.OffsetImm->getValue();
755    return (Val >= 0 && Val < 4096);
756  }
757  bool isMemImm12Offset() const {
758    // If we have an immediate that's not a constant, treat it as a label
759    // reference needing a fixup. If it is a constant, it's something else
760    // and we reject it.
761    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
762      return true;
763
764    if (Kind != Memory || Mem.OffsetRegNum != 0)
765      return false;
766    // Immediate offset in range [-4095, 4095].
767    if (!Mem.OffsetImm) return true;
768    int64_t Val = Mem.OffsetImm->getValue();
769    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
770  }
771  bool isPostIdxImm8() const {
772    if (Kind != Immediate)
773      return false;
774    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
775    if (!CE) return false;
776    int64_t Val = CE->getValue();
777    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
778  }
779
780  bool isMSRMask() const { return Kind == MSRMask; }
781  bool isProcIFlags() const { return Kind == ProcIFlags; }
782
783  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
784    // Add as immediates when possible.  Null MCExpr = 0.
785    if (Expr == 0)
786      Inst.addOperand(MCOperand::CreateImm(0));
787    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
788      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
789    else
790      Inst.addOperand(MCOperand::CreateExpr(Expr));
791  }
792
793  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
794    assert(N == 2 && "Invalid number of operands!");
795    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
796    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
797    Inst.addOperand(MCOperand::CreateReg(RegNum));
798  }
799
800  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
801    assert(N == 1 && "Invalid number of operands!");
802    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
803  }
804
805  void addITMaskOperands(MCInst &Inst, unsigned N) const {
806    assert(N == 1 && "Invalid number of operands!");
807    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
808  }
809
810  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
811    assert(N == 1 && "Invalid number of operands!");
812    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
813  }
814
815  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
816    assert(N == 1 && "Invalid number of operands!");
817    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
818  }
819
820  void addCCOutOperands(MCInst &Inst, unsigned N) const {
821    assert(N == 1 && "Invalid number of operands!");
822    Inst.addOperand(MCOperand::CreateReg(getReg()));
823  }
824
825  void addRegOperands(MCInst &Inst, unsigned N) const {
826    assert(N == 1 && "Invalid number of operands!");
827    Inst.addOperand(MCOperand::CreateReg(getReg()));
828  }
829
830  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
831    assert(N == 3 && "Invalid number of operands!");
832    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
833    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
834    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
835    Inst.addOperand(MCOperand::CreateImm(
836      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
837  }
838
839  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
840    assert(N == 2 && "Invalid number of operands!");
841    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
842    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
843    Inst.addOperand(MCOperand::CreateImm(
844      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
845  }
846
847
848  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
849    assert(N == 1 && "Invalid number of operands!");
850    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
851                                         ShifterImm.Imm));
852  }
853
854  void addRegListOperands(MCInst &Inst, unsigned N) const {
855    assert(N == 1 && "Invalid number of operands!");
856    const SmallVectorImpl<unsigned> &RegList = getRegList();
857    for (SmallVectorImpl<unsigned>::const_iterator
858           I = RegList.begin(), E = RegList.end(); I != E; ++I)
859      Inst.addOperand(MCOperand::CreateReg(*I));
860  }
861
862  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
863    addRegListOperands(Inst, N);
864  }
865
866  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
867    addRegListOperands(Inst, N);
868  }
869
870  void addRotImmOperands(MCInst &Inst, unsigned N) const {
871    assert(N == 1 && "Invalid number of operands!");
872    // Encoded as val>>3. The printer handles display as 8, 16, 24.
873    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
874  }
875
876  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
877    assert(N == 1 && "Invalid number of operands!");
878    // Munge the lsb/width into a bitfield mask.
879    unsigned lsb = Bitfield.LSB;
880    unsigned width = Bitfield.Width;
881    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
882    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
883                      (32 - (lsb + width)));
884    Inst.addOperand(MCOperand::CreateImm(Mask));
885  }
886
887  void addImmOperands(MCInst &Inst, unsigned N) const {
888    assert(N == 1 && "Invalid number of operands!");
889    addExpr(Inst, getImm());
890  }
891
892  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
893    assert(N == 1 && "Invalid number of operands!");
894    // The immediate is scaled by four in the encoding and is stored
895    // in the MCInst as such. Lop off the low two bits here.
896    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
897    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
898  }
899
900  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
901    assert(N == 1 && "Invalid number of operands!");
902    // The immediate is scaled by four in the encoding and is stored
903    // in the MCInst as such. Lop off the low two bits here.
904    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
905    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
906  }
907
908  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
909    assert(N == 1 && "Invalid number of operands!");
910    addExpr(Inst, getImm());
911  }
912
913  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
914    assert(N == 1 && "Invalid number of operands!");
915    addExpr(Inst, getImm());
916  }
917
918  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
919    assert(N == 1 && "Invalid number of operands!");
920    addExpr(Inst, getImm());
921  }
922
923  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
924    assert(N == 1 && "Invalid number of operands!");
925    addExpr(Inst, getImm());
926  }
927
928  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
929    assert(N == 1 && "Invalid number of operands!");
930    // The constant encodes as the immediate-1, and we store in the instruction
931    // the bits as encoded, so subtract off one here.
932    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
933    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
934  }
935
936  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
937    assert(N == 1 && "Invalid number of operands!");
938    // The constant encodes as the immediate-1, and we store in the instruction
939    // the bits as encoded, so subtract off one here.
940    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
942  }
943
944  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
945    assert(N == 1 && "Invalid number of operands!");
946    addExpr(Inst, getImm());
947  }
948
949  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
950    assert(N == 1 && "Invalid number of operands!");
951    addExpr(Inst, getImm());
952  }
953
954  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
955    assert(N == 1 && "Invalid number of operands!");
956    addExpr(Inst, getImm());
957  }
958
959  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
960    assert(N == 1 && "Invalid number of operands!");
961    // The constant encodes as the immediate, except for 32, which encodes as
962    // zero.
963    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964    unsigned Imm = CE->getValue();
965    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
966  }
967
968  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
969    assert(N == 1 && "Invalid number of operands!");
970    addExpr(Inst, getImm());
971  }
972
973  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
974    assert(N == 1 && "Invalid number of operands!");
975    // An ASR value of 32 encodes as 0, so that's how we want to add it to
976    // the instruction as well.
977    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
978    int Val = CE->getValue();
979    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
980  }
981
982  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
983    assert(N == 1 && "Invalid number of operands!");
984    addExpr(Inst, getImm());
985  }
986
987  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
988    assert(N == 1 && "Invalid number of operands!");
989    addExpr(Inst, getImm());
990  }
991
992  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
993    assert(N == 1 && "Invalid number of operands!");
994    addExpr(Inst, getImm());
995  }
996
997  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
998    assert(N == 1 && "Invalid number of operands!");
999    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1000  }
1001
1002  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1003    assert(N == 1 && "Invalid number of operands!");
1004    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1005  }
1006
1007  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1008    assert(N == 3 && "Invalid number of operands!");
1009    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1010    if (!Mem.OffsetRegNum) {
1011      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1012      // Special case for #-0
1013      if (Val == INT32_MIN) Val = 0;
1014      if (Val < 0) Val = -Val;
1015      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1016    } else {
1017      // For register offset, we encode the shift type and negation flag
1018      // here.
1019      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1020                              Mem.ShiftImm, Mem.ShiftType);
1021    }
1022    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1023    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1024    Inst.addOperand(MCOperand::CreateImm(Val));
1025  }
1026
1027  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1028    assert(N == 2 && "Invalid number of operands!");
1029    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1030    assert(CE && "non-constant AM2OffsetImm operand!");
1031    int32_t Val = CE->getValue();
1032    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1033    // Special case for #-0
1034    if (Val == INT32_MIN) Val = 0;
1035    if (Val < 0) Val = -Val;
1036    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1037    Inst.addOperand(MCOperand::CreateReg(0));
1038    Inst.addOperand(MCOperand::CreateImm(Val));
1039  }
1040
1041  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1042    assert(N == 3 && "Invalid number of operands!");
1043    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1044    if (!Mem.OffsetRegNum) {
1045      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1046      // Special case for #-0
1047      if (Val == INT32_MIN) Val = 0;
1048      if (Val < 0) Val = -Val;
1049      Val = ARM_AM::getAM3Opc(AddSub, Val);
1050    } else {
1051      // For register offset, we encode the shift type and negation flag
1052      // here.
1053      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1054    }
1055    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1056    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1057    Inst.addOperand(MCOperand::CreateImm(Val));
1058  }
1059
1060  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1061    assert(N == 2 && "Invalid number of operands!");
1062    if (Kind == PostIndexRegister) {
1063      int32_t Val =
1064        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1065      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1066      Inst.addOperand(MCOperand::CreateImm(Val));
1067      return;
1068    }
1069
1070    // Constant offset.
1071    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1072    int32_t Val = CE->getValue();
1073    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1074    // Special case for #-0
1075    if (Val == INT32_MIN) Val = 0;
1076    if (Val < 0) Val = -Val;
1077    Val = ARM_AM::getAM3Opc(AddSub, Val);
1078    Inst.addOperand(MCOperand::CreateReg(0));
1079    Inst.addOperand(MCOperand::CreateImm(Val));
1080  }
1081
1082  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1083    assert(N == 2 && "Invalid number of operands!");
1084    // The lower two bits are always zero and as such are not encoded.
1085    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1086    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1087    // Special case for #-0
1088    if (Val == INT32_MIN) Val = 0;
1089    if (Val < 0) Val = -Val;
1090    Val = ARM_AM::getAM5Opc(AddSub, Val);
1091    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1092    Inst.addOperand(MCOperand::CreateImm(Val));
1093  }
1094
1095  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1096    assert(N == 2 && "Invalid number of operands!");
1097    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1098    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1099    Inst.addOperand(MCOperand::CreateImm(Val));
1100  }
1101
1102  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1103    assert(N == 2 && "Invalid number of operands!");
1104    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1105    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1106    Inst.addOperand(MCOperand::CreateImm(Val));
1107  }
1108
1109  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1110    assert(N == 2 && "Invalid number of operands!");
1111    // If this is an immediate, it's a label reference.
1112    if (Kind == Immediate) {
1113      addExpr(Inst, getImm());
1114      Inst.addOperand(MCOperand::CreateImm(0));
1115      return;
1116    }
1117
1118    // Otherwise, it's a normal memory reg+offset.
1119    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1120    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1121    Inst.addOperand(MCOperand::CreateImm(Val));
1122  }
1123
1124  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1125    assert(N == 2 && "Invalid number of operands!");
1126    // If this is an immediate, it's a label reference.
1127    if (Kind == Immediate) {
1128      addExpr(Inst, getImm());
1129      Inst.addOperand(MCOperand::CreateImm(0));
1130      return;
1131    }
1132
1133    // Otherwise, it's a normal memory reg+offset.
1134    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1135    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1136    Inst.addOperand(MCOperand::CreateImm(Val));
1137  }
1138
1139  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1140    assert(N == 3 && "Invalid number of operands!");
1141    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1142                                     Mem.ShiftImm, Mem.ShiftType);
1143    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1144    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1145    Inst.addOperand(MCOperand::CreateImm(Val));
1146  }
1147
1148  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1149    assert(N == 2 && "Invalid number of operands!");
1150    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1151    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1152  }
1153
1154  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1155    assert(N == 2 && "Invalid number of operands!");
1156    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1157    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1158    Inst.addOperand(MCOperand::CreateImm(Val));
1159  }
1160
1161  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1162    assert(N == 2 && "Invalid number of operands!");
1163    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1164    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1165    Inst.addOperand(MCOperand::CreateImm(Val));
1166  }
1167
1168  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1169    assert(N == 2 && "Invalid number of operands!");
1170    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1171    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1172    Inst.addOperand(MCOperand::CreateImm(Val));
1173  }
1174
1175  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1176    assert(N == 2 && "Invalid number of operands!");
1177    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1178    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1179    Inst.addOperand(MCOperand::CreateImm(Val));
1180  }
1181
1182  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1183    assert(N == 1 && "Invalid number of operands!");
1184    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1185    assert(CE && "non-constant post-idx-imm8 operand!");
1186    int Imm = CE->getValue();
1187    bool isAdd = Imm >= 0;
1188    if (Imm == INT32_MIN) Imm = 0;
1189    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1190    Inst.addOperand(MCOperand::CreateImm(Imm));
1191  }
1192
1193  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1194    assert(N == 2 && "Invalid number of operands!");
1195    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1196    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1197  }
1198
1199  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1200    assert(N == 2 && "Invalid number of operands!");
1201    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1202    // The sign, shift type, and shift amount are encoded in a single operand
1203    // using the AM2 encoding helpers.
1204    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1205    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1206                                     PostIdxReg.ShiftTy);
1207    Inst.addOperand(MCOperand::CreateImm(Imm));
1208  }
1209
1210  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1211    assert(N == 1 && "Invalid number of operands!");
1212    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1213  }
1214
1215  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1216    assert(N == 1 && "Invalid number of operands!");
1217    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1218  }
1219
1220  virtual void print(raw_ostream &OS) const;
1221
1222  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1223    ARMOperand *Op = new ARMOperand(ITCondMask);
1224    Op->ITMask.Mask = Mask;
1225    Op->StartLoc = S;
1226    Op->EndLoc = S;
1227    return Op;
1228  }
1229
1230  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1231    ARMOperand *Op = new ARMOperand(CondCode);
1232    Op->CC.Val = CC;
1233    Op->StartLoc = S;
1234    Op->EndLoc = S;
1235    return Op;
1236  }
1237
1238  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1239    ARMOperand *Op = new ARMOperand(CoprocNum);
1240    Op->Cop.Val = CopVal;
1241    Op->StartLoc = S;
1242    Op->EndLoc = S;
1243    return Op;
1244  }
1245
1246  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1247    ARMOperand *Op = new ARMOperand(CoprocReg);
1248    Op->Cop.Val = CopVal;
1249    Op->StartLoc = S;
1250    Op->EndLoc = S;
1251    return Op;
1252  }
1253
1254  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1255    ARMOperand *Op = new ARMOperand(CCOut);
1256    Op->Reg.RegNum = RegNum;
1257    Op->StartLoc = S;
1258    Op->EndLoc = S;
1259    return Op;
1260  }
1261
1262  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1263    ARMOperand *Op = new ARMOperand(Token);
1264    Op->Tok.Data = Str.data();
1265    Op->Tok.Length = Str.size();
1266    Op->StartLoc = S;
1267    Op->EndLoc = S;
1268    return Op;
1269  }
1270
1271  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1272    ARMOperand *Op = new ARMOperand(Register);
1273    Op->Reg.RegNum = RegNum;
1274    Op->StartLoc = S;
1275    Op->EndLoc = E;
1276    return Op;
1277  }
1278
1279  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1280                                           unsigned SrcReg,
1281                                           unsigned ShiftReg,
1282                                           unsigned ShiftImm,
1283                                           SMLoc S, SMLoc E) {
1284    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1285    Op->RegShiftedReg.ShiftTy = ShTy;
1286    Op->RegShiftedReg.SrcReg = SrcReg;
1287    Op->RegShiftedReg.ShiftReg = ShiftReg;
1288    Op->RegShiftedReg.ShiftImm = ShiftImm;
1289    Op->StartLoc = S;
1290    Op->EndLoc = E;
1291    return Op;
1292  }
1293
1294  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1295                                            unsigned SrcReg,
1296                                            unsigned ShiftImm,
1297                                            SMLoc S, SMLoc E) {
1298    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1299    Op->RegShiftedImm.ShiftTy = ShTy;
1300    Op->RegShiftedImm.SrcReg = SrcReg;
1301    Op->RegShiftedImm.ShiftImm = ShiftImm;
1302    Op->StartLoc = S;
1303    Op->EndLoc = E;
1304    return Op;
1305  }
1306
1307  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1308                                   SMLoc S, SMLoc E) {
1309    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1310    Op->ShifterImm.isASR = isASR;
1311    Op->ShifterImm.Imm = Imm;
1312    Op->StartLoc = S;
1313    Op->EndLoc = E;
1314    return Op;
1315  }
1316
1317  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1318    ARMOperand *Op = new ARMOperand(RotateImmediate);
1319    Op->RotImm.Imm = Imm;
1320    Op->StartLoc = S;
1321    Op->EndLoc = E;
1322    return Op;
1323  }
1324
1325  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1326                                    SMLoc S, SMLoc E) {
1327    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1328    Op->Bitfield.LSB = LSB;
1329    Op->Bitfield.Width = Width;
1330    Op->StartLoc = S;
1331    Op->EndLoc = E;
1332    return Op;
1333  }
1334
1335  static ARMOperand *
1336  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1337                SMLoc StartLoc, SMLoc EndLoc) {
1338    KindTy Kind = RegisterList;
1339
1340    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1341        contains(Regs.front().first))
1342      Kind = DPRRegisterList;
1343    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1344             contains(Regs.front().first))
1345      Kind = SPRRegisterList;
1346
1347    ARMOperand *Op = new ARMOperand(Kind);
1348    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1349           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1350      Op->Registers.push_back(I->first);
1351    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1352    Op->StartLoc = StartLoc;
1353    Op->EndLoc = EndLoc;
1354    return Op;
1355  }
1356
1357  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1358    ARMOperand *Op = new ARMOperand(Immediate);
1359    Op->Imm.Val = Val;
1360    Op->StartLoc = S;
1361    Op->EndLoc = E;
1362    return Op;
1363  }
1364
1365  static ARMOperand *CreateMem(unsigned BaseRegNum,
1366                               const MCConstantExpr *OffsetImm,
1367                               unsigned OffsetRegNum,
1368                               ARM_AM::ShiftOpc ShiftType,
1369                               unsigned ShiftImm,
1370                               bool isNegative,
1371                               SMLoc S, SMLoc E) {
1372    ARMOperand *Op = new ARMOperand(Memory);
1373    Op->Mem.BaseRegNum = BaseRegNum;
1374    Op->Mem.OffsetImm = OffsetImm;
1375    Op->Mem.OffsetRegNum = OffsetRegNum;
1376    Op->Mem.ShiftType = ShiftType;
1377    Op->Mem.ShiftImm = ShiftImm;
1378    Op->Mem.isNegative = isNegative;
1379    Op->StartLoc = S;
1380    Op->EndLoc = E;
1381    return Op;
1382  }
1383
1384  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1385                                      ARM_AM::ShiftOpc ShiftTy,
1386                                      unsigned ShiftImm,
1387                                      SMLoc S, SMLoc E) {
1388    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1389    Op->PostIdxReg.RegNum = RegNum;
1390    Op->PostIdxReg.isAdd = isAdd;
1391    Op->PostIdxReg.ShiftTy = ShiftTy;
1392    Op->PostIdxReg.ShiftImm = ShiftImm;
1393    Op->StartLoc = S;
1394    Op->EndLoc = E;
1395    return Op;
1396  }
1397
1398  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1399    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1400    Op->MBOpt.Val = Opt;
1401    Op->StartLoc = S;
1402    Op->EndLoc = S;
1403    return Op;
1404  }
1405
1406  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1407    ARMOperand *Op = new ARMOperand(ProcIFlags);
1408    Op->IFlags.Val = IFlags;
1409    Op->StartLoc = S;
1410    Op->EndLoc = S;
1411    return Op;
1412  }
1413
1414  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1415    ARMOperand *Op = new ARMOperand(MSRMask);
1416    Op->MMask.Val = MMask;
1417    Op->StartLoc = S;
1418    Op->EndLoc = S;
1419    return Op;
1420  }
1421};
1422
1423} // end anonymous namespace.
1424
1425void ARMOperand::print(raw_ostream &OS) const {
1426  switch (Kind) {
1427  case CondCode:
1428    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1429    break;
1430  case CCOut:
1431    OS << "<ccout " << getReg() << ">";
1432    break;
1433  case ITCondMask: {
1434    static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1435      "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1436      "(tee)", "(eee)" };
1437    assert((ITMask.Mask & 0xf) == ITMask.Mask);
1438    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1439    break;
1440  }
1441  case CoprocNum:
1442    OS << "<coprocessor number: " << getCoproc() << ">";
1443    break;
1444  case CoprocReg:
1445    OS << "<coprocessor register: " << getCoproc() << ">";
1446    break;
1447  case MSRMask:
1448    OS << "<mask: " << getMSRMask() << ">";
1449    break;
1450  case Immediate:
1451    getImm()->print(OS);
1452    break;
1453  case MemBarrierOpt:
1454    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1455    break;
1456  case Memory:
1457    OS << "<memory "
1458       << " base:" << Mem.BaseRegNum;
1459    OS << ">";
1460    break;
1461  case PostIndexRegister:
1462    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1463       << PostIdxReg.RegNum;
1464    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1465      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1466         << PostIdxReg.ShiftImm;
1467    OS << ">";
1468    break;
1469  case ProcIFlags: {
1470    OS << "<ARM_PROC::";
1471    unsigned IFlags = getProcIFlags();
1472    for (int i=2; i >= 0; --i)
1473      if (IFlags & (1 << i))
1474        OS << ARM_PROC::IFlagsToString(1 << i);
1475    OS << ">";
1476    break;
1477  }
1478  case Register:
1479    OS << "<register " << getReg() << ">";
1480    break;
1481  case ShifterImmediate:
1482    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1483       << " #" << ShifterImm.Imm << ">";
1484    break;
1485  case ShiftedRegister:
1486    OS << "<so_reg_reg "
1487       << RegShiftedReg.SrcReg
1488       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1489       << ", " << RegShiftedReg.ShiftReg << ", "
1490       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1491       << ">";
1492    break;
1493  case ShiftedImmediate:
1494    OS << "<so_reg_imm "
1495       << RegShiftedImm.SrcReg
1496       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1497       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1498       << ">";
1499    break;
1500  case RotateImmediate:
1501    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1502    break;
1503  case BitfieldDescriptor:
1504    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1505       << ", width: " << Bitfield.Width << ">";
1506    break;
1507  case RegisterList:
1508  case DPRRegisterList:
1509  case SPRRegisterList: {
1510    OS << "<register_list ";
1511
1512    const SmallVectorImpl<unsigned> &RegList = getRegList();
1513    for (SmallVectorImpl<unsigned>::const_iterator
1514           I = RegList.begin(), E = RegList.end(); I != E; ) {
1515      OS << *I;
1516      if (++I < E) OS << ", ";
1517    }
1518
1519    OS << ">";
1520    break;
1521  }
1522  case Token:
1523    OS << "'" << getToken() << "'";
1524    break;
1525  }
1526}
1527
1528/// @name Auto-generated Match Functions
1529/// {
1530
1531static unsigned MatchRegisterName(StringRef Name);
1532
1533/// }
1534
1535bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1536                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1537  RegNo = tryParseRegister();
1538
1539  return (RegNo == (unsigned)-1);
1540}
1541
1542/// Try to parse a register name.  The token must be an Identifier when called,
1543/// and if it is a register name the token is eaten and the register number is
1544/// returned.  Otherwise return -1.
1545///
1546int ARMAsmParser::tryParseRegister() {
1547  const AsmToken &Tok = Parser.getTok();
1548  if (Tok.isNot(AsmToken::Identifier)) return -1;
1549
1550  // FIXME: Validate register for the current architecture; we have to do
1551  // validation later, so maybe there is no need for this here.
1552  std::string upperCase = Tok.getString().str();
1553  std::string lowerCase = LowercaseString(upperCase);
1554  unsigned RegNum = MatchRegisterName(lowerCase);
1555  if (!RegNum) {
1556    RegNum = StringSwitch<unsigned>(lowerCase)
1557      .Case("r13", ARM::SP)
1558      .Case("r14", ARM::LR)
1559      .Case("r15", ARM::PC)
1560      .Case("ip", ARM::R12)
1561      .Default(0);
1562  }
1563  if (!RegNum) return -1;
1564
1565  Parser.Lex(); // Eat identifier token.
1566  return RegNum;
1567}
1568
1569// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1570// If a recoverable error occurs, return 1. If an irrecoverable error
1571// occurs, return -1. An irrecoverable error is one where tokens have been
1572// consumed in the process of trying to parse the shifter (i.e., when it is
1573// indeed a shifter operand, but malformed).
1574int ARMAsmParser::tryParseShiftRegister(
1575                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1576  SMLoc S = Parser.getTok().getLoc();
1577  const AsmToken &Tok = Parser.getTok();
1578  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1579
1580  std::string upperCase = Tok.getString().str();
1581  std::string lowerCase = LowercaseString(upperCase);
1582  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1583      .Case("lsl", ARM_AM::lsl)
1584      .Case("lsr", ARM_AM::lsr)
1585      .Case("asr", ARM_AM::asr)
1586      .Case("ror", ARM_AM::ror)
1587      .Case("rrx", ARM_AM::rrx)
1588      .Default(ARM_AM::no_shift);
1589
1590  if (ShiftTy == ARM_AM::no_shift)
1591    return 1;
1592
1593  Parser.Lex(); // Eat the operator.
1594
1595  // The source register for the shift has already been added to the
1596  // operand list, so we need to pop it off and combine it into the shifted
1597  // register operand instead.
1598  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1599  if (!PrevOp->isReg())
1600    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1601  int SrcReg = PrevOp->getReg();
1602  int64_t Imm = 0;
1603  int ShiftReg = 0;
1604  if (ShiftTy == ARM_AM::rrx) {
1605    // RRX Doesn't have an explicit shift amount. The encoder expects
1606    // the shift register to be the same as the source register. Seems odd,
1607    // but OK.
1608    ShiftReg = SrcReg;
1609  } else {
1610    // Figure out if this is shifted by a constant or a register (for non-RRX).
1611    if (Parser.getTok().is(AsmToken::Hash)) {
1612      Parser.Lex(); // Eat hash.
1613      SMLoc ImmLoc = Parser.getTok().getLoc();
1614      const MCExpr *ShiftExpr = 0;
1615      if (getParser().ParseExpression(ShiftExpr)) {
1616        Error(ImmLoc, "invalid immediate shift value");
1617        return -1;
1618      }
1619      // The expression must be evaluatable as an immediate.
1620      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1621      if (!CE) {
1622        Error(ImmLoc, "invalid immediate shift value");
1623        return -1;
1624      }
1625      // Range check the immediate.
1626      // lsl, ror: 0 <= imm <= 31
1627      // lsr, asr: 0 <= imm <= 32
1628      Imm = CE->getValue();
1629      if (Imm < 0 ||
1630          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1631          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1632        Error(ImmLoc, "immediate shift value out of range");
1633        return -1;
1634      }
1635    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1636      ShiftReg = tryParseRegister();
1637      SMLoc L = Parser.getTok().getLoc();
1638      if (ShiftReg == -1) {
1639        Error (L, "expected immediate or register in shift operand");
1640        return -1;
1641      }
1642    } else {
1643      Error (Parser.getTok().getLoc(),
1644                    "expected immediate or register in shift operand");
1645      return -1;
1646    }
1647  }
1648
1649  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1650    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1651                                                         ShiftReg, Imm,
1652                                               S, Parser.getTok().getLoc()));
1653  else
1654    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1655                                               S, Parser.getTok().getLoc()));
1656
1657  return 0;
1658}
1659
1660
1661/// Try to parse a register name.  The token must be an Identifier when called.
1662/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1663/// if there is a "writeback". 'true' if it's not a register.
1664///
1665/// TODO this is likely to change to allow different register types and or to
1666/// parse for a specific register type.
1667bool ARMAsmParser::
1668tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1669  SMLoc S = Parser.getTok().getLoc();
1670  int RegNo = tryParseRegister();
1671  if (RegNo == -1)
1672    return true;
1673
1674  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1675
1676  const AsmToken &ExclaimTok = Parser.getTok();
1677  if (ExclaimTok.is(AsmToken::Exclaim)) {
1678    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1679                                               ExclaimTok.getLoc()));
1680    Parser.Lex(); // Eat exclaim token
1681  }
1682
1683  return false;
1684}
1685
1686/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1687/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1688/// "c5", ...
1689static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1690  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1691  // but efficient.
1692  switch (Name.size()) {
1693  default: break;
1694  case 2:
1695    if (Name[0] != CoprocOp)
1696      return -1;
1697    switch (Name[1]) {
1698    default:  return -1;
1699    case '0': return 0;
1700    case '1': return 1;
1701    case '2': return 2;
1702    case '3': return 3;
1703    case '4': return 4;
1704    case '5': return 5;
1705    case '6': return 6;
1706    case '7': return 7;
1707    case '8': return 8;
1708    case '9': return 9;
1709    }
1710    break;
1711  case 3:
1712    if (Name[0] != CoprocOp || Name[1] != '1')
1713      return -1;
1714    switch (Name[2]) {
1715    default:  return -1;
1716    case '0': return 10;
1717    case '1': return 11;
1718    case '2': return 12;
1719    case '3': return 13;
1720    case '4': return 14;
1721    case '5': return 15;
1722    }
1723    break;
1724  }
1725
1726  return -1;
1727}
1728
1729/// parseITCondCode - Try to parse a condition code for an IT instruction.
1730ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1731parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1732  SMLoc S = Parser.getTok().getLoc();
1733  const AsmToken &Tok = Parser.getTok();
1734  if (!Tok.is(AsmToken::Identifier))
1735    return MatchOperand_NoMatch;
1736  unsigned CC = StringSwitch<unsigned>(Tok.getString())
1737    .Case("eq", ARMCC::EQ)
1738    .Case("ne", ARMCC::NE)
1739    .Case("hs", ARMCC::HS)
1740    .Case("cs", ARMCC::HS)
1741    .Case("lo", ARMCC::LO)
1742    .Case("cc", ARMCC::LO)
1743    .Case("mi", ARMCC::MI)
1744    .Case("pl", ARMCC::PL)
1745    .Case("vs", ARMCC::VS)
1746    .Case("vc", ARMCC::VC)
1747    .Case("hi", ARMCC::HI)
1748    .Case("ls", ARMCC::LS)
1749    .Case("ge", ARMCC::GE)
1750    .Case("lt", ARMCC::LT)
1751    .Case("gt", ARMCC::GT)
1752    .Case("le", ARMCC::LE)
1753    .Case("al", ARMCC::AL)
1754    .Default(~0U);
1755  if (CC == ~0U)
1756    return MatchOperand_NoMatch;
1757  Parser.Lex(); // Eat the token.
1758
1759  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1760
1761  return MatchOperand_Success;
1762}
1763
1764/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1765/// token must be an Identifier when called, and if it is a coprocessor
1766/// number, the token is eaten and the operand is added to the operand list.
1767ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1768parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1769  SMLoc S = Parser.getTok().getLoc();
1770  const AsmToken &Tok = Parser.getTok();
1771  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1772
1773  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1774  if (Num == -1)
1775    return MatchOperand_NoMatch;
1776
1777  Parser.Lex(); // Eat identifier token.
1778  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1779  return MatchOperand_Success;
1780}
1781
1782/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1783/// token must be an Identifier when called, and if it is a coprocessor
1784/// number, the token is eaten and the operand is added to the operand list.
1785ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1786parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1787  SMLoc S = Parser.getTok().getLoc();
1788  const AsmToken &Tok = Parser.getTok();
1789  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1790
1791  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1792  if (Reg == -1)
1793    return MatchOperand_NoMatch;
1794
1795  Parser.Lex(); // Eat identifier token.
1796  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1797  return MatchOperand_Success;
1798}
1799
1800/// Parse a register list, return it if successful else return null.  The first
1801/// token must be a '{' when called.
1802bool ARMAsmParser::
1803parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1804  assert(Parser.getTok().is(AsmToken::LCurly) &&
1805         "Token is not a Left Curly Brace");
1806  SMLoc S = Parser.getTok().getLoc();
1807
1808  // Read the rest of the registers in the list.
1809  unsigned PrevRegNum = 0;
1810  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1811
1812  do {
1813    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1814    Parser.Lex(); // Eat non-identifier token.
1815
1816    const AsmToken &RegTok = Parser.getTok();
1817    SMLoc RegLoc = RegTok.getLoc();
1818    if (RegTok.isNot(AsmToken::Identifier)) {
1819      Error(RegLoc, "register expected");
1820      return true;
1821    }
1822
1823    int RegNum = tryParseRegister();
1824    if (RegNum == -1) {
1825      Error(RegLoc, "register expected");
1826      return true;
1827    }
1828
1829    if (IsRange) {
1830      int Reg = PrevRegNum;
1831      do {
1832        ++Reg;
1833        Registers.push_back(std::make_pair(Reg, RegLoc));
1834      } while (Reg != RegNum);
1835    } else {
1836      Registers.push_back(std::make_pair(RegNum, RegLoc));
1837    }
1838
1839    PrevRegNum = RegNum;
1840  } while (Parser.getTok().is(AsmToken::Comma) ||
1841           Parser.getTok().is(AsmToken::Minus));
1842
1843  // Process the right curly brace of the list.
1844  const AsmToken &RCurlyTok = Parser.getTok();
1845  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1846    Error(RCurlyTok.getLoc(), "'}' expected");
1847    return true;
1848  }
1849
1850  SMLoc E = RCurlyTok.getLoc();
1851  Parser.Lex(); // Eat right curly brace token.
1852
1853  // Verify the register list.
1854  bool EmittedWarning = false;
1855  unsigned HighRegNum = 0;
1856  BitVector RegMap(32);
1857  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1858    const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1859    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1860
1861    if (RegMap[Reg]) {
1862      Error(RegInfo.second, "register duplicated in register list");
1863      return true;
1864    }
1865
1866    if (!EmittedWarning && Reg < HighRegNum)
1867      Warning(RegInfo.second,
1868              "register not in ascending order in register list");
1869
1870    RegMap.set(Reg);
1871    HighRegNum = std::max(Reg, HighRegNum);
1872  }
1873
1874  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1875  return false;
1876}
1877
1878/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1879ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1880parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1881  SMLoc S = Parser.getTok().getLoc();
1882  const AsmToken &Tok = Parser.getTok();
1883  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1884  StringRef OptStr = Tok.getString();
1885
1886  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1887    .Case("sy",    ARM_MB::SY)
1888    .Case("st",    ARM_MB::ST)
1889    .Case("sh",    ARM_MB::ISH)
1890    .Case("ish",   ARM_MB::ISH)
1891    .Case("shst",  ARM_MB::ISHST)
1892    .Case("ishst", ARM_MB::ISHST)
1893    .Case("nsh",   ARM_MB::NSH)
1894    .Case("un",    ARM_MB::NSH)
1895    .Case("nshst", ARM_MB::NSHST)
1896    .Case("unst",  ARM_MB::NSHST)
1897    .Case("osh",   ARM_MB::OSH)
1898    .Case("oshst", ARM_MB::OSHST)
1899    .Default(~0U);
1900
1901  if (Opt == ~0U)
1902    return MatchOperand_NoMatch;
1903
1904  Parser.Lex(); // Eat identifier token.
1905  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1906  return MatchOperand_Success;
1907}
1908
1909/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1910ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1911parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1912  SMLoc S = Parser.getTok().getLoc();
1913  const AsmToken &Tok = Parser.getTok();
1914  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1915  StringRef IFlagsStr = Tok.getString();
1916
1917  unsigned IFlags = 0;
1918  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1919    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1920    .Case("a", ARM_PROC::A)
1921    .Case("i", ARM_PROC::I)
1922    .Case("f", ARM_PROC::F)
1923    .Default(~0U);
1924
1925    // If some specific iflag is already set, it means that some letter is
1926    // present more than once, this is not acceptable.
1927    if (Flag == ~0U || (IFlags & Flag))
1928      return MatchOperand_NoMatch;
1929
1930    IFlags |= Flag;
1931  }
1932
1933  Parser.Lex(); // Eat identifier token.
1934  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1935  return MatchOperand_Success;
1936}
1937
1938/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1939ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1940parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1941  SMLoc S = Parser.getTok().getLoc();
1942  const AsmToken &Tok = Parser.getTok();
1943  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1944  StringRef Mask = Tok.getString();
1945
1946  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1947  size_t Start = 0, Next = Mask.find('_');
1948  StringRef Flags = "";
1949  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1950  if (Next != StringRef::npos)
1951    Flags = Mask.slice(Next+1, Mask.size());
1952
1953  // FlagsVal contains the complete mask:
1954  // 3-0: Mask
1955  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1956  unsigned FlagsVal = 0;
1957
1958  if (SpecReg == "apsr") {
1959    FlagsVal = StringSwitch<unsigned>(Flags)
1960    .Case("nzcvq",  0x8) // same as CPSR_f
1961    .Case("g",      0x4) // same as CPSR_s
1962    .Case("nzcvqg", 0xc) // same as CPSR_fs
1963    .Default(~0U);
1964
1965    if (FlagsVal == ~0U) {
1966      if (!Flags.empty())
1967        return MatchOperand_NoMatch;
1968      else
1969        FlagsVal = 0; // No flag
1970    }
1971  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1972    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1973      Flags = "fc";
1974    for (int i = 0, e = Flags.size(); i != e; ++i) {
1975      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1976      .Case("c", 1)
1977      .Case("x", 2)
1978      .Case("s", 4)
1979      .Case("f", 8)
1980      .Default(~0U);
1981
1982      // If some specific flag is already set, it means that some letter is
1983      // present more than once, this is not acceptable.
1984      if (FlagsVal == ~0U || (FlagsVal & Flag))
1985        return MatchOperand_NoMatch;
1986      FlagsVal |= Flag;
1987    }
1988  } else // No match for special register.
1989    return MatchOperand_NoMatch;
1990
1991  // Special register without flags are equivalent to "fc" flags.
1992  if (!FlagsVal)
1993    FlagsVal = 0x9;
1994
1995  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1996  if (SpecReg == "spsr")
1997    FlagsVal |= 16;
1998
1999  Parser.Lex(); // Eat identifier token.
2000  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2001  return MatchOperand_Success;
2002}
2003
2004ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2005parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2006            int Low, int High) {
2007  const AsmToken &Tok = Parser.getTok();
2008  if (Tok.isNot(AsmToken::Identifier)) {
2009    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2010    return MatchOperand_ParseFail;
2011  }
2012  StringRef ShiftName = Tok.getString();
2013  std::string LowerOp = LowercaseString(Op);
2014  std::string UpperOp = UppercaseString(Op);
2015  if (ShiftName != LowerOp && ShiftName != UpperOp) {
2016    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2017    return MatchOperand_ParseFail;
2018  }
2019  Parser.Lex(); // Eat shift type token.
2020
2021  // There must be a '#' and a shift amount.
2022  if (Parser.getTok().isNot(AsmToken::Hash)) {
2023    Error(Parser.getTok().getLoc(), "'#' expected");
2024    return MatchOperand_ParseFail;
2025  }
2026  Parser.Lex(); // Eat hash token.
2027
2028  const MCExpr *ShiftAmount;
2029  SMLoc Loc = Parser.getTok().getLoc();
2030  if (getParser().ParseExpression(ShiftAmount)) {
2031    Error(Loc, "illegal expression");
2032    return MatchOperand_ParseFail;
2033  }
2034  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2035  if (!CE) {
2036    Error(Loc, "constant expression expected");
2037    return MatchOperand_ParseFail;
2038  }
2039  int Val = CE->getValue();
2040  if (Val < Low || Val > High) {
2041    Error(Loc, "immediate value out of range");
2042    return MatchOperand_ParseFail;
2043  }
2044
2045  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2046
2047  return MatchOperand_Success;
2048}
2049
2050ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2051parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2052  const AsmToken &Tok = Parser.getTok();
2053  SMLoc S = Tok.getLoc();
2054  if (Tok.isNot(AsmToken::Identifier)) {
2055    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2056    return MatchOperand_ParseFail;
2057  }
2058  int Val = StringSwitch<int>(Tok.getString())
2059    .Case("be", 1)
2060    .Case("le", 0)
2061    .Default(-1);
2062  Parser.Lex(); // Eat the token.
2063
2064  if (Val == -1) {
2065    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2066    return MatchOperand_ParseFail;
2067  }
2068  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2069                                                                  getContext()),
2070                                           S, Parser.getTok().getLoc()));
2071  return MatchOperand_Success;
2072}
2073
2074/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2075/// instructions. Legal values are:
2076///     lsl #n  'n' in [0,31]
2077///     asr #n  'n' in [1,32]
2078///             n == 32 encoded as n == 0.
2079ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2080parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2081  const AsmToken &Tok = Parser.getTok();
2082  SMLoc S = Tok.getLoc();
2083  if (Tok.isNot(AsmToken::Identifier)) {
2084    Error(S, "shift operator 'asr' or 'lsl' expected");
2085    return MatchOperand_ParseFail;
2086  }
2087  StringRef ShiftName = Tok.getString();
2088  bool isASR;
2089  if (ShiftName == "lsl" || ShiftName == "LSL")
2090    isASR = false;
2091  else if (ShiftName == "asr" || ShiftName == "ASR")
2092    isASR = true;
2093  else {
2094    Error(S, "shift operator 'asr' or 'lsl' expected");
2095    return MatchOperand_ParseFail;
2096  }
2097  Parser.Lex(); // Eat the operator.
2098
2099  // A '#' and a shift amount.
2100  if (Parser.getTok().isNot(AsmToken::Hash)) {
2101    Error(Parser.getTok().getLoc(), "'#' expected");
2102    return MatchOperand_ParseFail;
2103  }
2104  Parser.Lex(); // Eat hash token.
2105
2106  const MCExpr *ShiftAmount;
2107  SMLoc E = Parser.getTok().getLoc();
2108  if (getParser().ParseExpression(ShiftAmount)) {
2109    Error(E, "malformed shift expression");
2110    return MatchOperand_ParseFail;
2111  }
2112  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2113  if (!CE) {
2114    Error(E, "shift amount must be an immediate");
2115    return MatchOperand_ParseFail;
2116  }
2117
2118  int64_t Val = CE->getValue();
2119  if (isASR) {
2120    // Shift amount must be in [1,32]
2121    if (Val < 1 || Val > 32) {
2122      Error(E, "'asr' shift amount must be in range [1,32]");
2123      return MatchOperand_ParseFail;
2124    }
2125    // asr #32 encoded as asr #0.
2126    if (Val == 32) Val = 0;
2127  } else {
2128    // Shift amount must be in [1,32]
2129    if (Val < 0 || Val > 31) {
2130      Error(E, "'lsr' shift amount must be in range [0,31]");
2131      return MatchOperand_ParseFail;
2132    }
2133  }
2134
2135  E = Parser.getTok().getLoc();
2136  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2137
2138  return MatchOperand_Success;
2139}
2140
2141/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2142/// of instructions. Legal values are:
2143///     ror #n  'n' in {0, 8, 16, 24}
2144ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2145parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2146  const AsmToken &Tok = Parser.getTok();
2147  SMLoc S = Tok.getLoc();
2148  if (Tok.isNot(AsmToken::Identifier)) {
2149    Error(S, "rotate operator 'ror' expected");
2150    return MatchOperand_ParseFail;
2151  }
2152  StringRef ShiftName = Tok.getString();
2153  if (ShiftName != "ror" && ShiftName != "ROR") {
2154    Error(S, "rotate operator 'ror' expected");
2155    return MatchOperand_ParseFail;
2156  }
2157  Parser.Lex(); // Eat the operator.
2158
2159  // A '#' and a rotate amount.
2160  if (Parser.getTok().isNot(AsmToken::Hash)) {
2161    Error(Parser.getTok().getLoc(), "'#' expected");
2162    return MatchOperand_ParseFail;
2163  }
2164  Parser.Lex(); // Eat hash token.
2165
2166  const MCExpr *ShiftAmount;
2167  SMLoc E = Parser.getTok().getLoc();
2168  if (getParser().ParseExpression(ShiftAmount)) {
2169    Error(E, "malformed rotate expression");
2170    return MatchOperand_ParseFail;
2171  }
2172  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2173  if (!CE) {
2174    Error(E, "rotate amount must be an immediate");
2175    return MatchOperand_ParseFail;
2176  }
2177
2178  int64_t Val = CE->getValue();
2179  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2180  // normally, zero is represented in asm by omitting the rotate operand
2181  // entirely.
2182  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2183    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2184    return MatchOperand_ParseFail;
2185  }
2186
2187  E = Parser.getTok().getLoc();
2188  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2189
2190  return MatchOperand_Success;
2191}
2192
2193ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2194parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2195  SMLoc S = Parser.getTok().getLoc();
2196  // The bitfield descriptor is really two operands, the LSB and the width.
2197  if (Parser.getTok().isNot(AsmToken::Hash)) {
2198    Error(Parser.getTok().getLoc(), "'#' expected");
2199    return MatchOperand_ParseFail;
2200  }
2201  Parser.Lex(); // Eat hash token.
2202
2203  const MCExpr *LSBExpr;
2204  SMLoc E = Parser.getTok().getLoc();
2205  if (getParser().ParseExpression(LSBExpr)) {
2206    Error(E, "malformed immediate expression");
2207    return MatchOperand_ParseFail;
2208  }
2209  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2210  if (!CE) {
2211    Error(E, "'lsb' operand must be an immediate");
2212    return MatchOperand_ParseFail;
2213  }
2214
2215  int64_t LSB = CE->getValue();
2216  // The LSB must be in the range [0,31]
2217  if (LSB < 0 || LSB > 31) {
2218    Error(E, "'lsb' operand must be in the range [0,31]");
2219    return MatchOperand_ParseFail;
2220  }
2221  E = Parser.getTok().getLoc();
2222
2223  // Expect another immediate operand.
2224  if (Parser.getTok().isNot(AsmToken::Comma)) {
2225    Error(Parser.getTok().getLoc(), "too few operands");
2226    return MatchOperand_ParseFail;
2227  }
2228  Parser.Lex(); // Eat hash token.
2229  if (Parser.getTok().isNot(AsmToken::Hash)) {
2230    Error(Parser.getTok().getLoc(), "'#' expected");
2231    return MatchOperand_ParseFail;
2232  }
2233  Parser.Lex(); // Eat hash token.
2234
2235  const MCExpr *WidthExpr;
2236  if (getParser().ParseExpression(WidthExpr)) {
2237    Error(E, "malformed immediate expression");
2238    return MatchOperand_ParseFail;
2239  }
2240  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2241  if (!CE) {
2242    Error(E, "'width' operand must be an immediate");
2243    return MatchOperand_ParseFail;
2244  }
2245
2246  int64_t Width = CE->getValue();
2247  // The LSB must be in the range [1,32-lsb]
2248  if (Width < 1 || Width > 32 - LSB) {
2249    Error(E, "'width' operand must be in the range [1,32-lsb]");
2250    return MatchOperand_ParseFail;
2251  }
2252  E = Parser.getTok().getLoc();
2253
2254  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2255
2256  return MatchOperand_Success;
2257}
2258
2259ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2260parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2261  // Check for a post-index addressing register operand. Specifically:
2262  // postidx_reg := '+' register {, shift}
2263  //              | '-' register {, shift}
2264  //              | register {, shift}
2265
2266  // This method must return MatchOperand_NoMatch without consuming any tokens
2267  // in the case where there is no match, as other alternatives take other
2268  // parse methods.
2269  AsmToken Tok = Parser.getTok();
2270  SMLoc S = Tok.getLoc();
2271  bool haveEaten = false;
2272  bool isAdd = true;
2273  int Reg = -1;
2274  if (Tok.is(AsmToken::Plus)) {
2275    Parser.Lex(); // Eat the '+' token.
2276    haveEaten = true;
2277  } else if (Tok.is(AsmToken::Minus)) {
2278    Parser.Lex(); // Eat the '-' token.
2279    isAdd = false;
2280    haveEaten = true;
2281  }
2282  if (Parser.getTok().is(AsmToken::Identifier))
2283    Reg = tryParseRegister();
2284  if (Reg == -1) {
2285    if (!haveEaten)
2286      return MatchOperand_NoMatch;
2287    Error(Parser.getTok().getLoc(), "register expected");
2288    return MatchOperand_ParseFail;
2289  }
2290  SMLoc E = Parser.getTok().getLoc();
2291
2292  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2293  unsigned ShiftImm = 0;
2294  if (Parser.getTok().is(AsmToken::Comma)) {
2295    Parser.Lex(); // Eat the ','.
2296    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2297      return MatchOperand_ParseFail;
2298  }
2299
2300  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2301                                                  ShiftImm, S, E));
2302
2303  return MatchOperand_Success;
2304}
2305
2306ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2307parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2308  // Check for a post-index addressing register operand. Specifically:
2309  // am3offset := '+' register
2310  //              | '-' register
2311  //              | register
2312  //              | # imm
2313  //              | # + imm
2314  //              | # - imm
2315
2316  // This method must return MatchOperand_NoMatch without consuming any tokens
2317  // in the case where there is no match, as other alternatives take other
2318  // parse methods.
2319  AsmToken Tok = Parser.getTok();
2320  SMLoc S = Tok.getLoc();
2321
2322  // Do immediates first, as we always parse those if we have a '#'.
2323  if (Parser.getTok().is(AsmToken::Hash)) {
2324    Parser.Lex(); // Eat the '#'.
2325    // Explicitly look for a '-', as we need to encode negative zero
2326    // differently.
2327    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2328    const MCExpr *Offset;
2329    if (getParser().ParseExpression(Offset))
2330      return MatchOperand_ParseFail;
2331    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2332    if (!CE) {
2333      Error(S, "constant expression expected");
2334      return MatchOperand_ParseFail;
2335    }
2336    SMLoc E = Tok.getLoc();
2337    // Negative zero is encoded as the flag value INT32_MIN.
2338    int32_t Val = CE->getValue();
2339    if (isNegative && Val == 0)
2340      Val = INT32_MIN;
2341
2342    Operands.push_back(
2343      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2344
2345    return MatchOperand_Success;
2346  }
2347
2348
2349  bool haveEaten = false;
2350  bool isAdd = true;
2351  int Reg = -1;
2352  if (Tok.is(AsmToken::Plus)) {
2353    Parser.Lex(); // Eat the '+' token.
2354    haveEaten = true;
2355  } else if (Tok.is(AsmToken::Minus)) {
2356    Parser.Lex(); // Eat the '-' token.
2357    isAdd = false;
2358    haveEaten = true;
2359  }
2360  if (Parser.getTok().is(AsmToken::Identifier))
2361    Reg = tryParseRegister();
2362  if (Reg == -1) {
2363    if (!haveEaten)
2364      return MatchOperand_NoMatch;
2365    Error(Parser.getTok().getLoc(), "register expected");
2366    return MatchOperand_ParseFail;
2367  }
2368  SMLoc E = Parser.getTok().getLoc();
2369
2370  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2371                                                  0, S, E));
2372
2373  return MatchOperand_Success;
2374}
2375
2376/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2377/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2378/// when they refer multiple MIOperands inside a single one.
2379bool ARMAsmParser::
2380cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2381                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2382  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2383
2384  // Create a writeback register dummy placeholder.
2385  Inst.addOperand(MCOperand::CreateImm(0));
2386
2387  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2388  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2389  return true;
2390}
2391
2392/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2393/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2394/// when they refer multiple MIOperands inside a single one.
2395bool ARMAsmParser::
2396cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2397                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2398  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2399
2400  // Create a writeback register dummy placeholder.
2401  Inst.addOperand(MCOperand::CreateImm(0));
2402
2403  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2404  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2405  return true;
2406}
2407
2408
2409/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2410/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2411/// when they refer multiple MIOperands inside a single one.
2412bool ARMAsmParser::
2413cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2414                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2415  // Create a writeback register dummy placeholder.
2416  Inst.addOperand(MCOperand::CreateImm(0));
2417  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2418  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2419  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2420  return true;
2421}
2422
2423/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2424/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2425/// when they refer multiple MIOperands inside a single one.
2426bool ARMAsmParser::
2427cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2428                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2429  // Create a writeback register dummy placeholder.
2430  Inst.addOperand(MCOperand::CreateImm(0));
2431  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2432  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2433  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2434  return true;
2435}
2436
2437/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2438/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2439/// when they refer multiple MIOperands inside a single one.
2440bool ARMAsmParser::
2441cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2442                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2443  // Create a writeback register dummy placeholder.
2444  Inst.addOperand(MCOperand::CreateImm(0));
2445  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2446  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2447  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2448  return true;
2449}
2450
2451/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2452/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2453/// when they refer multiple MIOperands inside a single one.
2454bool ARMAsmParser::
2455cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2456                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2457  // Rt
2458  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2459  // Create a writeback register dummy placeholder.
2460  Inst.addOperand(MCOperand::CreateImm(0));
2461  // addr
2462  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2463  // offset
2464  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2465  // pred
2466  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2467  return true;
2468}
2469
2470/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2471/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2472/// when they refer multiple MIOperands inside a single one.
2473bool ARMAsmParser::
2474cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2475                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2476  // Rt
2477  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2478  // Create a writeback register dummy placeholder.
2479  Inst.addOperand(MCOperand::CreateImm(0));
2480  // addr
2481  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2482  // offset
2483  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2484  // pred
2485  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2486  return true;
2487}
2488
2489/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2490/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2491/// when they refer multiple MIOperands inside a single one.
2492bool ARMAsmParser::
2493cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2494                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2495  // Create a writeback register dummy placeholder.
2496  Inst.addOperand(MCOperand::CreateImm(0));
2497  // Rt
2498  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2499  // addr
2500  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2501  // offset
2502  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2503  // pred
2504  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2505  return true;
2506}
2507
2508/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2509/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2510/// when they refer multiple MIOperands inside a single one.
2511bool ARMAsmParser::
2512cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2513                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2514  // Create a writeback register dummy placeholder.
2515  Inst.addOperand(MCOperand::CreateImm(0));
2516  // Rt
2517  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2518  // addr
2519  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2520  // offset
2521  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2522  // pred
2523  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2524  return true;
2525}
2526
2527/// cvtLdrdPre - Convert parsed operands to MCInst.
2528/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2529/// when they refer multiple MIOperands inside a single one.
2530bool ARMAsmParser::
2531cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2532           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2533  // Rt, Rt2
2534  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2535  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2536  // Create a writeback register dummy placeholder.
2537  Inst.addOperand(MCOperand::CreateImm(0));
2538  // addr
2539  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2540  // pred
2541  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2542  return true;
2543}
2544
2545/// cvtStrdPre - Convert parsed operands to MCInst.
2546/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2547/// when they refer multiple MIOperands inside a single one.
2548bool ARMAsmParser::
2549cvtStrdPre(MCInst &Inst, unsigned Opcode,
2550           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2551  // Create a writeback register dummy placeholder.
2552  Inst.addOperand(MCOperand::CreateImm(0));
2553  // Rt, Rt2
2554  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2555  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2556  // addr
2557  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2558  // pred
2559  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2560  return true;
2561}
2562
2563/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2564/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2565/// when they refer multiple MIOperands inside a single one.
2566bool ARMAsmParser::
2567cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2568                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2569  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2570  // Create a writeback register dummy placeholder.
2571  Inst.addOperand(MCOperand::CreateImm(0));
2572  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2573  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2574  return true;
2575}
2576
2577/// cvtThumbMultiple- Convert parsed operands to MCInst.
2578/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2579/// when they refer multiple MIOperands inside a single one.
2580bool ARMAsmParser::
2581cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2582           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2583  // The second source operand must be the same register as the destination
2584  // operand.
2585  if (Operands.size() == 6 &&
2586      (((ARMOperand*)Operands[3])->getReg() !=
2587       ((ARMOperand*)Operands[5])->getReg()) &&
2588      (((ARMOperand*)Operands[3])->getReg() !=
2589       ((ARMOperand*)Operands[4])->getReg())) {
2590    Error(Operands[3]->getStartLoc(),
2591          "destination register must match source register");
2592    return false;
2593  }
2594  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2595  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2596  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2597  // If we have a three-operand form, use that, else the second source operand
2598  // is just the destination operand again.
2599  if (Operands.size() == 6)
2600    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2601  else
2602    Inst.addOperand(Inst.getOperand(0));
2603  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2604
2605  return true;
2606}
2607
2608/// Parse an ARM memory expression, return false if successful else return true
2609/// or an error.  The first token must be a '[' when called.
2610bool ARMAsmParser::
2611parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2612  SMLoc S, E;
2613  assert(Parser.getTok().is(AsmToken::LBrac) &&
2614         "Token is not a Left Bracket");
2615  S = Parser.getTok().getLoc();
2616  Parser.Lex(); // Eat left bracket token.
2617
2618  const AsmToken &BaseRegTok = Parser.getTok();
2619  int BaseRegNum = tryParseRegister();
2620  if (BaseRegNum == -1)
2621    return Error(BaseRegTok.getLoc(), "register expected");
2622
2623  // The next token must either be a comma or a closing bracket.
2624  const AsmToken &Tok = Parser.getTok();
2625  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2626    return Error(Tok.getLoc(), "malformed memory operand");
2627
2628  if (Tok.is(AsmToken::RBrac)) {
2629    E = Tok.getLoc();
2630    Parser.Lex(); // Eat right bracket token.
2631
2632    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2633                                             0, false, S, E));
2634
2635    return false;
2636  }
2637
2638  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2639  Parser.Lex(); // Eat the comma.
2640
2641  // If we have a '#' it's an immediate offset, else assume it's a register
2642  // offset.
2643  if (Parser.getTok().is(AsmToken::Hash)) {
2644    Parser.Lex(); // Eat the '#'.
2645    E = Parser.getTok().getLoc();
2646
2647    bool isNegative = getParser().getTok().is(AsmToken::Minus);
2648    const MCExpr *Offset;
2649    if (getParser().ParseExpression(Offset))
2650     return true;
2651
2652    // The expression has to be a constant. Memory references with relocations
2653    // don't come through here, as they use the <label> forms of the relevant
2654    // instructions.
2655    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2656    if (!CE)
2657      return Error (E, "constant expression expected");
2658
2659    // If the constant was #-0, represent it as INT32_MIN.
2660    int32_t Val = CE->getValue();
2661    if (isNegative && Val == 0)
2662      CE = MCConstantExpr::Create(INT32_MIN, getContext());
2663
2664    // Now we should have the closing ']'
2665    E = Parser.getTok().getLoc();
2666    if (Parser.getTok().isNot(AsmToken::RBrac))
2667      return Error(E, "']' expected");
2668    Parser.Lex(); // Eat right bracket token.
2669
2670    // Don't worry about range checking the value here. That's handled by
2671    // the is*() predicates.
2672    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2673                                             ARM_AM::no_shift, 0, false, S,E));
2674
2675    // If there's a pre-indexing writeback marker, '!', just add it as a token
2676    // operand.
2677    if (Parser.getTok().is(AsmToken::Exclaim)) {
2678      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2679      Parser.Lex(); // Eat the '!'.
2680    }
2681
2682    return false;
2683  }
2684
2685  // The register offset is optionally preceded by a '+' or '-'
2686  bool isNegative = false;
2687  if (Parser.getTok().is(AsmToken::Minus)) {
2688    isNegative = true;
2689    Parser.Lex(); // Eat the '-'.
2690  } else if (Parser.getTok().is(AsmToken::Plus)) {
2691    // Nothing to do.
2692    Parser.Lex(); // Eat the '+'.
2693  }
2694
2695  E = Parser.getTok().getLoc();
2696  int OffsetRegNum = tryParseRegister();
2697  if (OffsetRegNum == -1)
2698    return Error(E, "register expected");
2699
2700  // If there's a shift operator, handle it.
2701  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2702  unsigned ShiftImm = 0;
2703  if (Parser.getTok().is(AsmToken::Comma)) {
2704    Parser.Lex(); // Eat the ','.
2705    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2706      return true;
2707  }
2708
2709  // Now we should have the closing ']'
2710  E = Parser.getTok().getLoc();
2711  if (Parser.getTok().isNot(AsmToken::RBrac))
2712    return Error(E, "']' expected");
2713  Parser.Lex(); // Eat right bracket token.
2714
2715  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2716                                           ShiftType, ShiftImm, isNegative,
2717                                           S, E));
2718
2719  // If there's a pre-indexing writeback marker, '!', just add it as a token
2720  // operand.
2721  if (Parser.getTok().is(AsmToken::Exclaim)) {
2722    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2723    Parser.Lex(); // Eat the '!'.
2724  }
2725
2726  return false;
2727}
2728
2729/// parseMemRegOffsetShift - one of these two:
2730///   ( lsl | lsr | asr | ror ) , # shift_amount
2731///   rrx
2732/// return true if it parses a shift otherwise it returns false.
2733bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2734                                          unsigned &Amount) {
2735  SMLoc Loc = Parser.getTok().getLoc();
2736  const AsmToken &Tok = Parser.getTok();
2737  if (Tok.isNot(AsmToken::Identifier))
2738    return true;
2739  StringRef ShiftName = Tok.getString();
2740  if (ShiftName == "lsl" || ShiftName == "LSL")
2741    St = ARM_AM::lsl;
2742  else if (ShiftName == "lsr" || ShiftName == "LSR")
2743    St = ARM_AM::lsr;
2744  else if (ShiftName == "asr" || ShiftName == "ASR")
2745    St = ARM_AM::asr;
2746  else if (ShiftName == "ror" || ShiftName == "ROR")
2747    St = ARM_AM::ror;
2748  else if (ShiftName == "rrx" || ShiftName == "RRX")
2749    St = ARM_AM::rrx;
2750  else
2751    return Error(Loc, "illegal shift operator");
2752  Parser.Lex(); // Eat shift type token.
2753
2754  // rrx stands alone.
2755  Amount = 0;
2756  if (St != ARM_AM::rrx) {
2757    Loc = Parser.getTok().getLoc();
2758    // A '#' and a shift amount.
2759    const AsmToken &HashTok = Parser.getTok();
2760    if (HashTok.isNot(AsmToken::Hash))
2761      return Error(HashTok.getLoc(), "'#' expected");
2762    Parser.Lex(); // Eat hash token.
2763
2764    const MCExpr *Expr;
2765    if (getParser().ParseExpression(Expr))
2766      return true;
2767    // Range check the immediate.
2768    // lsl, ror: 0 <= imm <= 31
2769    // lsr, asr: 0 <= imm <= 32
2770    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2771    if (!CE)
2772      return Error(Loc, "shift amount must be an immediate");
2773    int64_t Imm = CE->getValue();
2774    if (Imm < 0 ||
2775        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2776        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2777      return Error(Loc, "immediate shift value out of range");
2778    Amount = Imm;
2779  }
2780
2781  return false;
2782}
2783
2784/// Parse a arm instruction operand.  For now this parses the operand regardless
2785/// of the mnemonic.
2786bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2787                                StringRef Mnemonic) {
2788  SMLoc S, E;
2789
2790  // Check if the current operand has a custom associated parser, if so, try to
2791  // custom parse the operand, or fallback to the general approach.
2792  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2793  if (ResTy == MatchOperand_Success)
2794    return false;
2795  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2796  // there was a match, but an error occurred, in which case, just return that
2797  // the operand parsing failed.
2798  if (ResTy == MatchOperand_ParseFail)
2799    return true;
2800
2801  switch (getLexer().getKind()) {
2802  default:
2803    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2804    return true;
2805  case AsmToken::Identifier: {
2806    if (!tryParseRegisterWithWriteBack(Operands))
2807      return false;
2808    int Res = tryParseShiftRegister(Operands);
2809    if (Res == 0) // success
2810      return false;
2811    else if (Res == -1) // irrecoverable error
2812      return true;
2813
2814    // Fall though for the Identifier case that is not a register or a
2815    // special name.
2816  }
2817  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2818  case AsmToken::Dot: {   // . as a branch target
2819    // This was not a register so parse other operands that start with an
2820    // identifier (like labels) as expressions and create them as immediates.
2821    const MCExpr *IdVal;
2822    S = Parser.getTok().getLoc();
2823    if (getParser().ParseExpression(IdVal))
2824      return true;
2825    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2826    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2827    return false;
2828  }
2829  case AsmToken::LBrac:
2830    return parseMemory(Operands);
2831  case AsmToken::LCurly:
2832    return parseRegisterList(Operands);
2833  case AsmToken::Hash: {
2834    // #42 -> immediate.
2835    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2836    S = Parser.getTok().getLoc();
2837    Parser.Lex();
2838    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2839    const MCExpr *ImmVal;
2840    if (getParser().ParseExpression(ImmVal))
2841      return true;
2842    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
2843    if (!CE) {
2844      Error(S, "constant expression expected");
2845      return MatchOperand_ParseFail;
2846    }
2847    int32_t Val = CE->getValue();
2848    if (isNegative && Val == 0)
2849      ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
2850    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2851    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2852    return false;
2853  }
2854  case AsmToken::Colon: {
2855    // ":lower16:" and ":upper16:" expression prefixes
2856    // FIXME: Check it's an expression prefix,
2857    // e.g. (FOO - :lower16:BAR) isn't legal.
2858    ARMMCExpr::VariantKind RefKind;
2859    if (parsePrefix(RefKind))
2860      return true;
2861
2862    const MCExpr *SubExprVal;
2863    if (getParser().ParseExpression(SubExprVal))
2864      return true;
2865
2866    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2867                                                   getContext());
2868    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2869    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2870    return false;
2871  }
2872  }
2873}
2874
2875// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2876//  :lower16: and :upper16:.
2877bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2878  RefKind = ARMMCExpr::VK_ARM_None;
2879
2880  // :lower16: and :upper16: modifiers
2881  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2882  Parser.Lex(); // Eat ':'
2883
2884  if (getLexer().isNot(AsmToken::Identifier)) {
2885    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2886    return true;
2887  }
2888
2889  StringRef IDVal = Parser.getTok().getIdentifier();
2890  if (IDVal == "lower16") {
2891    RefKind = ARMMCExpr::VK_ARM_LO16;
2892  } else if (IDVal == "upper16") {
2893    RefKind = ARMMCExpr::VK_ARM_HI16;
2894  } else {
2895    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2896    return true;
2897  }
2898  Parser.Lex();
2899
2900  if (getLexer().isNot(AsmToken::Colon)) {
2901    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2902    return true;
2903  }
2904  Parser.Lex(); // Eat the last ':'
2905  return false;
2906}
2907
2908const MCExpr *
2909ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2910                                MCSymbolRefExpr::VariantKind Variant) {
2911  // Recurse over the given expression, rebuilding it to apply the given variant
2912  // to the leftmost symbol.
2913  if (Variant == MCSymbolRefExpr::VK_None)
2914    return E;
2915
2916  switch (E->getKind()) {
2917  case MCExpr::Target:
2918    llvm_unreachable("Can't handle target expr yet");
2919  case MCExpr::Constant:
2920    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2921
2922  case MCExpr::SymbolRef: {
2923    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2924
2925    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2926      return 0;
2927
2928    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2929  }
2930
2931  case MCExpr::Unary:
2932    llvm_unreachable("Can't handle unary expressions yet");
2933
2934  case MCExpr::Binary: {
2935    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2936    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2937    const MCExpr *RHS = BE->getRHS();
2938    if (!LHS)
2939      return 0;
2940
2941    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2942  }
2943  }
2944
2945  assert(0 && "Invalid expression kind!");
2946  return 0;
2947}
2948
2949/// \brief Given a mnemonic, split out possible predication code and carry
2950/// setting letters to form a canonical mnemonic and flags.
2951//
2952// FIXME: Would be nice to autogen this.
2953// FIXME: This is a bit of a maze of special cases.
2954StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2955                                      unsigned &PredicationCode,
2956                                      bool &CarrySetting,
2957                                      unsigned &ProcessorIMod,
2958                                      StringRef &ITMask) {
2959  PredicationCode = ARMCC::AL;
2960  CarrySetting = false;
2961  ProcessorIMod = 0;
2962
2963  // Ignore some mnemonics we know aren't predicated forms.
2964  //
2965  // FIXME: Would be nice to autogen this.
2966  if ((Mnemonic == "movs" && isThumb()) ||
2967      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2968      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2969      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2970      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2971      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2972      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2973      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2974    return Mnemonic;
2975
2976  // First, split out any predication code. Ignore mnemonics we know aren't
2977  // predicated but do have a carry-set and so weren't caught above.
2978  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2979      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2980      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
2981      Mnemonic != "sbcs" && Mnemonic != "rscs") {
2982    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2983      .Case("eq", ARMCC::EQ)
2984      .Case("ne", ARMCC::NE)
2985      .Case("hs", ARMCC::HS)
2986      .Case("cs", ARMCC::HS)
2987      .Case("lo", ARMCC::LO)
2988      .Case("cc", ARMCC::LO)
2989      .Case("mi", ARMCC::MI)
2990      .Case("pl", ARMCC::PL)
2991      .Case("vs", ARMCC::VS)
2992      .Case("vc", ARMCC::VC)
2993      .Case("hi", ARMCC::HI)
2994      .Case("ls", ARMCC::LS)
2995      .Case("ge", ARMCC::GE)
2996      .Case("lt", ARMCC::LT)
2997      .Case("gt", ARMCC::GT)
2998      .Case("le", ARMCC::LE)
2999      .Case("al", ARMCC::AL)
3000      .Default(~0U);
3001    if (CC != ~0U) {
3002      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3003      PredicationCode = CC;
3004    }
3005  }
3006
3007  // Next, determine if we have a carry setting bit. We explicitly ignore all
3008  // the instructions we know end in 's'.
3009  if (Mnemonic.endswith("s") &&
3010      !(Mnemonic == "cps" || Mnemonic == "mls" ||
3011        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3012        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3013        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3014        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3015        (Mnemonic == "movs" && isThumb()))) {
3016    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3017    CarrySetting = true;
3018  }
3019
3020  // The "cps" instruction can have a interrupt mode operand which is glued into
3021  // the mnemonic. Check if this is the case, split it and parse the imod op
3022  if (Mnemonic.startswith("cps")) {
3023    // Split out any imod code.
3024    unsigned IMod =
3025      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3026      .Case("ie", ARM_PROC::IE)
3027      .Case("id", ARM_PROC::ID)
3028      .Default(~0U);
3029    if (IMod != ~0U) {
3030      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3031      ProcessorIMod = IMod;
3032    }
3033  }
3034
3035  // The "it" instruction has the condition mask on the end of the mnemonic.
3036  if (Mnemonic.startswith("it")) {
3037    ITMask = Mnemonic.slice(2, Mnemonic.size());
3038    Mnemonic = Mnemonic.slice(0, 2);
3039  }
3040
3041  return Mnemonic;
3042}
3043
3044/// \brief Given a canonical mnemonic, determine if the instruction ever allows
3045/// inclusion of carry set or predication code operands.
3046//
3047// FIXME: It would be nice to autogen this.
3048void ARMAsmParser::
3049getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3050                      bool &CanAcceptPredicationCode) {
3051  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3052      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3053      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
3054      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3055      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
3056      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3057      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
3058      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
3059      (Mnemonic == "mov" && !isThumb())) {
3060    CanAcceptCarrySet = true;
3061  } else {
3062    CanAcceptCarrySet = false;
3063  }
3064
3065  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3066      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3067      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3068      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3069      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3070      (Mnemonic == "clrex" && !isThumb()) ||
3071      (Mnemonic == "nop" && isThumbOne()) ||
3072      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
3073       !isThumb()) ||
3074      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3075       !isThumb()) ||
3076      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
3077    CanAcceptPredicationCode = false;
3078  } else {
3079    CanAcceptPredicationCode = true;
3080  }
3081
3082  if (isThumb())
3083    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3084        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3085      CanAcceptPredicationCode = false;
3086}
3087
3088bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3089                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3090  // FIXME: This is all horribly hacky. We really need a better way to deal
3091  // with optional operands like this in the matcher table.
3092
3093  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3094  // another does not. Specifically, the MOVW instruction does not. So we
3095  // special case it here and remove the defaulted (non-setting) cc_out
3096  // operand if that's the instruction we're trying to match.
3097  //
3098  // We do this as post-processing of the explicit operands rather than just
3099  // conditionally adding the cc_out in the first place because we need
3100  // to check the type of the parsed immediate operand.
3101  if (Mnemonic == "mov" && Operands.size() > 4 &&
3102      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3103      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3104      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3105    return true;
3106
3107  // Register-register 'add' for thumb does not have a cc_out operand
3108  // when there are only two register operands.
3109  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3110      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3111      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3112      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3113    return true;
3114  // Register-register 'add' for thumb does not have a cc_out operand
3115  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
3116  // have to check the immediate range here since Thumb2 has a variant
3117  // that can handle a different range and has a cc_out operand.
3118  if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
3119      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3120      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3121      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3122      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3123      (static_cast<ARMOperand*>(Operands[5])->isReg() ||
3124       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
3125    return true;
3126  // For Thumb2, add immediate does not have a cc_out operand for the
3127  // imm0_4096 variant. That's the least-preferred variant when
3128  // selecting via the generic "add" mnemonic, so to know that we
3129  // should remove the cc_out operand, we have to explicitly check that
3130  // it's not one of the other variants. Ugh.
3131  if (isThumbTwo() && Mnemonic == "add" && Operands.size() == 6 &&
3132      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3133      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3134      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3135    // Nest conditions rather than one big 'if' statement for readability.
3136    //
3137    // If either register is a high reg, it's either one of the SP
3138    // variants (handled above) or a 32-bit encoding, so we just
3139    // check against T3.
3140    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3141         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
3142        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
3143      return false;
3144    // If both registers are low, we're in an IT block, and the immediate is
3145    // in range, we should use encoding T1 instead, which has a cc_out.
3146    if (inITBlock() &&
3147        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3148        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3149        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
3150      return false;
3151
3152    // Otherwise, we use encoding T4, which does not have a cc_out
3153    // operand.
3154    return true;
3155  }
3156
3157
3158  // Register-register 'add/sub' for thumb does not have a cc_out operand
3159  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3160  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3161  // right, this will result in better diagnostics (which operand is off)
3162  // anyway.
3163  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3164      (Operands.size() == 5 || Operands.size() == 6) &&
3165      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3166      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3167      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3168    return true;
3169
3170  return false;
3171}
3172
3173/// Parse an arm instruction mnemonic followed by its operands.
3174bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3175                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3176  // Create the leading tokens for the mnemonic, split by '.' characters.
3177  size_t Start = 0, Next = Name.find('.');
3178  StringRef Mnemonic = Name.slice(Start, Next);
3179
3180  // Split out the predication code and carry setting flag from the mnemonic.
3181  unsigned PredicationCode;
3182  unsigned ProcessorIMod;
3183  bool CarrySetting;
3184  StringRef ITMask;
3185  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3186                           ProcessorIMod, ITMask);
3187
3188  // In Thumb1, only the branch (B) instruction can be predicated.
3189  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3190    Parser.EatToEndOfStatement();
3191    return Error(NameLoc, "conditional execution not supported in Thumb1");
3192  }
3193
3194  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3195
3196  // Handle the IT instruction ITMask. Convert it to a bitmask. This
3197  // is the mask as it will be for the IT encoding if the conditional
3198  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3199  // where the conditional bit0 is zero, the instruction post-processing
3200  // will adjust the mask accordingly.
3201  if (Mnemonic == "it") {
3202    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3203    if (ITMask.size() > 3) {
3204      Parser.EatToEndOfStatement();
3205      return Error(Loc, "too many conditions on IT instruction");
3206    }
3207    unsigned Mask = 8;
3208    for (unsigned i = ITMask.size(); i != 0; --i) {
3209      char pos = ITMask[i - 1];
3210      if (pos != 't' && pos != 'e') {
3211        Parser.EatToEndOfStatement();
3212        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
3213      }
3214      Mask >>= 1;
3215      if (ITMask[i - 1] == 't')
3216        Mask |= 8;
3217    }
3218    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
3219  }
3220
3221  // FIXME: This is all a pretty gross hack. We should automatically handle
3222  // optional operands like this via tblgen.
3223
3224  // Next, add the CCOut and ConditionCode operands, if needed.
3225  //
3226  // For mnemonics which can ever incorporate a carry setting bit or predication
3227  // code, our matching model involves us always generating CCOut and
3228  // ConditionCode operands to match the mnemonic "as written" and then we let
3229  // the matcher deal with finding the right instruction or generating an
3230  // appropriate error.
3231  bool CanAcceptCarrySet, CanAcceptPredicationCode;
3232  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3233
3234  // If we had a carry-set on an instruction that can't do that, issue an
3235  // error.
3236  if (!CanAcceptCarrySet && CarrySetting) {
3237    Parser.EatToEndOfStatement();
3238    return Error(NameLoc, "instruction '" + Mnemonic +
3239                 "' can not set flags, but 's' suffix specified");
3240  }
3241  // If we had a predication code on an instruction that can't do that, issue an
3242  // error.
3243  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3244    Parser.EatToEndOfStatement();
3245    return Error(NameLoc, "instruction '" + Mnemonic +
3246                 "' is not predicable, but condition code specified");
3247  }
3248
3249  // Add the carry setting operand, if necessary.
3250  if (CanAcceptCarrySet) {
3251    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
3252    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3253                                               Loc));
3254  }
3255
3256  // Add the predication code operand, if necessary.
3257  if (CanAcceptPredicationCode) {
3258    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
3259                                      CarrySetting);
3260    Operands.push_back(ARMOperand::CreateCondCode(
3261                         ARMCC::CondCodes(PredicationCode), Loc));
3262  }
3263
3264  // Add the processor imod operand, if necessary.
3265  if (ProcessorIMod) {
3266    Operands.push_back(ARMOperand::CreateImm(
3267          MCConstantExpr::Create(ProcessorIMod, getContext()),
3268                                 NameLoc, NameLoc));
3269  }
3270
3271  // Add the remaining tokens in the mnemonic.
3272  while (Next != StringRef::npos) {
3273    Start = Next;
3274    Next = Name.find('.', Start + 1);
3275    StringRef ExtraToken = Name.slice(Start, Next);
3276
3277    // For now, we're only parsing Thumb1 (for the most part), so
3278    // just ignore ".n" qualifiers. We'll use them to restrict
3279    // matching when we do Thumb2.
3280    if (ExtraToken != ".n") {
3281      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
3282      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
3283    }
3284  }
3285
3286  // Read the remaining operands.
3287  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3288    // Read the first operand.
3289    if (parseOperand(Operands, Mnemonic)) {
3290      Parser.EatToEndOfStatement();
3291      return true;
3292    }
3293
3294    while (getLexer().is(AsmToken::Comma)) {
3295      Parser.Lex();  // Eat the comma.
3296
3297      // Parse and remember the operand.
3298      if (parseOperand(Operands, Mnemonic)) {
3299        Parser.EatToEndOfStatement();
3300        return true;
3301      }
3302    }
3303  }
3304
3305  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3306    Parser.EatToEndOfStatement();
3307    return TokError("unexpected token in argument list");
3308  }
3309
3310  Parser.Lex(); // Consume the EndOfStatement
3311
3312  // Some instructions, mostly Thumb, have forms for the same mnemonic that
3313  // do and don't have a cc_out optional-def operand. With some spot-checks
3314  // of the operand list, we can figure out which variant we're trying to
3315  // parse and adjust accordingly before actually matching. We shouldn't ever
3316  // try to remove a cc_out operand that was explicitly set on the the
3317  // mnemonic, of course (CarrySetting == true). Reason number #317 the
3318  // table driven matcher doesn't fit well with the ARM instruction set.
3319  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
3320    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3321    Operands.erase(Operands.begin() + 1);
3322    delete Op;
3323  }
3324
3325  // ARM mode 'blx' need special handling, as the register operand version
3326  // is predicable, but the label operand version is not. So, we can't rely
3327  // on the Mnemonic based checking to correctly figure out when to put
3328  // a CondCode operand in the list. If we're trying to match the label
3329  // version, remove the CondCode operand here.
3330  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3331      static_cast<ARMOperand*>(Operands[2])->isImm()) {
3332    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3333    Operands.erase(Operands.begin() + 1);
3334    delete Op;
3335  }
3336
3337  // The vector-compare-to-zero instructions have a literal token "#0" at
3338  // the end that comes to here as an immediate operand. Convert it to a
3339  // token to play nicely with the matcher.
3340  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3341      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3342      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3343    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3344    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3345    if (CE && CE->getValue() == 0) {
3346      Operands.erase(Operands.begin() + 5);
3347      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3348      delete Op;
3349    }
3350  }
3351  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3352  // end. Convert it to a token here.
3353  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3354      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3355    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3356    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3357    if (CE && CE->getValue() == 0) {
3358      Operands.erase(Operands.begin() + 5);
3359      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3360      delete Op;
3361    }
3362  }
3363
3364  return false;
3365}
3366
3367// Validate context-sensitive operand constraints.
3368
3369// return 'true' if register list contains non-low GPR registers,
3370// 'false' otherwise. If Reg is in the register list or is HiReg, set
3371// 'containsReg' to true.
3372static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3373                                 unsigned HiReg, bool &containsReg) {
3374  containsReg = false;
3375  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3376    unsigned OpReg = Inst.getOperand(i).getReg();
3377    if (OpReg == Reg)
3378      containsReg = true;
3379    // Anything other than a low register isn't legal here.
3380    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3381      return true;
3382  }
3383  return false;
3384}
3385
3386// Check if the specified regisgter is in the register list of the inst,
3387// starting at the indicated operand number.
3388static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
3389  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3390    unsigned OpReg = Inst.getOperand(i).getReg();
3391    if (OpReg == Reg)
3392      return true;
3393  }
3394  return false;
3395}
3396
3397// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3398// the ARMInsts array) instead. Getting that here requires awkward
3399// API changes, though. Better way?
3400namespace llvm {
3401extern MCInstrDesc ARMInsts[];
3402}
3403static MCInstrDesc &getInstDesc(unsigned Opcode) {
3404  return ARMInsts[Opcode];
3405}
3406
3407// FIXME: We would really like to be able to tablegen'erate this.
3408bool ARMAsmParser::
3409validateInstruction(MCInst &Inst,
3410                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3411  MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3412  SMLoc Loc = Operands[0]->getStartLoc();
3413  // Check the IT block state first.
3414  if (inITBlock()) {
3415    unsigned bit = 1;
3416    if (ITState.FirstCond)
3417      ITState.FirstCond = false;
3418    else
3419      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
3420    // The instruction must be predicable.
3421    if (!MCID.isPredicable())
3422      return Error(Loc, "instructions in IT block must be predicable");
3423    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
3424    unsigned ITCond = bit ? ITState.Cond :
3425      ARMCC::getOppositeCondition(ITState.Cond);
3426    if (Cond != ITCond) {
3427      // Find the condition code Operand to get its SMLoc information.
3428      SMLoc CondLoc;
3429      for (unsigned i = 1; i < Operands.size(); ++i)
3430        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
3431          CondLoc = Operands[i]->getStartLoc();
3432      return Error(CondLoc, "incorrect condition in IT block; got '" +
3433                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
3434                   "', but expected '" +
3435                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
3436    }
3437  // Check for non-'al' condition codes outside of the IT block.
3438  } else if (isThumbTwo() && MCID.isPredicable() &&
3439             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
3440             ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
3441             Inst.getOpcode() != ARM::t2Bcc)
3442    return Error(Loc, "predicated instructions must be in IT block");
3443
3444  switch (Inst.getOpcode()) {
3445  case ARM::LDRD:
3446  case ARM::LDRD_PRE:
3447  case ARM::LDRD_POST:
3448  case ARM::LDREXD: {
3449    // Rt2 must be Rt + 1.
3450    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3451    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3452    if (Rt2 != Rt + 1)
3453      return Error(Operands[3]->getStartLoc(),
3454                   "destination operands must be sequential");
3455    return false;
3456  }
3457  case ARM::STRD: {
3458    // Rt2 must be Rt + 1.
3459    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3460    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3461    if (Rt2 != Rt + 1)
3462      return Error(Operands[3]->getStartLoc(),
3463                   "source operands must be sequential");
3464    return false;
3465  }
3466  case ARM::STRD_PRE:
3467  case ARM::STRD_POST:
3468  case ARM::STREXD: {
3469    // Rt2 must be Rt + 1.
3470    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3471    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3472    if (Rt2 != Rt + 1)
3473      return Error(Operands[3]->getStartLoc(),
3474                   "source operands must be sequential");
3475    return false;
3476  }
3477  case ARM::SBFX:
3478  case ARM::UBFX: {
3479    // width must be in range [1, 32-lsb]
3480    unsigned lsb = Inst.getOperand(2).getImm();
3481    unsigned widthm1 = Inst.getOperand(3).getImm();
3482    if (widthm1 >= 32 - lsb)
3483      return Error(Operands[5]->getStartLoc(),
3484                   "bitfield width must be in range [1,32-lsb]");
3485    return false;
3486  }
3487  case ARM::tLDMIA: {
3488    // If we're parsing Thumb2, the .w variant is available and handles
3489    // most cases that are normally illegal for a Thumb1 LDM
3490    // instruction. We'll make the transformation in processInstruction()
3491    // if necessary.
3492    //
3493    // Thumb LDM instructions are writeback iff the base register is not
3494    // in the register list.
3495    unsigned Rn = Inst.getOperand(0).getReg();
3496    bool hasWritebackToken =
3497      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3498       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3499    bool listContainsBase;
3500    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
3501      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3502                   "registers must be in range r0-r7");
3503    // If we should have writeback, then there should be a '!' token.
3504    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
3505      return Error(Operands[2]->getStartLoc(),
3506                   "writeback operator '!' expected");
3507    // If we should not have writeback, there must not be a '!'. This is
3508    // true even for the 32-bit wide encodings.
3509    if (listContainsBase && hasWritebackToken)
3510      return Error(Operands[3]->getStartLoc(),
3511                   "writeback operator '!' not allowed when base register "
3512                   "in register list");
3513
3514    break;
3515  }
3516  case ARM::t2LDMIA_UPD: {
3517    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
3518      return Error(Operands[4]->getStartLoc(),
3519                   "writeback operator '!' not allowed when base register "
3520                   "in register list");
3521    break;
3522  }
3523  case ARM::tPOP: {
3524    bool listContainsBase;
3525    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3526      return Error(Operands[2]->getStartLoc(),
3527                   "registers must be in range r0-r7 or pc");
3528    break;
3529  }
3530  case ARM::tPUSH: {
3531    bool listContainsBase;
3532    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3533      return Error(Operands[2]->getStartLoc(),
3534                   "registers must be in range r0-r7 or lr");
3535    break;
3536  }
3537  case ARM::tSTMIA_UPD: {
3538    bool listContainsBase;
3539    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3540      return Error(Operands[4]->getStartLoc(),
3541                   "registers must be in range r0-r7");
3542    break;
3543  }
3544  }
3545
3546  return false;
3547}
3548
3549void ARMAsmParser::
3550processInstruction(MCInst &Inst,
3551                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3552  switch (Inst.getOpcode()) {
3553  case ARM::LDMIA_UPD:
3554    // If this is a load of a single register via a 'pop', then we should use
3555    // a post-indexed LDR instruction instead, per the ARM ARM.
3556    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3557        Inst.getNumOperands() == 5) {
3558      MCInst TmpInst;
3559      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3560      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3561      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3562      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3563      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3564      TmpInst.addOperand(MCOperand::CreateImm(4));
3565      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3566      TmpInst.addOperand(Inst.getOperand(3));
3567      Inst = TmpInst;
3568    }
3569    break;
3570  case ARM::STMDB_UPD:
3571    // If this is a store of a single register via a 'push', then we should use
3572    // a pre-indexed STR instruction instead, per the ARM ARM.
3573    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3574        Inst.getNumOperands() == 5) {
3575      MCInst TmpInst;
3576      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3577      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3578      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3579      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3580      TmpInst.addOperand(MCOperand::CreateImm(-4));
3581      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3582      TmpInst.addOperand(Inst.getOperand(3));
3583      Inst = TmpInst;
3584    }
3585    break;
3586  case ARM::tADDi8:
3587    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3588    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3589    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3590    // to encoding T1 if <Rd> is omitted."
3591    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3592      Inst.setOpcode(ARM::tADDi3);
3593    break;
3594  case ARM::t2Bcc:
3595    // If the conditional is AL or we're in an IT block, we really want t2B.
3596    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
3597      Inst.setOpcode(ARM::t2B);
3598    break;
3599  case ARM::tBcc:
3600    // If the conditional is AL, we really want tB.
3601    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3602      Inst.setOpcode(ARM::tB);
3603    break;
3604  case ARM::tLDMIA: {
3605    // If the register list contains any high registers, or if the writeback
3606    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
3607    // instead if we're in Thumb2. Otherwise, this should have generated
3608    // an error in validateInstruction().
3609    unsigned Rn = Inst.getOperand(0).getReg();
3610    bool hasWritebackToken =
3611      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3612       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3613    bool listContainsBase;
3614    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
3615        (!listContainsBase && !hasWritebackToken) ||
3616        (listContainsBase && hasWritebackToken)) {
3617      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
3618      assert (isThumbTwo());
3619      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
3620      // If we're switching to the updating version, we need to insert
3621      // the writeback tied operand.
3622      if (hasWritebackToken)
3623        Inst.insert(Inst.begin(),
3624                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
3625    }
3626    break;
3627  }
3628  case ARM::t2IT: {
3629    // The mask bits for all but the first condition are represented as
3630    // the low bit of the condition code value implies 't'. We currently
3631    // always have 1 implies 't', so XOR toggle the bits if the low bit
3632    // of the condition code is zero. The encoding also expects the low
3633    // bit of the condition to be encoded as bit 4 of the mask operand,
3634    // so mask that in if needed
3635    MCOperand &MO = Inst.getOperand(1);
3636    unsigned Mask = MO.getImm();
3637    unsigned OrigMask = Mask;
3638    unsigned TZ = CountTrailingZeros_32(Mask);
3639    if ((Inst.getOperand(0).getImm() & 1) == 0) {
3640      assert(Mask && TZ <= 3 && "illegal IT mask value!");
3641      for (unsigned i = 3; i != TZ; --i)
3642        Mask ^= 1 << i;
3643    } else
3644      Mask |= 0x10;
3645    MO.setImm(Mask);
3646
3647    // Set up the IT block state according to the IT instruction we just
3648    // matched.
3649    assert(!inITBlock() && "nested IT blocks?!");
3650    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
3651    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
3652    ITState.CurPosition = 0;
3653    ITState.FirstCond = true;
3654    break;
3655  }
3656  }
3657}
3658
3659unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3660  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3661  // suffix depending on whether they're in an IT block or not.
3662  unsigned Opc = Inst.getOpcode();
3663  MCInstrDesc &MCID = getInstDesc(Opc);
3664  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3665    assert(MCID.hasOptionalDef() &&
3666           "optionally flag setting instruction missing optional def operand");
3667    assert(MCID.NumOperands == Inst.getNumOperands() &&
3668           "operand count mismatch!");
3669    // Find the optional-def operand (cc_out).
3670    unsigned OpNo;
3671    for (OpNo = 0;
3672         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3673         ++OpNo)
3674      ;
3675    // If we're parsing Thumb1, reject it completely.
3676    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3677      return Match_MnemonicFail;
3678    // If we're parsing Thumb2, which form is legal depends on whether we're
3679    // in an IT block.
3680    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
3681        !inITBlock())
3682      return Match_RequiresITBlock;
3683    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
3684        inITBlock())
3685      return Match_RequiresNotITBlock;
3686  }
3687  // Some high-register supporting Thumb1 encodings only allow both registers
3688  // to be from r0-r7 when in Thumb2.
3689  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3690           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3691           isARMLowRegister(Inst.getOperand(2).getReg()))
3692    return Match_RequiresThumb2;
3693  // Others only require ARMv6 or later.
3694  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3695           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3696           isARMLowRegister(Inst.getOperand(1).getReg()))
3697    return Match_RequiresV6;
3698  return Match_Success;
3699}
3700
3701bool ARMAsmParser::
3702MatchAndEmitInstruction(SMLoc IDLoc,
3703                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3704                        MCStreamer &Out) {
3705  MCInst Inst;
3706  unsigned ErrorInfo;
3707  unsigned MatchResult;
3708  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3709  switch (MatchResult) {
3710  default: break;
3711  case Match_Success:
3712    // Context sensitive operand constraints aren't handled by the matcher,
3713    // so check them here.
3714    if (validateInstruction(Inst, Operands)) {
3715      // Still progress the IT block, otherwise one wrong condition causes
3716      // nasty cascading errors.
3717      forwardITPosition();
3718      return true;
3719    }
3720
3721    // Some instructions need post-processing to, for example, tweak which
3722    // encoding is selected.
3723    processInstruction(Inst, Operands);
3724
3725    // Only move forward at the very end so that everything in validate
3726    // and process gets a consistent answer about whether we're in an IT
3727    // block.
3728    forwardITPosition();
3729
3730    Out.EmitInstruction(Inst);
3731    return false;
3732  case Match_MissingFeature:
3733    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3734    return true;
3735  case Match_InvalidOperand: {
3736    SMLoc ErrorLoc = IDLoc;
3737    if (ErrorInfo != ~0U) {
3738      if (ErrorInfo >= Operands.size())
3739        return Error(IDLoc, "too few operands for instruction");
3740
3741      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3742      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3743    }
3744
3745    return Error(ErrorLoc, "invalid operand for instruction");
3746  }
3747  case Match_MnemonicFail:
3748    return Error(IDLoc, "invalid instruction");
3749  case Match_ConversionFail:
3750    // The converter function will have already emited a diagnostic.
3751    return true;
3752  case Match_RequiresNotITBlock:
3753    return Error(IDLoc, "flag setting instruction only valid outside IT block");
3754  case Match_RequiresITBlock:
3755    return Error(IDLoc, "instruction only valid inside IT block");
3756  case Match_RequiresV6:
3757    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3758  case Match_RequiresThumb2:
3759    return Error(IDLoc, "instruction variant requires Thumb2");
3760  }
3761
3762  llvm_unreachable("Implement any new match types added!");
3763  return true;
3764}
3765
3766/// parseDirective parses the arm specific directives
3767bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3768  StringRef IDVal = DirectiveID.getIdentifier();
3769  if (IDVal == ".word")
3770    return parseDirectiveWord(4, DirectiveID.getLoc());
3771  else if (IDVal == ".thumb")
3772    return parseDirectiveThumb(DirectiveID.getLoc());
3773  else if (IDVal == ".thumb_func")
3774    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3775  else if (IDVal == ".code")
3776    return parseDirectiveCode(DirectiveID.getLoc());
3777  else if (IDVal == ".syntax")
3778    return parseDirectiveSyntax(DirectiveID.getLoc());
3779  return true;
3780}
3781
3782/// parseDirectiveWord
3783///  ::= .word [ expression (, expression)* ]
3784bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3785  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3786    for (;;) {
3787      const MCExpr *Value;
3788      if (getParser().ParseExpression(Value))
3789        return true;
3790
3791      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3792
3793      if (getLexer().is(AsmToken::EndOfStatement))
3794        break;
3795
3796      // FIXME: Improve diagnostic.
3797      if (getLexer().isNot(AsmToken::Comma))
3798        return Error(L, "unexpected token in directive");
3799      Parser.Lex();
3800    }
3801  }
3802
3803  Parser.Lex();
3804  return false;
3805}
3806
3807/// parseDirectiveThumb
3808///  ::= .thumb
3809bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3810  if (getLexer().isNot(AsmToken::EndOfStatement))
3811    return Error(L, "unexpected token in directive");
3812  Parser.Lex();
3813
3814  // TODO: set thumb mode
3815  // TODO: tell the MC streamer the mode
3816  // getParser().getStreamer().Emit???();
3817  return false;
3818}
3819
3820/// parseDirectiveThumbFunc
3821///  ::= .thumbfunc symbol_name
3822bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3823  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3824  bool isMachO = MAI.hasSubsectionsViaSymbols();
3825  StringRef Name;
3826
3827  // Darwin asm has function name after .thumb_func direction
3828  // ELF doesn't
3829  if (isMachO) {
3830    const AsmToken &Tok = Parser.getTok();
3831    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3832      return Error(L, "unexpected token in .thumb_func directive");
3833    Name = Tok.getString();
3834    Parser.Lex(); // Consume the identifier token.
3835  }
3836
3837  if (getLexer().isNot(AsmToken::EndOfStatement))
3838    return Error(L, "unexpected token in directive");
3839  Parser.Lex();
3840
3841  // FIXME: assuming function name will be the line following .thumb_func
3842  if (!isMachO) {
3843    Name = Parser.getTok().getString();
3844  }
3845
3846  // Mark symbol as a thumb symbol.
3847  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3848  getParser().getStreamer().EmitThumbFunc(Func);
3849  return false;
3850}
3851
3852/// parseDirectiveSyntax
3853///  ::= .syntax unified | divided
3854bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3855  const AsmToken &Tok = Parser.getTok();
3856  if (Tok.isNot(AsmToken::Identifier))
3857    return Error(L, "unexpected token in .syntax directive");
3858  StringRef Mode = Tok.getString();
3859  if (Mode == "unified" || Mode == "UNIFIED")
3860    Parser.Lex();
3861  else if (Mode == "divided" || Mode == "DIVIDED")
3862    return Error(L, "'.syntax divided' arm asssembly not supported");
3863  else
3864    return Error(L, "unrecognized syntax mode in .syntax directive");
3865
3866  if (getLexer().isNot(AsmToken::EndOfStatement))
3867    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3868  Parser.Lex();
3869
3870  // TODO tell the MC streamer the mode
3871  // getParser().getStreamer().Emit???();
3872  return false;
3873}
3874
3875/// parseDirectiveCode
3876///  ::= .code 16 | 32
3877bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3878  const AsmToken &Tok = Parser.getTok();
3879  if (Tok.isNot(AsmToken::Integer))
3880    return Error(L, "unexpected token in .code directive");
3881  int64_t Val = Parser.getTok().getIntVal();
3882  if (Val == 16)
3883    Parser.Lex();
3884  else if (Val == 32)
3885    Parser.Lex();
3886  else
3887    return Error(L, "invalid operand to .code directive");
3888
3889  if (getLexer().isNot(AsmToken::EndOfStatement))
3890    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3891  Parser.Lex();
3892
3893  if (Val == 16) {
3894    if (!isThumb())
3895      SwitchMode();
3896    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3897  } else {
3898    if (isThumb())
3899      SwitchMode();
3900    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3901  }
3902
3903  return false;
3904}
3905
3906extern "C" void LLVMInitializeARMAsmLexer();
3907
3908/// Force static initialization.
3909extern "C" void LLVMInitializeARMAsmParser() {
3910  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3911  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3912  LLVMInitializeARMAsmLexer();
3913}
3914
3915#define GET_REGISTER_MATCHER
3916#define GET_MATCHER_IMPLEMENTATION
3917#include "ARMGenAsmMatcher.inc"
3918