ARMAsmParser.cpp revision c9a9b442853ee086492d6ad1384a2de2fea9b43b 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringExtras.h"
34#include "llvm/ADT/StringSwitch.h"
35#include "llvm/ADT/Twine.h"
36
37using namespace llvm;
38
39namespace {
40
41class ARMOperand;
42
43class ARMAsmParser : public MCTargetAsmParser {
44  MCSubtargetInfo &STI;
45  MCAsmParser &Parser;
46
47  struct {
48    ARMCC::CondCodes Cond;    // Condition for IT block.
49    unsigned Mask:4;          // Condition mask for instructions.
50                              // Starting at first 1 (from lsb).
51                              //   '1'  condition as indicated in IT.
52                              //   '0'  inverse of condition (else).
53                              // Count of instructions in IT block is
54                              // 4 - trailingzeroes(mask)
55
56    bool FirstCond;           // Explicit flag for when we're parsing the
57                              // First instruction in the IT block. It's
58                              // implied in the mask, so needs special
59                              // handling.
60
61    unsigned CurPosition;     // Current position in parsing of IT
62                              // block. In range [0,3]. Initialized
63                              // according to count of instructions in block.
64                              // ~0U if no active IT block.
65  } ITState;
66  bool inITBlock() { return ITState.CurPosition != ~0U;}
67
68
69  MCAsmParser &getParser() const { return Parser; }
70  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
71
72  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
73  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
74
75  int tryParseRegister();
76  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
77  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
78  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
79  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
80  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
81  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
82  const MCExpr *applyPrefixToExpr(const MCExpr *E,
83                                  MCSymbolRefExpr::VariantKind Variant);
84
85
86  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
87                              unsigned &ShiftAmount);
88  bool parseDirectiveWord(unsigned Size, SMLoc L);
89  bool parseDirectiveThumb(SMLoc L);
90  bool parseDirectiveThumbFunc(SMLoc L);
91  bool parseDirectiveCode(SMLoc L);
92  bool parseDirectiveSyntax(SMLoc L);
93
94  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
95                          bool &CarrySetting, unsigned &ProcessorIMod,
96                          StringRef &ITMask);
97  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
98                             bool &CanAcceptPredicationCode);
99
100  bool isThumb() const {
101    // FIXME: Can tablegen auto-generate this?
102    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
103  }
104  bool isThumbOne() const {
105    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
106  }
107  bool isThumbTwo() const {
108    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
109  }
110  bool hasV6Ops() const {
111    return STI.getFeatureBits() & ARM::HasV6Ops;
112  }
113  void SwitchMode() {
114    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
115    setAvailableFeatures(FB);
116  }
117
118  /// @name Auto-generated Match Functions
119  /// {
120
121#define GET_ASSEMBLER_HEADER
122#include "ARMGenAsmMatcher.inc"
123
124  /// }
125
126  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
127  OperandMatchResultTy parseCoprocNumOperand(
128    SmallVectorImpl<MCParsedAsmOperand*>&);
129  OperandMatchResultTy parseCoprocRegOperand(
130    SmallVectorImpl<MCParsedAsmOperand*>&);
131  OperandMatchResultTy parseMemBarrierOptOperand(
132    SmallVectorImpl<MCParsedAsmOperand*>&);
133  OperandMatchResultTy parseProcIFlagsOperand(
134    SmallVectorImpl<MCParsedAsmOperand*>&);
135  OperandMatchResultTy parseMSRMaskOperand(
136    SmallVectorImpl<MCParsedAsmOperand*>&);
137  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
138                                   StringRef Op, int Low, int High);
139  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
140    return parsePKHImm(O, "lsl", 0, 31);
141  }
142  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
143    return parsePKHImm(O, "asr", 1, 32);
144  }
145  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
146  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
147  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
148  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
149  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
150  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
151
152  // Asm Match Converter Methods
153  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
154                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
155  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
156                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
157  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
158                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
159  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
160                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
161  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
162                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
163  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
164                             const SmallVectorImpl<MCParsedAsmOperand*> &);
165  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
166                             const SmallVectorImpl<MCParsedAsmOperand*> &);
167  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
168                             const SmallVectorImpl<MCParsedAsmOperand*> &);
169  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
170                             const SmallVectorImpl<MCParsedAsmOperand*> &);
171  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
172                  const SmallVectorImpl<MCParsedAsmOperand*> &);
173  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
174                  const SmallVectorImpl<MCParsedAsmOperand*> &);
175  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
176                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
177  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
178                        const SmallVectorImpl<MCParsedAsmOperand*> &);
179
180  bool validateInstruction(MCInst &Inst,
181                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
182  void processInstruction(MCInst &Inst,
183                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
184  bool shouldOmitCCOutOperand(StringRef Mnemonic,
185                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
186
187public:
188  enum ARMMatchResultTy {
189    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
190    Match_RequiresNotITBlock,
191    Match_RequiresV6,
192    Match_RequiresThumb2
193  };
194
195  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
196    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
197    MCAsmParserExtension::Initialize(_Parser);
198
199    // Initialize the set of available features.
200    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
201
202    // Not in an ITBlock to start with.
203    ITState.CurPosition = ~0U;
204  }
205
206  // Implementation of the MCTargetAsmParser interface:
207  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
208  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
209                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
210  bool ParseDirective(AsmToken DirectiveID);
211
212  unsigned checkTargetMatchPredicate(MCInst &Inst);
213
214  bool MatchAndEmitInstruction(SMLoc IDLoc,
215                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
216                               MCStreamer &Out);
217};
218} // end anonymous namespace
219
220namespace {
221
222/// ARMOperand - Instances of this class represent a parsed ARM machine
223/// instruction.
224class ARMOperand : public MCParsedAsmOperand {
225  enum KindTy {
226    CondCode,
227    CCOut,
228    ITCondMask,
229    CoprocNum,
230    CoprocReg,
231    Immediate,
232    MemBarrierOpt,
233    Memory,
234    PostIndexRegister,
235    MSRMask,
236    ProcIFlags,
237    Register,
238    RegisterList,
239    DPRRegisterList,
240    SPRRegisterList,
241    ShiftedRegister,
242    ShiftedImmediate,
243    ShifterImmediate,
244    RotateImmediate,
245    BitfieldDescriptor,
246    Token
247  } Kind;
248
249  SMLoc StartLoc, EndLoc;
250  SmallVector<unsigned, 8> Registers;
251
252  union {
253    struct {
254      ARMCC::CondCodes Val;
255    } CC;
256
257    struct {
258      unsigned Val;
259    } Cop;
260
261    struct {
262      unsigned Mask:4;
263    } ITMask;
264
265    struct {
266      ARM_MB::MemBOpt Val;
267    } MBOpt;
268
269    struct {
270      ARM_PROC::IFlags Val;
271    } IFlags;
272
273    struct {
274      unsigned Val;
275    } MMask;
276
277    struct {
278      const char *Data;
279      unsigned Length;
280    } Tok;
281
282    struct {
283      unsigned RegNum;
284    } Reg;
285
286    struct {
287      const MCExpr *Val;
288    } Imm;
289
290    /// Combined record for all forms of ARM address expressions.
291    struct {
292      unsigned BaseRegNum;
293      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
294      // was specified.
295      const MCConstantExpr *OffsetImm;  // Offset immediate value
296      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
297      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
298      unsigned ShiftImm;      // shift for OffsetReg.
299      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
300    } Mem;
301
302    struct {
303      unsigned RegNum;
304      bool isAdd;
305      ARM_AM::ShiftOpc ShiftTy;
306      unsigned ShiftImm;
307    } PostIdxReg;
308
309    struct {
310      bool isASR;
311      unsigned Imm;
312    } ShifterImm;
313    struct {
314      ARM_AM::ShiftOpc ShiftTy;
315      unsigned SrcReg;
316      unsigned ShiftReg;
317      unsigned ShiftImm;
318    } RegShiftedReg;
319    struct {
320      ARM_AM::ShiftOpc ShiftTy;
321      unsigned SrcReg;
322      unsigned ShiftImm;
323    } RegShiftedImm;
324    struct {
325      unsigned Imm;
326    } RotImm;
327    struct {
328      unsigned LSB;
329      unsigned Width;
330    } Bitfield;
331  };
332
333  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
334public:
335  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
336    Kind = o.Kind;
337    StartLoc = o.StartLoc;
338    EndLoc = o.EndLoc;
339    switch (Kind) {
340    case CondCode:
341      CC = o.CC;
342      break;
343    case ITCondMask:
344      ITMask = o.ITMask;
345      break;
346    case Token:
347      Tok = o.Tok;
348      break;
349    case CCOut:
350    case Register:
351      Reg = o.Reg;
352      break;
353    case RegisterList:
354    case DPRRegisterList:
355    case SPRRegisterList:
356      Registers = o.Registers;
357      break;
358    case CoprocNum:
359    case CoprocReg:
360      Cop = o.Cop;
361      break;
362    case Immediate:
363      Imm = o.Imm;
364      break;
365    case MemBarrierOpt:
366      MBOpt = o.MBOpt;
367      break;
368    case Memory:
369      Mem = o.Mem;
370      break;
371    case PostIndexRegister:
372      PostIdxReg = o.PostIdxReg;
373      break;
374    case MSRMask:
375      MMask = o.MMask;
376      break;
377    case ProcIFlags:
378      IFlags = o.IFlags;
379      break;
380    case ShifterImmediate:
381      ShifterImm = o.ShifterImm;
382      break;
383    case ShiftedRegister:
384      RegShiftedReg = o.RegShiftedReg;
385      break;
386    case ShiftedImmediate:
387      RegShiftedImm = o.RegShiftedImm;
388      break;
389    case RotateImmediate:
390      RotImm = o.RotImm;
391      break;
392    case BitfieldDescriptor:
393      Bitfield = o.Bitfield;
394      break;
395    }
396  }
397
398  /// getStartLoc - Get the location of the first token of this operand.
399  SMLoc getStartLoc() const { return StartLoc; }
400  /// getEndLoc - Get the location of the last token of this operand.
401  SMLoc getEndLoc() const { return EndLoc; }
402
403  ARMCC::CondCodes getCondCode() const {
404    assert(Kind == CondCode && "Invalid access!");
405    return CC.Val;
406  }
407
408  unsigned getCoproc() const {
409    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
410    return Cop.Val;
411  }
412
413  StringRef getToken() const {
414    assert(Kind == Token && "Invalid access!");
415    return StringRef(Tok.Data, Tok.Length);
416  }
417
418  unsigned getReg() const {
419    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
420    return Reg.RegNum;
421  }
422
423  const SmallVectorImpl<unsigned> &getRegList() const {
424    assert((Kind == RegisterList || Kind == DPRRegisterList ||
425            Kind == SPRRegisterList) && "Invalid access!");
426    return Registers;
427  }
428
429  const MCExpr *getImm() const {
430    assert(Kind == Immediate && "Invalid access!");
431    return Imm.Val;
432  }
433
434  ARM_MB::MemBOpt getMemBarrierOpt() const {
435    assert(Kind == MemBarrierOpt && "Invalid access!");
436    return MBOpt.Val;
437  }
438
439  ARM_PROC::IFlags getProcIFlags() const {
440    assert(Kind == ProcIFlags && "Invalid access!");
441    return IFlags.Val;
442  }
443
444  unsigned getMSRMask() const {
445    assert(Kind == MSRMask && "Invalid access!");
446    return MMask.Val;
447  }
448
449  bool isCoprocNum() const { return Kind == CoprocNum; }
450  bool isCoprocReg() const { return Kind == CoprocReg; }
451  bool isCondCode() const { return Kind == CondCode; }
452  bool isCCOut() const { return Kind == CCOut; }
453  bool isITMask() const { return Kind == ITCondMask; }
454  bool isITCondCode() const { return Kind == CondCode; }
455  bool isImm() const { return Kind == Immediate; }
456  bool isImm0_1020s4() const {
457    if (Kind != Immediate)
458      return false;
459    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
460    if (!CE) return false;
461    int64_t Value = CE->getValue();
462    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
463  }
464  bool isImm0_508s4() const {
465    if (Kind != Immediate)
466      return false;
467    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
468    if (!CE) return false;
469    int64_t Value = CE->getValue();
470    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
471  }
472  bool isImm0_255() const {
473    if (Kind != Immediate)
474      return false;
475    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
476    if (!CE) return false;
477    int64_t Value = CE->getValue();
478    return Value >= 0 && Value < 256;
479  }
480  bool isImm0_7() const {
481    if (Kind != Immediate)
482      return false;
483    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
484    if (!CE) return false;
485    int64_t Value = CE->getValue();
486    return Value >= 0 && Value < 8;
487  }
488  bool isImm0_15() const {
489    if (Kind != Immediate)
490      return false;
491    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
492    if (!CE) return false;
493    int64_t Value = CE->getValue();
494    return Value >= 0 && Value < 16;
495  }
496  bool isImm0_31() const {
497    if (Kind != Immediate)
498      return false;
499    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
500    if (!CE) return false;
501    int64_t Value = CE->getValue();
502    return Value >= 0 && Value < 32;
503  }
504  bool isImm1_16() const {
505    if (Kind != Immediate)
506      return false;
507    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
508    if (!CE) return false;
509    int64_t Value = CE->getValue();
510    return Value > 0 && Value < 17;
511  }
512  bool isImm1_32() const {
513    if (Kind != Immediate)
514      return false;
515    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
516    if (!CE) return false;
517    int64_t Value = CE->getValue();
518    return Value > 0 && Value < 33;
519  }
520  bool isImm0_65535() const {
521    if (Kind != Immediate)
522      return false;
523    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
524    if (!CE) return false;
525    int64_t Value = CE->getValue();
526    return Value >= 0 && Value < 65536;
527  }
528  bool isImm0_65535Expr() const {
529    if (Kind != Immediate)
530      return false;
531    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
532    // If it's not a constant expression, it'll generate a fixup and be
533    // handled later.
534    if (!CE) return true;
535    int64_t Value = CE->getValue();
536    return Value >= 0 && Value < 65536;
537  }
538  bool isImm24bit() const {
539    if (Kind != Immediate)
540      return false;
541    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
542    if (!CE) return false;
543    int64_t Value = CE->getValue();
544    return Value >= 0 && Value <= 0xffffff;
545  }
546  bool isImmThumbSR() const {
547    if (Kind != Immediate)
548      return false;
549    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
550    if (!CE) return false;
551    int64_t Value = CE->getValue();
552    return Value > 0 && Value < 33;
553  }
554  bool isPKHLSLImm() const {
555    if (Kind != Immediate)
556      return false;
557    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
558    if (!CE) return false;
559    int64_t Value = CE->getValue();
560    return Value >= 0 && Value < 32;
561  }
562  bool isPKHASRImm() const {
563    if (Kind != Immediate)
564      return false;
565    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
566    if (!CE) return false;
567    int64_t Value = CE->getValue();
568    return Value > 0 && Value <= 32;
569  }
570  bool isARMSOImm() const {
571    if (Kind != Immediate)
572      return false;
573    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
574    if (!CE) return false;
575    int64_t Value = CE->getValue();
576    return ARM_AM::getSOImmVal(Value) != -1;
577  }
578  bool isT2SOImm() const {
579    if (Kind != Immediate)
580      return false;
581    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
582    if (!CE) return false;
583    int64_t Value = CE->getValue();
584    return ARM_AM::getT2SOImmVal(Value) != -1;
585  }
586  bool isSetEndImm() const {
587    if (Kind != Immediate)
588      return false;
589    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
590    if (!CE) return false;
591    int64_t Value = CE->getValue();
592    return Value == 1 || Value == 0;
593  }
594  bool isReg() const { return Kind == Register; }
595  bool isRegList() const { return Kind == RegisterList; }
596  bool isDPRRegList() const { return Kind == DPRRegisterList; }
597  bool isSPRRegList() const { return Kind == SPRRegisterList; }
598  bool isToken() const { return Kind == Token; }
599  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
600  bool isMemory() const { return Kind == Memory; }
601  bool isShifterImm() const { return Kind == ShifterImmediate; }
602  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
603  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
604  bool isRotImm() const { return Kind == RotateImmediate; }
605  bool isBitfield() const { return Kind == BitfieldDescriptor; }
606  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
607  bool isPostIdxReg() const {
608    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
609  }
610  bool isMemNoOffset() const {
611    if (Kind != Memory)
612      return false;
613    // No offset of any kind.
614    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
615  }
616  bool isAddrMode2() const {
617    if (Kind != Memory)
618      return false;
619    // Check for register offset.
620    if (Mem.OffsetRegNum) return true;
621    // Immediate offset in range [-4095, 4095].
622    if (!Mem.OffsetImm) return true;
623    int64_t Val = Mem.OffsetImm->getValue();
624    return Val > -4096 && Val < 4096;
625  }
626  bool isAM2OffsetImm() const {
627    if (Kind != Immediate)
628      return false;
629    // Immediate offset in range [-4095, 4095].
630    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
631    if (!CE) return false;
632    int64_t Val = CE->getValue();
633    return Val > -4096 && Val < 4096;
634  }
635  bool isAddrMode3() const {
636    if (Kind != Memory)
637      return false;
638    // No shifts are legal for AM3.
639    if (Mem.ShiftType != ARM_AM::no_shift) return false;
640    // Check for register offset.
641    if (Mem.OffsetRegNum) return true;
642    // Immediate offset in range [-255, 255].
643    if (!Mem.OffsetImm) return true;
644    int64_t Val = Mem.OffsetImm->getValue();
645    return Val > -256 && Val < 256;
646  }
647  bool isAM3Offset() const {
648    if (Kind != Immediate && Kind != PostIndexRegister)
649      return false;
650    if (Kind == PostIndexRegister)
651      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
652    // Immediate offset in range [-255, 255].
653    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
654    if (!CE) return false;
655    int64_t Val = CE->getValue();
656    // Special case, #-0 is INT32_MIN.
657    return (Val > -256 && Val < 256) || Val == INT32_MIN;
658  }
659  bool isAddrMode5() const {
660    if (Kind != Memory)
661      return false;
662    // Check for register offset.
663    if (Mem.OffsetRegNum) return false;
664    // Immediate offset in range [-1020, 1020] and a multiple of 4.
665    if (!Mem.OffsetImm) return true;
666    int64_t Val = Mem.OffsetImm->getValue();
667    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
668           Val == INT32_MIN;
669  }
670  bool isMemRegOffset() const {
671    if (Kind != Memory || !Mem.OffsetRegNum)
672      return false;
673    return true;
674  }
675  bool isMemThumbRR() const {
676    // Thumb reg+reg addressing is simple. Just two registers, a base and
677    // an offset. No shifts, negations or any other complicating factors.
678    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
679        Mem.ShiftType != ARM_AM::no_shift)
680      return false;
681    return isARMLowRegister(Mem.BaseRegNum) &&
682      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
683  }
684  bool isMemThumbRIs4() const {
685    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
686        !isARMLowRegister(Mem.BaseRegNum))
687      return false;
688    // Immediate offset, multiple of 4 in range [0, 124].
689    if (!Mem.OffsetImm) return true;
690    int64_t Val = Mem.OffsetImm->getValue();
691    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
692  }
693  bool isMemThumbRIs2() const {
694    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
695        !isARMLowRegister(Mem.BaseRegNum))
696      return false;
697    // Immediate offset, multiple of 4 in range [0, 62].
698    if (!Mem.OffsetImm) return true;
699    int64_t Val = Mem.OffsetImm->getValue();
700    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
701  }
702  bool isMemThumbRIs1() const {
703    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
704        !isARMLowRegister(Mem.BaseRegNum))
705      return false;
706    // Immediate offset in range [0, 31].
707    if (!Mem.OffsetImm) return true;
708    int64_t Val = Mem.OffsetImm->getValue();
709    return Val >= 0 && Val <= 31;
710  }
711  bool isMemThumbSPI() const {
712    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
713      return false;
714    // Immediate offset, multiple of 4 in range [0, 1020].
715    if (!Mem.OffsetImm) return true;
716    int64_t Val = Mem.OffsetImm->getValue();
717    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
718  }
719  bool isMemImm8Offset() const {
720    if (Kind != Memory || Mem.OffsetRegNum != 0)
721      return false;
722    // Immediate offset in range [-255, 255].
723    if (!Mem.OffsetImm) return true;
724    int64_t Val = Mem.OffsetImm->getValue();
725    return Val > -256 && Val < 256;
726  }
727  bool isMemImm12Offset() const {
728    // If we have an immediate that's not a constant, treat it as a label
729    // reference needing a fixup. If it is a constant, it's something else
730    // and we reject it.
731    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
732      return true;
733
734    if (Kind != Memory || Mem.OffsetRegNum != 0)
735      return false;
736    // Immediate offset in range [-4095, 4095].
737    if (!Mem.OffsetImm) return true;
738    int64_t Val = Mem.OffsetImm->getValue();
739    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
740  }
741  bool isPostIdxImm8() const {
742    if (Kind != Immediate)
743      return false;
744    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
745    if (!CE) return false;
746    int64_t Val = CE->getValue();
747    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
748  }
749
750  bool isMSRMask() const { return Kind == MSRMask; }
751  bool isProcIFlags() const { return Kind == ProcIFlags; }
752
753  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
754    // Add as immediates when possible.  Null MCExpr = 0.
755    if (Expr == 0)
756      Inst.addOperand(MCOperand::CreateImm(0));
757    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
758      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
759    else
760      Inst.addOperand(MCOperand::CreateExpr(Expr));
761  }
762
763  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
764    assert(N == 2 && "Invalid number of operands!");
765    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
766    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
767    Inst.addOperand(MCOperand::CreateReg(RegNum));
768  }
769
770  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
771    assert(N == 1 && "Invalid number of operands!");
772    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
773  }
774
775  void addITMaskOperands(MCInst &Inst, unsigned N) const {
776    assert(N == 1 && "Invalid number of operands!");
777    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
778  }
779
780  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
781    assert(N == 1 && "Invalid number of operands!");
782    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
783  }
784
785  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
786    assert(N == 1 && "Invalid number of operands!");
787    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
788  }
789
790  void addCCOutOperands(MCInst &Inst, unsigned N) const {
791    assert(N == 1 && "Invalid number of operands!");
792    Inst.addOperand(MCOperand::CreateReg(getReg()));
793  }
794
795  void addRegOperands(MCInst &Inst, unsigned N) const {
796    assert(N == 1 && "Invalid number of operands!");
797    Inst.addOperand(MCOperand::CreateReg(getReg()));
798  }
799
800  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
801    assert(N == 3 && "Invalid number of operands!");
802    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
803    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
804    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
805    Inst.addOperand(MCOperand::CreateImm(
806      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
807  }
808
809  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
810    assert(N == 2 && "Invalid number of operands!");
811    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
812    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
813    Inst.addOperand(MCOperand::CreateImm(
814      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
815  }
816
817
818  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
819    assert(N == 1 && "Invalid number of operands!");
820    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
821                                         ShifterImm.Imm));
822  }
823
824  void addRegListOperands(MCInst &Inst, unsigned N) const {
825    assert(N == 1 && "Invalid number of operands!");
826    const SmallVectorImpl<unsigned> &RegList = getRegList();
827    for (SmallVectorImpl<unsigned>::const_iterator
828           I = RegList.begin(), E = RegList.end(); I != E; ++I)
829      Inst.addOperand(MCOperand::CreateReg(*I));
830  }
831
832  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
833    addRegListOperands(Inst, N);
834  }
835
836  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
837    addRegListOperands(Inst, N);
838  }
839
840  void addRotImmOperands(MCInst &Inst, unsigned N) const {
841    assert(N == 1 && "Invalid number of operands!");
842    // Encoded as val>>3. The printer handles display as 8, 16, 24.
843    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
844  }
845
846  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
847    assert(N == 1 && "Invalid number of operands!");
848    // Munge the lsb/width into a bitfield mask.
849    unsigned lsb = Bitfield.LSB;
850    unsigned width = Bitfield.Width;
851    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
852    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
853                      (32 - (lsb + width)));
854    Inst.addOperand(MCOperand::CreateImm(Mask));
855  }
856
857  void addImmOperands(MCInst &Inst, unsigned N) const {
858    assert(N == 1 && "Invalid number of operands!");
859    addExpr(Inst, getImm());
860  }
861
862  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
863    assert(N == 1 && "Invalid number of operands!");
864    // The immediate is scaled by four in the encoding and is stored
865    // in the MCInst as such. Lop off the low two bits here.
866    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
867    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
868  }
869
870  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
871    assert(N == 1 && "Invalid number of operands!");
872    // The immediate is scaled by four in the encoding and is stored
873    // in the MCInst as such. Lop off the low two bits here.
874    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
875    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
876  }
877
878  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
879    assert(N == 1 && "Invalid number of operands!");
880    addExpr(Inst, getImm());
881  }
882
883  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
884    assert(N == 1 && "Invalid number of operands!");
885    addExpr(Inst, getImm());
886  }
887
888  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
889    assert(N == 1 && "Invalid number of operands!");
890    addExpr(Inst, getImm());
891  }
892
893  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
894    assert(N == 1 && "Invalid number of operands!");
895    addExpr(Inst, getImm());
896  }
897
898  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
899    assert(N == 1 && "Invalid number of operands!");
900    // The constant encodes as the immediate-1, and we store in the instruction
901    // the bits as encoded, so subtract off one here.
902    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
903    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
904  }
905
906  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
907    assert(N == 1 && "Invalid number of operands!");
908    // The constant encodes as the immediate-1, and we store in the instruction
909    // the bits as encoded, so subtract off one here.
910    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
911    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
912  }
913
914  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
915    assert(N == 1 && "Invalid number of operands!");
916    addExpr(Inst, getImm());
917  }
918
919  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
920    assert(N == 1 && "Invalid number of operands!");
921    addExpr(Inst, getImm());
922  }
923
924  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
925    assert(N == 1 && "Invalid number of operands!");
926    addExpr(Inst, getImm());
927  }
928
929  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
930    assert(N == 1 && "Invalid number of operands!");
931    // The constant encodes as the immediate, except for 32, which encodes as
932    // zero.
933    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934    unsigned Imm = CE->getValue();
935    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
936  }
937
938  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
939    assert(N == 1 && "Invalid number of operands!");
940    addExpr(Inst, getImm());
941  }
942
943  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
944    assert(N == 1 && "Invalid number of operands!");
945    // An ASR value of 32 encodes as 0, so that's how we want to add it to
946    // the instruction as well.
947    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948    int Val = CE->getValue();
949    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
950  }
951
952  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
953    assert(N == 1 && "Invalid number of operands!");
954    addExpr(Inst, getImm());
955  }
956
957  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
958    assert(N == 1 && "Invalid number of operands!");
959    addExpr(Inst, getImm());
960  }
961
962  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
963    assert(N == 1 && "Invalid number of operands!");
964    addExpr(Inst, getImm());
965  }
966
967  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
968    assert(N == 1 && "Invalid number of operands!");
969    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
970  }
971
972  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
973    assert(N == 1 && "Invalid number of operands!");
974    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
975  }
976
977  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
978    assert(N == 3 && "Invalid number of operands!");
979    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
980    if (!Mem.OffsetRegNum) {
981      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
982      // Special case for #-0
983      if (Val == INT32_MIN) Val = 0;
984      if (Val < 0) Val = -Val;
985      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
986    } else {
987      // For register offset, we encode the shift type and negation flag
988      // here.
989      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
990                              Mem.ShiftImm, Mem.ShiftType);
991    }
992    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
993    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
994    Inst.addOperand(MCOperand::CreateImm(Val));
995  }
996
997  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
998    assert(N == 2 && "Invalid number of operands!");
999    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1000    assert(CE && "non-constant AM2OffsetImm operand!");
1001    int32_t Val = CE->getValue();
1002    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1003    // Special case for #-0
1004    if (Val == INT32_MIN) Val = 0;
1005    if (Val < 0) Val = -Val;
1006    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1007    Inst.addOperand(MCOperand::CreateReg(0));
1008    Inst.addOperand(MCOperand::CreateImm(Val));
1009  }
1010
1011  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1012    assert(N == 3 && "Invalid number of operands!");
1013    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1014    if (!Mem.OffsetRegNum) {
1015      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1016      // Special case for #-0
1017      if (Val == INT32_MIN) Val = 0;
1018      if (Val < 0) Val = -Val;
1019      Val = ARM_AM::getAM3Opc(AddSub, Val);
1020    } else {
1021      // For register offset, we encode the shift type and negation flag
1022      // here.
1023      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1024    }
1025    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1026    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1027    Inst.addOperand(MCOperand::CreateImm(Val));
1028  }
1029
1030  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1031    assert(N == 2 && "Invalid number of operands!");
1032    if (Kind == PostIndexRegister) {
1033      int32_t Val =
1034        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1035      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1036      Inst.addOperand(MCOperand::CreateImm(Val));
1037      return;
1038    }
1039
1040    // Constant offset.
1041    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1042    int32_t Val = CE->getValue();
1043    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1044    // Special case for #-0
1045    if (Val == INT32_MIN) Val = 0;
1046    if (Val < 0) Val = -Val;
1047    Val = ARM_AM::getAM3Opc(AddSub, Val);
1048    Inst.addOperand(MCOperand::CreateReg(0));
1049    Inst.addOperand(MCOperand::CreateImm(Val));
1050  }
1051
1052  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1053    assert(N == 2 && "Invalid number of operands!");
1054    // The lower two bits are always zero and as such are not encoded.
1055    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1056    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1057    // Special case for #-0
1058    if (Val == INT32_MIN) Val = 0;
1059    if (Val < 0) Val = -Val;
1060    Val = ARM_AM::getAM5Opc(AddSub, Val);
1061    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1062    Inst.addOperand(MCOperand::CreateImm(Val));
1063  }
1064
1065  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1066    assert(N == 2 && "Invalid number of operands!");
1067    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1068    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1069    Inst.addOperand(MCOperand::CreateImm(Val));
1070  }
1071
1072  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1073    assert(N == 2 && "Invalid number of operands!");
1074    // If this is an immediate, it's a label reference.
1075    if (Kind == Immediate) {
1076      addExpr(Inst, getImm());
1077      Inst.addOperand(MCOperand::CreateImm(0));
1078      return;
1079    }
1080
1081    // Otherwise, it's a normal memory reg+offset.
1082    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1083    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1084    Inst.addOperand(MCOperand::CreateImm(Val));
1085  }
1086
1087  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1088    assert(N == 3 && "Invalid number of operands!");
1089    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1090                                     Mem.ShiftImm, Mem.ShiftType);
1091    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1092    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1093    Inst.addOperand(MCOperand::CreateImm(Val));
1094  }
1095
1096  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1097    assert(N == 2 && "Invalid number of operands!");
1098    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1099    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1100  }
1101
1102  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1103    assert(N == 2 && "Invalid number of operands!");
1104    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1105    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1106    Inst.addOperand(MCOperand::CreateImm(Val));
1107  }
1108
1109  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1110    assert(N == 2 && "Invalid number of operands!");
1111    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1112    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1113    Inst.addOperand(MCOperand::CreateImm(Val));
1114  }
1115
1116  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1117    assert(N == 2 && "Invalid number of operands!");
1118    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1119    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1120    Inst.addOperand(MCOperand::CreateImm(Val));
1121  }
1122
1123  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1124    assert(N == 2 && "Invalid number of operands!");
1125    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1126    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1127    Inst.addOperand(MCOperand::CreateImm(Val));
1128  }
1129
1130  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1131    assert(N == 1 && "Invalid number of operands!");
1132    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1133    assert(CE && "non-constant post-idx-imm8 operand!");
1134    int Imm = CE->getValue();
1135    bool isAdd = Imm >= 0;
1136    if (Imm == INT32_MIN) Imm = 0;
1137    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1138    Inst.addOperand(MCOperand::CreateImm(Imm));
1139  }
1140
1141  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1142    assert(N == 2 && "Invalid number of operands!");
1143    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1144    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1145  }
1146
1147  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1148    assert(N == 2 && "Invalid number of operands!");
1149    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1150    // The sign, shift type, and shift amount are encoded in a single operand
1151    // using the AM2 encoding helpers.
1152    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1153    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1154                                     PostIdxReg.ShiftTy);
1155    Inst.addOperand(MCOperand::CreateImm(Imm));
1156  }
1157
1158  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1159    assert(N == 1 && "Invalid number of operands!");
1160    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1161  }
1162
1163  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1164    assert(N == 1 && "Invalid number of operands!");
1165    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1166  }
1167
1168  virtual void print(raw_ostream &OS) const;
1169
1170  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1171    ARMOperand *Op = new ARMOperand(ITCondMask);
1172    Op->ITMask.Mask = Mask;
1173    Op->StartLoc = S;
1174    Op->EndLoc = S;
1175    return Op;
1176  }
1177
1178  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1179    ARMOperand *Op = new ARMOperand(CondCode);
1180    Op->CC.Val = CC;
1181    Op->StartLoc = S;
1182    Op->EndLoc = S;
1183    return Op;
1184  }
1185
1186  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1187    ARMOperand *Op = new ARMOperand(CoprocNum);
1188    Op->Cop.Val = CopVal;
1189    Op->StartLoc = S;
1190    Op->EndLoc = S;
1191    return Op;
1192  }
1193
1194  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1195    ARMOperand *Op = new ARMOperand(CoprocReg);
1196    Op->Cop.Val = CopVal;
1197    Op->StartLoc = S;
1198    Op->EndLoc = S;
1199    return Op;
1200  }
1201
1202  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1203    ARMOperand *Op = new ARMOperand(CCOut);
1204    Op->Reg.RegNum = RegNum;
1205    Op->StartLoc = S;
1206    Op->EndLoc = S;
1207    return Op;
1208  }
1209
1210  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1211    ARMOperand *Op = new ARMOperand(Token);
1212    Op->Tok.Data = Str.data();
1213    Op->Tok.Length = Str.size();
1214    Op->StartLoc = S;
1215    Op->EndLoc = S;
1216    return Op;
1217  }
1218
1219  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1220    ARMOperand *Op = new ARMOperand(Register);
1221    Op->Reg.RegNum = RegNum;
1222    Op->StartLoc = S;
1223    Op->EndLoc = E;
1224    return Op;
1225  }
1226
1227  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1228                                           unsigned SrcReg,
1229                                           unsigned ShiftReg,
1230                                           unsigned ShiftImm,
1231                                           SMLoc S, SMLoc E) {
1232    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1233    Op->RegShiftedReg.ShiftTy = ShTy;
1234    Op->RegShiftedReg.SrcReg = SrcReg;
1235    Op->RegShiftedReg.ShiftReg = ShiftReg;
1236    Op->RegShiftedReg.ShiftImm = ShiftImm;
1237    Op->StartLoc = S;
1238    Op->EndLoc = E;
1239    return Op;
1240  }
1241
1242  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1243                                            unsigned SrcReg,
1244                                            unsigned ShiftImm,
1245                                            SMLoc S, SMLoc E) {
1246    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1247    Op->RegShiftedImm.ShiftTy = ShTy;
1248    Op->RegShiftedImm.SrcReg = SrcReg;
1249    Op->RegShiftedImm.ShiftImm = ShiftImm;
1250    Op->StartLoc = S;
1251    Op->EndLoc = E;
1252    return Op;
1253  }
1254
1255  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1256                                   SMLoc S, SMLoc E) {
1257    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1258    Op->ShifterImm.isASR = isASR;
1259    Op->ShifterImm.Imm = Imm;
1260    Op->StartLoc = S;
1261    Op->EndLoc = E;
1262    return Op;
1263  }
1264
1265  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1266    ARMOperand *Op = new ARMOperand(RotateImmediate);
1267    Op->RotImm.Imm = Imm;
1268    Op->StartLoc = S;
1269    Op->EndLoc = E;
1270    return Op;
1271  }
1272
1273  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1274                                    SMLoc S, SMLoc E) {
1275    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1276    Op->Bitfield.LSB = LSB;
1277    Op->Bitfield.Width = Width;
1278    Op->StartLoc = S;
1279    Op->EndLoc = E;
1280    return Op;
1281  }
1282
1283  static ARMOperand *
1284  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1285                SMLoc StartLoc, SMLoc EndLoc) {
1286    KindTy Kind = RegisterList;
1287
1288    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1289        contains(Regs.front().first))
1290      Kind = DPRRegisterList;
1291    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1292             contains(Regs.front().first))
1293      Kind = SPRRegisterList;
1294
1295    ARMOperand *Op = new ARMOperand(Kind);
1296    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1297           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1298      Op->Registers.push_back(I->first);
1299    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1300    Op->StartLoc = StartLoc;
1301    Op->EndLoc = EndLoc;
1302    return Op;
1303  }
1304
1305  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1306    ARMOperand *Op = new ARMOperand(Immediate);
1307    Op->Imm.Val = Val;
1308    Op->StartLoc = S;
1309    Op->EndLoc = E;
1310    return Op;
1311  }
1312
1313  static ARMOperand *CreateMem(unsigned BaseRegNum,
1314                               const MCConstantExpr *OffsetImm,
1315                               unsigned OffsetRegNum,
1316                               ARM_AM::ShiftOpc ShiftType,
1317                               unsigned ShiftImm,
1318                               bool isNegative,
1319                               SMLoc S, SMLoc E) {
1320    ARMOperand *Op = new ARMOperand(Memory);
1321    Op->Mem.BaseRegNum = BaseRegNum;
1322    Op->Mem.OffsetImm = OffsetImm;
1323    Op->Mem.OffsetRegNum = OffsetRegNum;
1324    Op->Mem.ShiftType = ShiftType;
1325    Op->Mem.ShiftImm = ShiftImm;
1326    Op->Mem.isNegative = isNegative;
1327    Op->StartLoc = S;
1328    Op->EndLoc = E;
1329    return Op;
1330  }
1331
1332  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1333                                      ARM_AM::ShiftOpc ShiftTy,
1334                                      unsigned ShiftImm,
1335                                      SMLoc S, SMLoc E) {
1336    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1337    Op->PostIdxReg.RegNum = RegNum;
1338    Op->PostIdxReg.isAdd = isAdd;
1339    Op->PostIdxReg.ShiftTy = ShiftTy;
1340    Op->PostIdxReg.ShiftImm = ShiftImm;
1341    Op->StartLoc = S;
1342    Op->EndLoc = E;
1343    return Op;
1344  }
1345
1346  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1347    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1348    Op->MBOpt.Val = Opt;
1349    Op->StartLoc = S;
1350    Op->EndLoc = S;
1351    return Op;
1352  }
1353
1354  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1355    ARMOperand *Op = new ARMOperand(ProcIFlags);
1356    Op->IFlags.Val = IFlags;
1357    Op->StartLoc = S;
1358    Op->EndLoc = S;
1359    return Op;
1360  }
1361
1362  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1363    ARMOperand *Op = new ARMOperand(MSRMask);
1364    Op->MMask.Val = MMask;
1365    Op->StartLoc = S;
1366    Op->EndLoc = S;
1367    return Op;
1368  }
1369};
1370
1371} // end anonymous namespace.
1372
1373void ARMOperand::print(raw_ostream &OS) const {
1374  switch (Kind) {
1375  case CondCode:
1376    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1377    break;
1378  case CCOut:
1379    OS << "<ccout " << getReg() << ">";
1380    break;
1381  case ITCondMask: {
1382    static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1383      "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1384      "(tee)", "(eee)" };
1385    assert((ITMask.Mask & 0xf) == ITMask.Mask);
1386    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1387    break;
1388  }
1389  case CoprocNum:
1390    OS << "<coprocessor number: " << getCoproc() << ">";
1391    break;
1392  case CoprocReg:
1393    OS << "<coprocessor register: " << getCoproc() << ">";
1394    break;
1395  case MSRMask:
1396    OS << "<mask: " << getMSRMask() << ">";
1397    break;
1398  case Immediate:
1399    getImm()->print(OS);
1400    break;
1401  case MemBarrierOpt:
1402    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1403    break;
1404  case Memory:
1405    OS << "<memory "
1406       << " base:" << Mem.BaseRegNum;
1407    OS << ">";
1408    break;
1409  case PostIndexRegister:
1410    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1411       << PostIdxReg.RegNum;
1412    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1413      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1414         << PostIdxReg.ShiftImm;
1415    OS << ">";
1416    break;
1417  case ProcIFlags: {
1418    OS << "<ARM_PROC::";
1419    unsigned IFlags = getProcIFlags();
1420    for (int i=2; i >= 0; --i)
1421      if (IFlags & (1 << i))
1422        OS << ARM_PROC::IFlagsToString(1 << i);
1423    OS << ">";
1424    break;
1425  }
1426  case Register:
1427    OS << "<register " << getReg() << ">";
1428    break;
1429  case ShifterImmediate:
1430    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1431       << " #" << ShifterImm.Imm << ">";
1432    break;
1433  case ShiftedRegister:
1434    OS << "<so_reg_reg "
1435       << RegShiftedReg.SrcReg
1436       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1437       << ", " << RegShiftedReg.ShiftReg << ", "
1438       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1439       << ">";
1440    break;
1441  case ShiftedImmediate:
1442    OS << "<so_reg_imm "
1443       << RegShiftedImm.SrcReg
1444       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1445       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1446       << ">";
1447    break;
1448  case RotateImmediate:
1449    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1450    break;
1451  case BitfieldDescriptor:
1452    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1453       << ", width: " << Bitfield.Width << ">";
1454    break;
1455  case RegisterList:
1456  case DPRRegisterList:
1457  case SPRRegisterList: {
1458    OS << "<register_list ";
1459
1460    const SmallVectorImpl<unsigned> &RegList = getRegList();
1461    for (SmallVectorImpl<unsigned>::const_iterator
1462           I = RegList.begin(), E = RegList.end(); I != E; ) {
1463      OS << *I;
1464      if (++I < E) OS << ", ";
1465    }
1466
1467    OS << ">";
1468    break;
1469  }
1470  case Token:
1471    OS << "'" << getToken() << "'";
1472    break;
1473  }
1474}
1475
1476/// @name Auto-generated Match Functions
1477/// {
1478
1479static unsigned MatchRegisterName(StringRef Name);
1480
1481/// }
1482
1483bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1484                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1485  RegNo = tryParseRegister();
1486
1487  return (RegNo == (unsigned)-1);
1488}
1489
1490/// Try to parse a register name.  The token must be an Identifier when called,
1491/// and if it is a register name the token is eaten and the register number is
1492/// returned.  Otherwise return -1.
1493///
1494int ARMAsmParser::tryParseRegister() {
1495  const AsmToken &Tok = Parser.getTok();
1496  if (Tok.isNot(AsmToken::Identifier)) return -1;
1497
1498  // FIXME: Validate register for the current architecture; we have to do
1499  // validation later, so maybe there is no need for this here.
1500  std::string upperCase = Tok.getString().str();
1501  std::string lowerCase = LowercaseString(upperCase);
1502  unsigned RegNum = MatchRegisterName(lowerCase);
1503  if (!RegNum) {
1504    RegNum = StringSwitch<unsigned>(lowerCase)
1505      .Case("r13", ARM::SP)
1506      .Case("r14", ARM::LR)
1507      .Case("r15", ARM::PC)
1508      .Case("ip", ARM::R12)
1509      .Default(0);
1510  }
1511  if (!RegNum) return -1;
1512
1513  Parser.Lex(); // Eat identifier token.
1514  return RegNum;
1515}
1516
1517// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1518// If a recoverable error occurs, return 1. If an irrecoverable error
1519// occurs, return -1. An irrecoverable error is one where tokens have been
1520// consumed in the process of trying to parse the shifter (i.e., when it is
1521// indeed a shifter operand, but malformed).
1522int ARMAsmParser::tryParseShiftRegister(
1523                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1524  SMLoc S = Parser.getTok().getLoc();
1525  const AsmToken &Tok = Parser.getTok();
1526  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1527
1528  std::string upperCase = Tok.getString().str();
1529  std::string lowerCase = LowercaseString(upperCase);
1530  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1531      .Case("lsl", ARM_AM::lsl)
1532      .Case("lsr", ARM_AM::lsr)
1533      .Case("asr", ARM_AM::asr)
1534      .Case("ror", ARM_AM::ror)
1535      .Case("rrx", ARM_AM::rrx)
1536      .Default(ARM_AM::no_shift);
1537
1538  if (ShiftTy == ARM_AM::no_shift)
1539    return 1;
1540
1541  Parser.Lex(); // Eat the operator.
1542
1543  // The source register for the shift has already been added to the
1544  // operand list, so we need to pop it off and combine it into the shifted
1545  // register operand instead.
1546  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1547  if (!PrevOp->isReg())
1548    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1549  int SrcReg = PrevOp->getReg();
1550  int64_t Imm = 0;
1551  int ShiftReg = 0;
1552  if (ShiftTy == ARM_AM::rrx) {
1553    // RRX Doesn't have an explicit shift amount. The encoder expects
1554    // the shift register to be the same as the source register. Seems odd,
1555    // but OK.
1556    ShiftReg = SrcReg;
1557  } else {
1558    // Figure out if this is shifted by a constant or a register (for non-RRX).
1559    if (Parser.getTok().is(AsmToken::Hash)) {
1560      Parser.Lex(); // Eat hash.
1561      SMLoc ImmLoc = Parser.getTok().getLoc();
1562      const MCExpr *ShiftExpr = 0;
1563      if (getParser().ParseExpression(ShiftExpr)) {
1564        Error(ImmLoc, "invalid immediate shift value");
1565        return -1;
1566      }
1567      // The expression must be evaluatable as an immediate.
1568      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1569      if (!CE) {
1570        Error(ImmLoc, "invalid immediate shift value");
1571        return -1;
1572      }
1573      // Range check the immediate.
1574      // lsl, ror: 0 <= imm <= 31
1575      // lsr, asr: 0 <= imm <= 32
1576      Imm = CE->getValue();
1577      if (Imm < 0 ||
1578          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1579          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1580        Error(ImmLoc, "immediate shift value out of range");
1581        return -1;
1582      }
1583    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1584      ShiftReg = tryParseRegister();
1585      SMLoc L = Parser.getTok().getLoc();
1586      if (ShiftReg == -1) {
1587        Error (L, "expected immediate or register in shift operand");
1588        return -1;
1589      }
1590    } else {
1591      Error (Parser.getTok().getLoc(),
1592                    "expected immediate or register in shift operand");
1593      return -1;
1594    }
1595  }
1596
1597  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1598    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1599                                                         ShiftReg, Imm,
1600                                               S, Parser.getTok().getLoc()));
1601  else
1602    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1603                                               S, Parser.getTok().getLoc()));
1604
1605  return 0;
1606}
1607
1608
1609/// Try to parse a register name.  The token must be an Identifier when called.
1610/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1611/// if there is a "writeback". 'true' if it's not a register.
1612///
1613/// TODO this is likely to change to allow different register types and or to
1614/// parse for a specific register type.
1615bool ARMAsmParser::
1616tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1617  SMLoc S = Parser.getTok().getLoc();
1618  int RegNo = tryParseRegister();
1619  if (RegNo == -1)
1620    return true;
1621
1622  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1623
1624  const AsmToken &ExclaimTok = Parser.getTok();
1625  if (ExclaimTok.is(AsmToken::Exclaim)) {
1626    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1627                                               ExclaimTok.getLoc()));
1628    Parser.Lex(); // Eat exclaim token
1629  }
1630
1631  return false;
1632}
1633
1634/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1635/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1636/// "c5", ...
1637static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1638  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1639  // but efficient.
1640  switch (Name.size()) {
1641  default: break;
1642  case 2:
1643    if (Name[0] != CoprocOp)
1644      return -1;
1645    switch (Name[1]) {
1646    default:  return -1;
1647    case '0': return 0;
1648    case '1': return 1;
1649    case '2': return 2;
1650    case '3': return 3;
1651    case '4': return 4;
1652    case '5': return 5;
1653    case '6': return 6;
1654    case '7': return 7;
1655    case '8': return 8;
1656    case '9': return 9;
1657    }
1658    break;
1659  case 3:
1660    if (Name[0] != CoprocOp || Name[1] != '1')
1661      return -1;
1662    switch (Name[2]) {
1663    default:  return -1;
1664    case '0': return 10;
1665    case '1': return 11;
1666    case '2': return 12;
1667    case '3': return 13;
1668    case '4': return 14;
1669    case '5': return 15;
1670    }
1671    break;
1672  }
1673
1674  return -1;
1675}
1676
1677/// parseITCondCode - Try to parse a condition code for an IT instruction.
1678ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1679parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1680  SMLoc S = Parser.getTok().getLoc();
1681  const AsmToken &Tok = Parser.getTok();
1682  if (!Tok.is(AsmToken::Identifier))
1683    return MatchOperand_NoMatch;
1684  unsigned CC = StringSwitch<unsigned>(Tok.getString())
1685    .Case("eq", ARMCC::EQ)
1686    .Case("ne", ARMCC::NE)
1687    .Case("hs", ARMCC::HS)
1688    .Case("cs", ARMCC::HS)
1689    .Case("lo", ARMCC::LO)
1690    .Case("cc", ARMCC::LO)
1691    .Case("mi", ARMCC::MI)
1692    .Case("pl", ARMCC::PL)
1693    .Case("vs", ARMCC::VS)
1694    .Case("vc", ARMCC::VC)
1695    .Case("hi", ARMCC::HI)
1696    .Case("ls", ARMCC::LS)
1697    .Case("ge", ARMCC::GE)
1698    .Case("lt", ARMCC::LT)
1699    .Case("gt", ARMCC::GT)
1700    .Case("le", ARMCC::LE)
1701    .Case("al", ARMCC::AL)
1702    .Default(~0U);
1703  if (CC == ~0U)
1704    return MatchOperand_NoMatch;
1705  Parser.Lex(); // Eat the token.
1706
1707  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1708
1709  return MatchOperand_Success;
1710}
1711
1712/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1713/// token must be an Identifier when called, and if it is a coprocessor
1714/// number, the token is eaten and the operand is added to the operand list.
1715ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1716parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1717  SMLoc S = Parser.getTok().getLoc();
1718  const AsmToken &Tok = Parser.getTok();
1719  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1720
1721  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1722  if (Num == -1)
1723    return MatchOperand_NoMatch;
1724
1725  Parser.Lex(); // Eat identifier token.
1726  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1727  return MatchOperand_Success;
1728}
1729
1730/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1731/// token must be an Identifier when called, and if it is a coprocessor
1732/// number, the token is eaten and the operand is added to the operand list.
1733ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1734parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1735  SMLoc S = Parser.getTok().getLoc();
1736  const AsmToken &Tok = Parser.getTok();
1737  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1738
1739  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1740  if (Reg == -1)
1741    return MatchOperand_NoMatch;
1742
1743  Parser.Lex(); // Eat identifier token.
1744  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1745  return MatchOperand_Success;
1746}
1747
1748/// Parse a register list, return it if successful else return null.  The first
1749/// token must be a '{' when called.
1750bool ARMAsmParser::
1751parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1752  assert(Parser.getTok().is(AsmToken::LCurly) &&
1753         "Token is not a Left Curly Brace");
1754  SMLoc S = Parser.getTok().getLoc();
1755
1756  // Read the rest of the registers in the list.
1757  unsigned PrevRegNum = 0;
1758  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1759
1760  do {
1761    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1762    Parser.Lex(); // Eat non-identifier token.
1763
1764    const AsmToken &RegTok = Parser.getTok();
1765    SMLoc RegLoc = RegTok.getLoc();
1766    if (RegTok.isNot(AsmToken::Identifier)) {
1767      Error(RegLoc, "register expected");
1768      return true;
1769    }
1770
1771    int RegNum = tryParseRegister();
1772    if (RegNum == -1) {
1773      Error(RegLoc, "register expected");
1774      return true;
1775    }
1776
1777    if (IsRange) {
1778      int Reg = PrevRegNum;
1779      do {
1780        ++Reg;
1781        Registers.push_back(std::make_pair(Reg, RegLoc));
1782      } while (Reg != RegNum);
1783    } else {
1784      Registers.push_back(std::make_pair(RegNum, RegLoc));
1785    }
1786
1787    PrevRegNum = RegNum;
1788  } while (Parser.getTok().is(AsmToken::Comma) ||
1789           Parser.getTok().is(AsmToken::Minus));
1790
1791  // Process the right curly brace of the list.
1792  const AsmToken &RCurlyTok = Parser.getTok();
1793  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1794    Error(RCurlyTok.getLoc(), "'}' expected");
1795    return true;
1796  }
1797
1798  SMLoc E = RCurlyTok.getLoc();
1799  Parser.Lex(); // Eat right curly brace token.
1800
1801  // Verify the register list.
1802  bool EmittedWarning = false;
1803  unsigned HighRegNum = 0;
1804  BitVector RegMap(32);
1805  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1806    const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1807    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1808
1809    if (RegMap[Reg]) {
1810      Error(RegInfo.second, "register duplicated in register list");
1811      return true;
1812    }
1813
1814    if (!EmittedWarning && Reg < HighRegNum)
1815      Warning(RegInfo.second,
1816              "register not in ascending order in register list");
1817
1818    RegMap.set(Reg);
1819    HighRegNum = std::max(Reg, HighRegNum);
1820  }
1821
1822  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1823  return false;
1824}
1825
1826/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1827ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1828parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1829  SMLoc S = Parser.getTok().getLoc();
1830  const AsmToken &Tok = Parser.getTok();
1831  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1832  StringRef OptStr = Tok.getString();
1833
1834  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1835    .Case("sy",    ARM_MB::SY)
1836    .Case("st",    ARM_MB::ST)
1837    .Case("sh",    ARM_MB::ISH)
1838    .Case("ish",   ARM_MB::ISH)
1839    .Case("shst",  ARM_MB::ISHST)
1840    .Case("ishst", ARM_MB::ISHST)
1841    .Case("nsh",   ARM_MB::NSH)
1842    .Case("un",    ARM_MB::NSH)
1843    .Case("nshst", ARM_MB::NSHST)
1844    .Case("unst",  ARM_MB::NSHST)
1845    .Case("osh",   ARM_MB::OSH)
1846    .Case("oshst", ARM_MB::OSHST)
1847    .Default(~0U);
1848
1849  if (Opt == ~0U)
1850    return MatchOperand_NoMatch;
1851
1852  Parser.Lex(); // Eat identifier token.
1853  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1854  return MatchOperand_Success;
1855}
1856
1857/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1858ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1859parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1860  SMLoc S = Parser.getTok().getLoc();
1861  const AsmToken &Tok = Parser.getTok();
1862  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1863  StringRef IFlagsStr = Tok.getString();
1864
1865  unsigned IFlags = 0;
1866  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1867    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1868    .Case("a", ARM_PROC::A)
1869    .Case("i", ARM_PROC::I)
1870    .Case("f", ARM_PROC::F)
1871    .Default(~0U);
1872
1873    // If some specific iflag is already set, it means that some letter is
1874    // present more than once, this is not acceptable.
1875    if (Flag == ~0U || (IFlags & Flag))
1876      return MatchOperand_NoMatch;
1877
1878    IFlags |= Flag;
1879  }
1880
1881  Parser.Lex(); // Eat identifier token.
1882  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1883  return MatchOperand_Success;
1884}
1885
1886/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1887ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1888parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1889  SMLoc S = Parser.getTok().getLoc();
1890  const AsmToken &Tok = Parser.getTok();
1891  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1892  StringRef Mask = Tok.getString();
1893
1894  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1895  size_t Start = 0, Next = Mask.find('_');
1896  StringRef Flags = "";
1897  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1898  if (Next != StringRef::npos)
1899    Flags = Mask.slice(Next+1, Mask.size());
1900
1901  // FlagsVal contains the complete mask:
1902  // 3-0: Mask
1903  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1904  unsigned FlagsVal = 0;
1905
1906  if (SpecReg == "apsr") {
1907    FlagsVal = StringSwitch<unsigned>(Flags)
1908    .Case("nzcvq",  0x8) // same as CPSR_f
1909    .Case("g",      0x4) // same as CPSR_s
1910    .Case("nzcvqg", 0xc) // same as CPSR_fs
1911    .Default(~0U);
1912
1913    if (FlagsVal == ~0U) {
1914      if (!Flags.empty())
1915        return MatchOperand_NoMatch;
1916      else
1917        FlagsVal = 0; // No flag
1918    }
1919  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1920    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1921      Flags = "fc";
1922    for (int i = 0, e = Flags.size(); i != e; ++i) {
1923      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1924      .Case("c", 1)
1925      .Case("x", 2)
1926      .Case("s", 4)
1927      .Case("f", 8)
1928      .Default(~0U);
1929
1930      // If some specific flag is already set, it means that some letter is
1931      // present more than once, this is not acceptable.
1932      if (FlagsVal == ~0U || (FlagsVal & Flag))
1933        return MatchOperand_NoMatch;
1934      FlagsVal |= Flag;
1935    }
1936  } else // No match for special register.
1937    return MatchOperand_NoMatch;
1938
1939  // Special register without flags are equivalent to "fc" flags.
1940  if (!FlagsVal)
1941    FlagsVal = 0x9;
1942
1943  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1944  if (SpecReg == "spsr")
1945    FlagsVal |= 16;
1946
1947  Parser.Lex(); // Eat identifier token.
1948  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1949  return MatchOperand_Success;
1950}
1951
1952ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1953parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1954            int Low, int High) {
1955  const AsmToken &Tok = Parser.getTok();
1956  if (Tok.isNot(AsmToken::Identifier)) {
1957    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1958    return MatchOperand_ParseFail;
1959  }
1960  StringRef ShiftName = Tok.getString();
1961  std::string LowerOp = LowercaseString(Op);
1962  std::string UpperOp = UppercaseString(Op);
1963  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1964    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1965    return MatchOperand_ParseFail;
1966  }
1967  Parser.Lex(); // Eat shift type token.
1968
1969  // There must be a '#' and a shift amount.
1970  if (Parser.getTok().isNot(AsmToken::Hash)) {
1971    Error(Parser.getTok().getLoc(), "'#' expected");
1972    return MatchOperand_ParseFail;
1973  }
1974  Parser.Lex(); // Eat hash token.
1975
1976  const MCExpr *ShiftAmount;
1977  SMLoc Loc = Parser.getTok().getLoc();
1978  if (getParser().ParseExpression(ShiftAmount)) {
1979    Error(Loc, "illegal expression");
1980    return MatchOperand_ParseFail;
1981  }
1982  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1983  if (!CE) {
1984    Error(Loc, "constant expression expected");
1985    return MatchOperand_ParseFail;
1986  }
1987  int Val = CE->getValue();
1988  if (Val < Low || Val > High) {
1989    Error(Loc, "immediate value out of range");
1990    return MatchOperand_ParseFail;
1991  }
1992
1993  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1994
1995  return MatchOperand_Success;
1996}
1997
1998ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1999parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2000  const AsmToken &Tok = Parser.getTok();
2001  SMLoc S = Tok.getLoc();
2002  if (Tok.isNot(AsmToken::Identifier)) {
2003    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2004    return MatchOperand_ParseFail;
2005  }
2006  int Val = StringSwitch<int>(Tok.getString())
2007    .Case("be", 1)
2008    .Case("le", 0)
2009    .Default(-1);
2010  Parser.Lex(); // Eat the token.
2011
2012  if (Val == -1) {
2013    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2014    return MatchOperand_ParseFail;
2015  }
2016  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2017                                                                  getContext()),
2018                                           S, Parser.getTok().getLoc()));
2019  return MatchOperand_Success;
2020}
2021
2022/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2023/// instructions. Legal values are:
2024///     lsl #n  'n' in [0,31]
2025///     asr #n  'n' in [1,32]
2026///             n == 32 encoded as n == 0.
2027ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2028parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2029  const AsmToken &Tok = Parser.getTok();
2030  SMLoc S = Tok.getLoc();
2031  if (Tok.isNot(AsmToken::Identifier)) {
2032    Error(S, "shift operator 'asr' or 'lsl' expected");
2033    return MatchOperand_ParseFail;
2034  }
2035  StringRef ShiftName = Tok.getString();
2036  bool isASR;
2037  if (ShiftName == "lsl" || ShiftName == "LSL")
2038    isASR = false;
2039  else if (ShiftName == "asr" || ShiftName == "ASR")
2040    isASR = true;
2041  else {
2042    Error(S, "shift operator 'asr' or 'lsl' expected");
2043    return MatchOperand_ParseFail;
2044  }
2045  Parser.Lex(); // Eat the operator.
2046
2047  // A '#' and a shift amount.
2048  if (Parser.getTok().isNot(AsmToken::Hash)) {
2049    Error(Parser.getTok().getLoc(), "'#' expected");
2050    return MatchOperand_ParseFail;
2051  }
2052  Parser.Lex(); // Eat hash token.
2053
2054  const MCExpr *ShiftAmount;
2055  SMLoc E = Parser.getTok().getLoc();
2056  if (getParser().ParseExpression(ShiftAmount)) {
2057    Error(E, "malformed shift expression");
2058    return MatchOperand_ParseFail;
2059  }
2060  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2061  if (!CE) {
2062    Error(E, "shift amount must be an immediate");
2063    return MatchOperand_ParseFail;
2064  }
2065
2066  int64_t Val = CE->getValue();
2067  if (isASR) {
2068    // Shift amount must be in [1,32]
2069    if (Val < 1 || Val > 32) {
2070      Error(E, "'asr' shift amount must be in range [1,32]");
2071      return MatchOperand_ParseFail;
2072    }
2073    // asr #32 encoded as asr #0.
2074    if (Val == 32) Val = 0;
2075  } else {
2076    // Shift amount must be in [1,32]
2077    if (Val < 0 || Val > 31) {
2078      Error(E, "'lsr' shift amount must be in range [0,31]");
2079      return MatchOperand_ParseFail;
2080    }
2081  }
2082
2083  E = Parser.getTok().getLoc();
2084  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2085
2086  return MatchOperand_Success;
2087}
2088
2089/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2090/// of instructions. Legal values are:
2091///     ror #n  'n' in {0, 8, 16, 24}
2092ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2093parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2094  const AsmToken &Tok = Parser.getTok();
2095  SMLoc S = Tok.getLoc();
2096  if (Tok.isNot(AsmToken::Identifier)) {
2097    Error(S, "rotate operator 'ror' expected");
2098    return MatchOperand_ParseFail;
2099  }
2100  StringRef ShiftName = Tok.getString();
2101  if (ShiftName != "ror" && ShiftName != "ROR") {
2102    Error(S, "rotate operator 'ror' expected");
2103    return MatchOperand_ParseFail;
2104  }
2105  Parser.Lex(); // Eat the operator.
2106
2107  // A '#' and a rotate amount.
2108  if (Parser.getTok().isNot(AsmToken::Hash)) {
2109    Error(Parser.getTok().getLoc(), "'#' expected");
2110    return MatchOperand_ParseFail;
2111  }
2112  Parser.Lex(); // Eat hash token.
2113
2114  const MCExpr *ShiftAmount;
2115  SMLoc E = Parser.getTok().getLoc();
2116  if (getParser().ParseExpression(ShiftAmount)) {
2117    Error(E, "malformed rotate expression");
2118    return MatchOperand_ParseFail;
2119  }
2120  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2121  if (!CE) {
2122    Error(E, "rotate amount must be an immediate");
2123    return MatchOperand_ParseFail;
2124  }
2125
2126  int64_t Val = CE->getValue();
2127  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2128  // normally, zero is represented in asm by omitting the rotate operand
2129  // entirely.
2130  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2131    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2132    return MatchOperand_ParseFail;
2133  }
2134
2135  E = Parser.getTok().getLoc();
2136  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2137
2138  return MatchOperand_Success;
2139}
2140
2141ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2142parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2143  SMLoc S = Parser.getTok().getLoc();
2144  // The bitfield descriptor is really two operands, the LSB and the width.
2145  if (Parser.getTok().isNot(AsmToken::Hash)) {
2146    Error(Parser.getTok().getLoc(), "'#' expected");
2147    return MatchOperand_ParseFail;
2148  }
2149  Parser.Lex(); // Eat hash token.
2150
2151  const MCExpr *LSBExpr;
2152  SMLoc E = Parser.getTok().getLoc();
2153  if (getParser().ParseExpression(LSBExpr)) {
2154    Error(E, "malformed immediate expression");
2155    return MatchOperand_ParseFail;
2156  }
2157  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2158  if (!CE) {
2159    Error(E, "'lsb' operand must be an immediate");
2160    return MatchOperand_ParseFail;
2161  }
2162
2163  int64_t LSB = CE->getValue();
2164  // The LSB must be in the range [0,31]
2165  if (LSB < 0 || LSB > 31) {
2166    Error(E, "'lsb' operand must be in the range [0,31]");
2167    return MatchOperand_ParseFail;
2168  }
2169  E = Parser.getTok().getLoc();
2170
2171  // Expect another immediate operand.
2172  if (Parser.getTok().isNot(AsmToken::Comma)) {
2173    Error(Parser.getTok().getLoc(), "too few operands");
2174    return MatchOperand_ParseFail;
2175  }
2176  Parser.Lex(); // Eat hash token.
2177  if (Parser.getTok().isNot(AsmToken::Hash)) {
2178    Error(Parser.getTok().getLoc(), "'#' expected");
2179    return MatchOperand_ParseFail;
2180  }
2181  Parser.Lex(); // Eat hash token.
2182
2183  const MCExpr *WidthExpr;
2184  if (getParser().ParseExpression(WidthExpr)) {
2185    Error(E, "malformed immediate expression");
2186    return MatchOperand_ParseFail;
2187  }
2188  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2189  if (!CE) {
2190    Error(E, "'width' operand must be an immediate");
2191    return MatchOperand_ParseFail;
2192  }
2193
2194  int64_t Width = CE->getValue();
2195  // The LSB must be in the range [1,32-lsb]
2196  if (Width < 1 || Width > 32 - LSB) {
2197    Error(E, "'width' operand must be in the range [1,32-lsb]");
2198    return MatchOperand_ParseFail;
2199  }
2200  E = Parser.getTok().getLoc();
2201
2202  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2203
2204  return MatchOperand_Success;
2205}
2206
2207ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2208parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2209  // Check for a post-index addressing register operand. Specifically:
2210  // postidx_reg := '+' register {, shift}
2211  //              | '-' register {, shift}
2212  //              | register {, shift}
2213
2214  // This method must return MatchOperand_NoMatch without consuming any tokens
2215  // in the case where there is no match, as other alternatives take other
2216  // parse methods.
2217  AsmToken Tok = Parser.getTok();
2218  SMLoc S = Tok.getLoc();
2219  bool haveEaten = false;
2220  bool isAdd = true;
2221  int Reg = -1;
2222  if (Tok.is(AsmToken::Plus)) {
2223    Parser.Lex(); // Eat the '+' token.
2224    haveEaten = true;
2225  } else if (Tok.is(AsmToken::Minus)) {
2226    Parser.Lex(); // Eat the '-' token.
2227    isAdd = false;
2228    haveEaten = true;
2229  }
2230  if (Parser.getTok().is(AsmToken::Identifier))
2231    Reg = tryParseRegister();
2232  if (Reg == -1) {
2233    if (!haveEaten)
2234      return MatchOperand_NoMatch;
2235    Error(Parser.getTok().getLoc(), "register expected");
2236    return MatchOperand_ParseFail;
2237  }
2238  SMLoc E = Parser.getTok().getLoc();
2239
2240  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2241  unsigned ShiftImm = 0;
2242  if (Parser.getTok().is(AsmToken::Comma)) {
2243    Parser.Lex(); // Eat the ','.
2244    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2245      return MatchOperand_ParseFail;
2246  }
2247
2248  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2249                                                  ShiftImm, S, E));
2250
2251  return MatchOperand_Success;
2252}
2253
2254ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2255parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2256  // Check for a post-index addressing register operand. Specifically:
2257  // am3offset := '+' register
2258  //              | '-' register
2259  //              | register
2260  //              | # imm
2261  //              | # + imm
2262  //              | # - imm
2263
2264  // This method must return MatchOperand_NoMatch without consuming any tokens
2265  // in the case where there is no match, as other alternatives take other
2266  // parse methods.
2267  AsmToken Tok = Parser.getTok();
2268  SMLoc S = Tok.getLoc();
2269
2270  // Do immediates first, as we always parse those if we have a '#'.
2271  if (Parser.getTok().is(AsmToken::Hash)) {
2272    Parser.Lex(); // Eat the '#'.
2273    // Explicitly look for a '-', as we need to encode negative zero
2274    // differently.
2275    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2276    const MCExpr *Offset;
2277    if (getParser().ParseExpression(Offset))
2278      return MatchOperand_ParseFail;
2279    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2280    if (!CE) {
2281      Error(S, "constant expression expected");
2282      return MatchOperand_ParseFail;
2283    }
2284    SMLoc E = Tok.getLoc();
2285    // Negative zero is encoded as the flag value INT32_MIN.
2286    int32_t Val = CE->getValue();
2287    if (isNegative && Val == 0)
2288      Val = INT32_MIN;
2289
2290    Operands.push_back(
2291      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2292
2293    return MatchOperand_Success;
2294  }
2295
2296
2297  bool haveEaten = false;
2298  bool isAdd = true;
2299  int Reg = -1;
2300  if (Tok.is(AsmToken::Plus)) {
2301    Parser.Lex(); // Eat the '+' token.
2302    haveEaten = true;
2303  } else if (Tok.is(AsmToken::Minus)) {
2304    Parser.Lex(); // Eat the '-' token.
2305    isAdd = false;
2306    haveEaten = true;
2307  }
2308  if (Parser.getTok().is(AsmToken::Identifier))
2309    Reg = tryParseRegister();
2310  if (Reg == -1) {
2311    if (!haveEaten)
2312      return MatchOperand_NoMatch;
2313    Error(Parser.getTok().getLoc(), "register expected");
2314    return MatchOperand_ParseFail;
2315  }
2316  SMLoc E = Parser.getTok().getLoc();
2317
2318  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2319                                                  0, S, E));
2320
2321  return MatchOperand_Success;
2322}
2323
2324/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2325/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2326/// when they refer multiple MIOperands inside a single one.
2327bool ARMAsmParser::
2328cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2329                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2330  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2331
2332  // Create a writeback register dummy placeholder.
2333  Inst.addOperand(MCOperand::CreateImm(0));
2334
2335  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2336  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2337  return true;
2338}
2339
2340/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2341/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2342/// when they refer multiple MIOperands inside a single one.
2343bool ARMAsmParser::
2344cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2345                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2346  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2347
2348  // Create a writeback register dummy placeholder.
2349  Inst.addOperand(MCOperand::CreateImm(0));
2350
2351  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2352  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2353  return true;
2354}
2355
2356
2357/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2358/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2359/// when they refer multiple MIOperands inside a single one.
2360bool ARMAsmParser::
2361cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2362                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2363  // Create a writeback register dummy placeholder.
2364  Inst.addOperand(MCOperand::CreateImm(0));
2365  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2366  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2367  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2368  return true;
2369}
2370
2371/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2372/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2373/// when they refer multiple MIOperands inside a single one.
2374bool ARMAsmParser::
2375cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2376                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2377  // Create a writeback register dummy placeholder.
2378  Inst.addOperand(MCOperand::CreateImm(0));
2379  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2380  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2381  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2382  return true;
2383}
2384
2385/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2386/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2387/// when they refer multiple MIOperands inside a single one.
2388bool ARMAsmParser::
2389cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2390                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2391  // Create a writeback register dummy placeholder.
2392  Inst.addOperand(MCOperand::CreateImm(0));
2393  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2394  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2395  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2396  return true;
2397}
2398
2399/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2400/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2401/// when they refer multiple MIOperands inside a single one.
2402bool ARMAsmParser::
2403cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2404                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2405  // Rt
2406  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2407  // Create a writeback register dummy placeholder.
2408  Inst.addOperand(MCOperand::CreateImm(0));
2409  // addr
2410  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2411  // offset
2412  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2413  // pred
2414  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2415  return true;
2416}
2417
2418/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2419/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2420/// when they refer multiple MIOperands inside a single one.
2421bool ARMAsmParser::
2422cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2423                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2424  // Rt
2425  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2426  // Create a writeback register dummy placeholder.
2427  Inst.addOperand(MCOperand::CreateImm(0));
2428  // addr
2429  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2430  // offset
2431  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2432  // pred
2433  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2434  return true;
2435}
2436
2437/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2438/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2439/// when they refer multiple MIOperands inside a single one.
2440bool ARMAsmParser::
2441cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2442                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2443  // Create a writeback register dummy placeholder.
2444  Inst.addOperand(MCOperand::CreateImm(0));
2445  // Rt
2446  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2447  // addr
2448  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2449  // offset
2450  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2451  // pred
2452  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2453  return true;
2454}
2455
2456/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2457/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2458/// when they refer multiple MIOperands inside a single one.
2459bool ARMAsmParser::
2460cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2461                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2462  // Create a writeback register dummy placeholder.
2463  Inst.addOperand(MCOperand::CreateImm(0));
2464  // Rt
2465  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2466  // addr
2467  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2468  // offset
2469  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2470  // pred
2471  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2472  return true;
2473}
2474
2475/// cvtLdrdPre - Convert parsed operands to MCInst.
2476/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2477/// when they refer multiple MIOperands inside a single one.
2478bool ARMAsmParser::
2479cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2480           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2481  // Rt, Rt2
2482  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2483  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2484  // Create a writeback register dummy placeholder.
2485  Inst.addOperand(MCOperand::CreateImm(0));
2486  // addr
2487  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2488  // pred
2489  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2490  return true;
2491}
2492
2493/// cvtStrdPre - Convert parsed operands to MCInst.
2494/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2495/// when they refer multiple MIOperands inside a single one.
2496bool ARMAsmParser::
2497cvtStrdPre(MCInst &Inst, unsigned Opcode,
2498           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2499  // Create a writeback register dummy placeholder.
2500  Inst.addOperand(MCOperand::CreateImm(0));
2501  // Rt, Rt2
2502  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2503  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2504  // addr
2505  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2506  // pred
2507  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2508  return true;
2509}
2510
2511/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2512/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2513/// when they refer multiple MIOperands inside a single one.
2514bool ARMAsmParser::
2515cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2516                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2517  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2518  // Create a writeback register dummy placeholder.
2519  Inst.addOperand(MCOperand::CreateImm(0));
2520  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2521  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2522  return true;
2523}
2524
2525/// cvtThumbMultiple- Convert parsed operands to MCInst.
2526/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2527/// when they refer multiple MIOperands inside a single one.
2528bool ARMAsmParser::
2529cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2530           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2531  // The second source operand must be the same register as the destination
2532  // operand.
2533  if (Operands.size() == 6 &&
2534      (((ARMOperand*)Operands[3])->getReg() !=
2535       ((ARMOperand*)Operands[5])->getReg()) &&
2536      (((ARMOperand*)Operands[3])->getReg() !=
2537       ((ARMOperand*)Operands[4])->getReg())) {
2538    Error(Operands[3]->getStartLoc(),
2539          "destination register must match source register");
2540    return false;
2541  }
2542  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2543  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2544  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2545  // If we have a three-operand form, use that, else the second source operand
2546  // is just the destination operand again.
2547  if (Operands.size() == 6)
2548    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2549  else
2550    Inst.addOperand(Inst.getOperand(0));
2551  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2552
2553  return true;
2554}
2555
2556/// Parse an ARM memory expression, return false if successful else return true
2557/// or an error.  The first token must be a '[' when called.
2558bool ARMAsmParser::
2559parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2560  SMLoc S, E;
2561  assert(Parser.getTok().is(AsmToken::LBrac) &&
2562         "Token is not a Left Bracket");
2563  S = Parser.getTok().getLoc();
2564  Parser.Lex(); // Eat left bracket token.
2565
2566  const AsmToken &BaseRegTok = Parser.getTok();
2567  int BaseRegNum = tryParseRegister();
2568  if (BaseRegNum == -1)
2569    return Error(BaseRegTok.getLoc(), "register expected");
2570
2571  // The next token must either be a comma or a closing bracket.
2572  const AsmToken &Tok = Parser.getTok();
2573  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2574    return Error(Tok.getLoc(), "malformed memory operand");
2575
2576  if (Tok.is(AsmToken::RBrac)) {
2577    E = Tok.getLoc();
2578    Parser.Lex(); // Eat right bracket token.
2579
2580    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2581                                             0, false, S, E));
2582
2583    return false;
2584  }
2585
2586  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2587  Parser.Lex(); // Eat the comma.
2588
2589  // If we have a '#' it's an immediate offset, else assume it's a register
2590  // offset.
2591  if (Parser.getTok().is(AsmToken::Hash)) {
2592    Parser.Lex(); // Eat the '#'.
2593    E = Parser.getTok().getLoc();
2594
2595    bool isNegative = getParser().getTok().is(AsmToken::Minus);
2596    const MCExpr *Offset;
2597    if (getParser().ParseExpression(Offset))
2598     return true;
2599
2600    // The expression has to be a constant. Memory references with relocations
2601    // don't come through here, as they use the <label> forms of the relevant
2602    // instructions.
2603    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2604    if (!CE)
2605      return Error (E, "constant expression expected");
2606
2607    // If the constant was #-0, represent it as INT32_MIN.
2608    int32_t Val = CE->getValue();
2609    if (isNegative && Val == 0)
2610      CE = MCConstantExpr::Create(INT32_MIN, getContext());
2611
2612    // Now we should have the closing ']'
2613    E = Parser.getTok().getLoc();
2614    if (Parser.getTok().isNot(AsmToken::RBrac))
2615      return Error(E, "']' expected");
2616    Parser.Lex(); // Eat right bracket token.
2617
2618    // Don't worry about range checking the value here. That's handled by
2619    // the is*() predicates.
2620    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2621                                             ARM_AM::no_shift, 0, false, S,E));
2622
2623    // If there's a pre-indexing writeback marker, '!', just add it as a token
2624    // operand.
2625    if (Parser.getTok().is(AsmToken::Exclaim)) {
2626      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2627      Parser.Lex(); // Eat the '!'.
2628    }
2629
2630    return false;
2631  }
2632
2633  // The register offset is optionally preceded by a '+' or '-'
2634  bool isNegative = false;
2635  if (Parser.getTok().is(AsmToken::Minus)) {
2636    isNegative = true;
2637    Parser.Lex(); // Eat the '-'.
2638  } else if (Parser.getTok().is(AsmToken::Plus)) {
2639    // Nothing to do.
2640    Parser.Lex(); // Eat the '+'.
2641  }
2642
2643  E = Parser.getTok().getLoc();
2644  int OffsetRegNum = tryParseRegister();
2645  if (OffsetRegNum == -1)
2646    return Error(E, "register expected");
2647
2648  // If there's a shift operator, handle it.
2649  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2650  unsigned ShiftImm = 0;
2651  if (Parser.getTok().is(AsmToken::Comma)) {
2652    Parser.Lex(); // Eat the ','.
2653    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2654      return true;
2655  }
2656
2657  // Now we should have the closing ']'
2658  E = Parser.getTok().getLoc();
2659  if (Parser.getTok().isNot(AsmToken::RBrac))
2660    return Error(E, "']' expected");
2661  Parser.Lex(); // Eat right bracket token.
2662
2663  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2664                                           ShiftType, ShiftImm, isNegative,
2665                                           S, E));
2666
2667  // If there's a pre-indexing writeback marker, '!', just add it as a token
2668  // operand.
2669  if (Parser.getTok().is(AsmToken::Exclaim)) {
2670    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2671    Parser.Lex(); // Eat the '!'.
2672  }
2673
2674  return false;
2675}
2676
2677/// parseMemRegOffsetShift - one of these two:
2678///   ( lsl | lsr | asr | ror ) , # shift_amount
2679///   rrx
2680/// return true if it parses a shift otherwise it returns false.
2681bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2682                                          unsigned &Amount) {
2683  SMLoc Loc = Parser.getTok().getLoc();
2684  const AsmToken &Tok = Parser.getTok();
2685  if (Tok.isNot(AsmToken::Identifier))
2686    return true;
2687  StringRef ShiftName = Tok.getString();
2688  if (ShiftName == "lsl" || ShiftName == "LSL")
2689    St = ARM_AM::lsl;
2690  else if (ShiftName == "lsr" || ShiftName == "LSR")
2691    St = ARM_AM::lsr;
2692  else if (ShiftName == "asr" || ShiftName == "ASR")
2693    St = ARM_AM::asr;
2694  else if (ShiftName == "ror" || ShiftName == "ROR")
2695    St = ARM_AM::ror;
2696  else if (ShiftName == "rrx" || ShiftName == "RRX")
2697    St = ARM_AM::rrx;
2698  else
2699    return Error(Loc, "illegal shift operator");
2700  Parser.Lex(); // Eat shift type token.
2701
2702  // rrx stands alone.
2703  Amount = 0;
2704  if (St != ARM_AM::rrx) {
2705    Loc = Parser.getTok().getLoc();
2706    // A '#' and a shift amount.
2707    const AsmToken &HashTok = Parser.getTok();
2708    if (HashTok.isNot(AsmToken::Hash))
2709      return Error(HashTok.getLoc(), "'#' expected");
2710    Parser.Lex(); // Eat hash token.
2711
2712    const MCExpr *Expr;
2713    if (getParser().ParseExpression(Expr))
2714      return true;
2715    // Range check the immediate.
2716    // lsl, ror: 0 <= imm <= 31
2717    // lsr, asr: 0 <= imm <= 32
2718    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2719    if (!CE)
2720      return Error(Loc, "shift amount must be an immediate");
2721    int64_t Imm = CE->getValue();
2722    if (Imm < 0 ||
2723        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2724        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2725      return Error(Loc, "immediate shift value out of range");
2726    Amount = Imm;
2727  }
2728
2729  return false;
2730}
2731
2732/// Parse a arm instruction operand.  For now this parses the operand regardless
2733/// of the mnemonic.
2734bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2735                                StringRef Mnemonic) {
2736  SMLoc S, E;
2737
2738  // Check if the current operand has a custom associated parser, if so, try to
2739  // custom parse the operand, or fallback to the general approach.
2740  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2741  if (ResTy == MatchOperand_Success)
2742    return false;
2743  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2744  // there was a match, but an error occurred, in which case, just return that
2745  // the operand parsing failed.
2746  if (ResTy == MatchOperand_ParseFail)
2747    return true;
2748
2749  switch (getLexer().getKind()) {
2750  default:
2751    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2752    return true;
2753  case AsmToken::Identifier: {
2754    if (!tryParseRegisterWithWriteBack(Operands))
2755      return false;
2756    int Res = tryParseShiftRegister(Operands);
2757    if (Res == 0) // success
2758      return false;
2759    else if (Res == -1) // irrecoverable error
2760      return true;
2761
2762    // Fall though for the Identifier case that is not a register or a
2763    // special name.
2764  }
2765  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2766  case AsmToken::Dot: {   // . as a branch target
2767    // This was not a register so parse other operands that start with an
2768    // identifier (like labels) as expressions and create them as immediates.
2769    const MCExpr *IdVal;
2770    S = Parser.getTok().getLoc();
2771    if (getParser().ParseExpression(IdVal))
2772      return true;
2773    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2774    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2775    return false;
2776  }
2777  case AsmToken::LBrac:
2778    return parseMemory(Operands);
2779  case AsmToken::LCurly:
2780    return parseRegisterList(Operands);
2781  case AsmToken::Hash: {
2782    // #42 -> immediate.
2783    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2784    S = Parser.getTok().getLoc();
2785    Parser.Lex();
2786    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2787    const MCExpr *ImmVal;
2788    if (getParser().ParseExpression(ImmVal))
2789      return true;
2790    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
2791    if (!CE) {
2792      Error(S, "constant expression expected");
2793      return MatchOperand_ParseFail;
2794    }
2795    int32_t Val = CE->getValue();
2796    if (isNegative && Val == 0)
2797      ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
2798    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2799    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2800    return false;
2801  }
2802  case AsmToken::Colon: {
2803    // ":lower16:" and ":upper16:" expression prefixes
2804    // FIXME: Check it's an expression prefix,
2805    // e.g. (FOO - :lower16:BAR) isn't legal.
2806    ARMMCExpr::VariantKind RefKind;
2807    if (parsePrefix(RefKind))
2808      return true;
2809
2810    const MCExpr *SubExprVal;
2811    if (getParser().ParseExpression(SubExprVal))
2812      return true;
2813
2814    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2815                                                   getContext());
2816    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2817    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2818    return false;
2819  }
2820  }
2821}
2822
2823// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2824//  :lower16: and :upper16:.
2825bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2826  RefKind = ARMMCExpr::VK_ARM_None;
2827
2828  // :lower16: and :upper16: modifiers
2829  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2830  Parser.Lex(); // Eat ':'
2831
2832  if (getLexer().isNot(AsmToken::Identifier)) {
2833    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2834    return true;
2835  }
2836
2837  StringRef IDVal = Parser.getTok().getIdentifier();
2838  if (IDVal == "lower16") {
2839    RefKind = ARMMCExpr::VK_ARM_LO16;
2840  } else if (IDVal == "upper16") {
2841    RefKind = ARMMCExpr::VK_ARM_HI16;
2842  } else {
2843    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2844    return true;
2845  }
2846  Parser.Lex();
2847
2848  if (getLexer().isNot(AsmToken::Colon)) {
2849    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2850    return true;
2851  }
2852  Parser.Lex(); // Eat the last ':'
2853  return false;
2854}
2855
2856const MCExpr *
2857ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2858                                MCSymbolRefExpr::VariantKind Variant) {
2859  // Recurse over the given expression, rebuilding it to apply the given variant
2860  // to the leftmost symbol.
2861  if (Variant == MCSymbolRefExpr::VK_None)
2862    return E;
2863
2864  switch (E->getKind()) {
2865  case MCExpr::Target:
2866    llvm_unreachable("Can't handle target expr yet");
2867  case MCExpr::Constant:
2868    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2869
2870  case MCExpr::SymbolRef: {
2871    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2872
2873    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2874      return 0;
2875
2876    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2877  }
2878
2879  case MCExpr::Unary:
2880    llvm_unreachable("Can't handle unary expressions yet");
2881
2882  case MCExpr::Binary: {
2883    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2884    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2885    const MCExpr *RHS = BE->getRHS();
2886    if (!LHS)
2887      return 0;
2888
2889    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2890  }
2891  }
2892
2893  assert(0 && "Invalid expression kind!");
2894  return 0;
2895}
2896
2897/// \brief Given a mnemonic, split out possible predication code and carry
2898/// setting letters to form a canonical mnemonic and flags.
2899//
2900// FIXME: Would be nice to autogen this.
2901// FIXME: This is a bit of a maze of special cases.
2902StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2903                                      unsigned &PredicationCode,
2904                                      bool &CarrySetting,
2905                                      unsigned &ProcessorIMod,
2906                                      StringRef &ITMask) {
2907  PredicationCode = ARMCC::AL;
2908  CarrySetting = false;
2909  ProcessorIMod = 0;
2910
2911  // Ignore some mnemonics we know aren't predicated forms.
2912  //
2913  // FIXME: Would be nice to autogen this.
2914  if ((Mnemonic == "movs" && isThumb()) ||
2915      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2916      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2917      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2918      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2919      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2920      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2921      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2922    return Mnemonic;
2923
2924  // First, split out any predication code. Ignore mnemonics we know aren't
2925  // predicated but do have a carry-set and so weren't caught above.
2926  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2927      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2928      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
2929      Mnemonic != "sbcs") {
2930    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2931      .Case("eq", ARMCC::EQ)
2932      .Case("ne", ARMCC::NE)
2933      .Case("hs", ARMCC::HS)
2934      .Case("cs", ARMCC::HS)
2935      .Case("lo", ARMCC::LO)
2936      .Case("cc", ARMCC::LO)
2937      .Case("mi", ARMCC::MI)
2938      .Case("pl", ARMCC::PL)
2939      .Case("vs", ARMCC::VS)
2940      .Case("vc", ARMCC::VC)
2941      .Case("hi", ARMCC::HI)
2942      .Case("ls", ARMCC::LS)
2943      .Case("ge", ARMCC::GE)
2944      .Case("lt", ARMCC::LT)
2945      .Case("gt", ARMCC::GT)
2946      .Case("le", ARMCC::LE)
2947      .Case("al", ARMCC::AL)
2948      .Default(~0U);
2949    if (CC != ~0U) {
2950      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2951      PredicationCode = CC;
2952    }
2953  }
2954
2955  // Next, determine if we have a carry setting bit. We explicitly ignore all
2956  // the instructions we know end in 's'.
2957  if (Mnemonic.endswith("s") &&
2958      !(Mnemonic == "cps" || Mnemonic == "mls" ||
2959        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2960        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2961        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2962        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2963        (Mnemonic == "movs" && isThumb()))) {
2964    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2965    CarrySetting = true;
2966  }
2967
2968  // The "cps" instruction can have a interrupt mode operand which is glued into
2969  // the mnemonic. Check if this is the case, split it and parse the imod op
2970  if (Mnemonic.startswith("cps")) {
2971    // Split out any imod code.
2972    unsigned IMod =
2973      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2974      .Case("ie", ARM_PROC::IE)
2975      .Case("id", ARM_PROC::ID)
2976      .Default(~0U);
2977    if (IMod != ~0U) {
2978      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2979      ProcessorIMod = IMod;
2980    }
2981  }
2982
2983  // The "it" instruction has the condition mask on the end of the mnemonic.
2984  if (Mnemonic.startswith("it")) {
2985    ITMask = Mnemonic.slice(2, Mnemonic.size());
2986    Mnemonic = Mnemonic.slice(0, 2);
2987  }
2988
2989  return Mnemonic;
2990}
2991
2992/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2993/// inclusion of carry set or predication code operands.
2994//
2995// FIXME: It would be nice to autogen this.
2996void ARMAsmParser::
2997getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2998                      bool &CanAcceptPredicationCode) {
2999  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3000      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3001      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
3002      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3003      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
3004      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3005      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
3006      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
3007      // FIXME: We need a better way. This really confused Thumb2
3008      // parsing for 'mov'.
3009      (Mnemonic == "mov" && !isThumbOne())) {
3010    CanAcceptCarrySet = true;
3011  } else {
3012    CanAcceptCarrySet = false;
3013  }
3014
3015  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3016      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3017      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3018      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3019      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
3020      Mnemonic == "setend" ||
3021      (Mnemonic == "nop" && isThumbOne()) ||
3022      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
3023       !isThumb()) ||
3024      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3025       !isThumb()) ||
3026      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
3027    CanAcceptPredicationCode = false;
3028  } else {
3029    CanAcceptPredicationCode = true;
3030  }
3031
3032  if (isThumb())
3033    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3034        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3035      CanAcceptPredicationCode = false;
3036}
3037
3038bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3039                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3040
3041  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3042  // another does not. Specifically, the MOVW instruction does not. So we
3043  // special case it here and remove the defaulted (non-setting) cc_out
3044  // operand if that's the instruction we're trying to match.
3045  //
3046  // We do this as post-processing of the explicit operands rather than just
3047  // conditionally adding the cc_out in the first place because we need
3048  // to check the type of the parsed immediate operand.
3049  if (Mnemonic == "mov" && Operands.size() > 4 &&
3050      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3051      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3052      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3053    return true;
3054
3055  // Register-register 'add' for thumb does not have a cc_out operand
3056  // when there are only two register operands.
3057  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3058      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3059      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3060      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3061    return true;
3062  // Register-register 'add' for thumb does not have a cc_out operand
3063  // when it's an ADD Rdm, SP, {Rdm|#imm} instruction.
3064  if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
3065      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3066      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3067      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3068      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3069    return true;
3070  // Register-register 'add/sub' for thumb does not have a cc_out operand
3071  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3072  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3073  // right, this will result in better diagnostics (which operand is off)
3074  // anyway.
3075  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3076      (Operands.size() == 5 || Operands.size() == 6) &&
3077      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3078      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3079      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3080    return true;
3081
3082  return false;
3083}
3084
3085/// Parse an arm instruction mnemonic followed by its operands.
3086bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3087                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3088  // Create the leading tokens for the mnemonic, split by '.' characters.
3089  size_t Start = 0, Next = Name.find('.');
3090  StringRef Mnemonic = Name.slice(Start, Next);
3091
3092  // Split out the predication code and carry setting flag from the mnemonic.
3093  unsigned PredicationCode;
3094  unsigned ProcessorIMod;
3095  bool CarrySetting;
3096  StringRef ITMask;
3097  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3098                           ProcessorIMod, ITMask);
3099
3100  // In Thumb1, only the branch (B) instruction can be predicated.
3101  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3102    Parser.EatToEndOfStatement();
3103    return Error(NameLoc, "conditional execution not supported in Thumb1");
3104  }
3105
3106  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3107
3108  // Handle the IT instruction ITMask. Convert it to a bitmask. This
3109  // is the mask as it will be for the IT encoding if the conditional
3110  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3111  // where the conditional bit0 is zero, the instruction post-processing
3112  // will adjust the mask accordingly.
3113  if (Mnemonic == "it") {
3114    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3115    if (ITMask.size() > 3) {
3116      Parser.EatToEndOfStatement();
3117      return Error(Loc, "too many conditions on IT instruction");
3118    }
3119    unsigned Mask = 8;
3120    for (unsigned i = ITMask.size(); i != 0; --i) {
3121      char pos = ITMask[i - 1];
3122      if (pos != 't' && pos != 'e') {
3123        Parser.EatToEndOfStatement();
3124        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
3125      }
3126      Mask >>= 1;
3127      if (ITMask[i - 1] == 't')
3128        Mask |= 8;
3129    }
3130    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
3131  }
3132
3133  // FIXME: This is all a pretty gross hack. We should automatically handle
3134  // optional operands like this via tblgen.
3135
3136  // Next, add the CCOut and ConditionCode operands, if needed.
3137  //
3138  // For mnemonics which can ever incorporate a carry setting bit or predication
3139  // code, our matching model involves us always generating CCOut and
3140  // ConditionCode operands to match the mnemonic "as written" and then we let
3141  // the matcher deal with finding the right instruction or generating an
3142  // appropriate error.
3143  bool CanAcceptCarrySet, CanAcceptPredicationCode;
3144  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3145
3146  // If we had a carry-set on an instruction that can't do that, issue an
3147  // error.
3148  if (!CanAcceptCarrySet && CarrySetting) {
3149    Parser.EatToEndOfStatement();
3150    return Error(NameLoc, "instruction '" + Mnemonic +
3151                 "' can not set flags, but 's' suffix specified");
3152  }
3153  // If we had a predication code on an instruction that can't do that, issue an
3154  // error.
3155  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3156    Parser.EatToEndOfStatement();
3157    return Error(NameLoc, "instruction '" + Mnemonic +
3158                 "' is not predicable, but condition code specified");
3159  }
3160
3161  // Add the carry setting operand, if necessary.
3162  if (CanAcceptCarrySet) {
3163    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
3164    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3165                                               Loc));
3166  }
3167
3168  // Add the predication code operand, if necessary.
3169  if (CanAcceptPredicationCode) {
3170    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
3171                                      CarrySetting);
3172    Operands.push_back(ARMOperand::CreateCondCode(
3173                         ARMCC::CondCodes(PredicationCode), Loc));
3174  }
3175
3176  // Add the processor imod operand, if necessary.
3177  if (ProcessorIMod) {
3178    Operands.push_back(ARMOperand::CreateImm(
3179          MCConstantExpr::Create(ProcessorIMod, getContext()),
3180                                 NameLoc, NameLoc));
3181  }
3182
3183  // Add the remaining tokens in the mnemonic.
3184  while (Next != StringRef::npos) {
3185    Start = Next;
3186    Next = Name.find('.', Start + 1);
3187    StringRef ExtraToken = Name.slice(Start, Next);
3188
3189    // For now, we're only parsing Thumb1 (for the most part), so
3190    // just ignore ".n" qualifiers. We'll use them to restrict
3191    // matching when we do Thumb2.
3192    if (ExtraToken != ".n")
3193      Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
3194  }
3195
3196  // Read the remaining operands.
3197  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3198    // Read the first operand.
3199    if (parseOperand(Operands, Mnemonic)) {
3200      Parser.EatToEndOfStatement();
3201      return true;
3202    }
3203
3204    while (getLexer().is(AsmToken::Comma)) {
3205      Parser.Lex();  // Eat the comma.
3206
3207      // Parse and remember the operand.
3208      if (parseOperand(Operands, Mnemonic)) {
3209        Parser.EatToEndOfStatement();
3210        return true;
3211      }
3212    }
3213  }
3214
3215  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3216    Parser.EatToEndOfStatement();
3217    return TokError("unexpected token in argument list");
3218  }
3219
3220  Parser.Lex(); // Consume the EndOfStatement
3221
3222  // Some instructions, mostly Thumb, have forms for the same mnemonic that
3223  // do and don't have a cc_out optional-def operand. With some spot-checks
3224  // of the operand list, we can figure out which variant we're trying to
3225  // parse and adjust accordingly before actually matching. Reason number
3226  // #317 the table driven matcher doesn't fit well with the ARM instruction
3227  // set.
3228  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
3229    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3230    Operands.erase(Operands.begin() + 1);
3231    delete Op;
3232  }
3233
3234  // ARM mode 'blx' need special handling, as the register operand version
3235  // is predicable, but the label operand version is not. So, we can't rely
3236  // on the Mnemonic based checking to correctly figure out when to put
3237  // a CondCode operand in the list. If we're trying to match the label
3238  // version, remove the CondCode operand here.
3239  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3240      static_cast<ARMOperand*>(Operands[2])->isImm()) {
3241    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3242    Operands.erase(Operands.begin() + 1);
3243    delete Op;
3244  }
3245
3246  // The vector-compare-to-zero instructions have a literal token "#0" at
3247  // the end that comes to here as an immediate operand. Convert it to a
3248  // token to play nicely with the matcher.
3249  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3250      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3251      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3252    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3253    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3254    if (CE && CE->getValue() == 0) {
3255      Operands.erase(Operands.begin() + 5);
3256      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3257      delete Op;
3258    }
3259  }
3260  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3261  // end. Convert it to a token here.
3262  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3263      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3264    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3265    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3266    if (CE && CE->getValue() == 0) {
3267      Operands.erase(Operands.begin() + 5);
3268      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3269      delete Op;
3270    }
3271  }
3272
3273  return false;
3274}
3275
3276// Validate context-sensitive operand constraints.
3277
3278// return 'true' if register list contains non-low GPR registers,
3279// 'false' otherwise. If Reg is in the register list or is HiReg, set
3280// 'containsReg' to true.
3281static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3282                                 unsigned HiReg, bool &containsReg) {
3283  containsReg = false;
3284  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3285    unsigned OpReg = Inst.getOperand(i).getReg();
3286    if (OpReg == Reg)
3287      containsReg = true;
3288    // Anything other than a low register isn't legal here.
3289    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3290      return true;
3291  }
3292  return false;
3293}
3294
3295// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3296// the ARMInsts array) instead. Getting that here requires awkward
3297// API changes, though. Better way?
3298namespace llvm {
3299extern MCInstrDesc ARMInsts[];
3300}
3301static MCInstrDesc &getInstDesc(unsigned Opcode) {
3302  return ARMInsts[Opcode];
3303}
3304
3305// FIXME: We would really like to be able to tablegen'erate this.
3306bool ARMAsmParser::
3307validateInstruction(MCInst &Inst,
3308                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3309  MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3310  SMLoc Loc = Operands[0]->getStartLoc();
3311  // Check the IT block state first.
3312  if (inITBlock()) {
3313    unsigned bit = 1;
3314    if (ITState.FirstCond)
3315      ITState.FirstCond = false;
3316    else
3317      bit = (ITState.Mask >> (4 - ITState.CurPosition)) & 1;
3318    // Increment our position in the IT block first thing, as we want to
3319    // move forward even if we find an error in the IT block.
3320    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
3321    if (++ITState.CurPosition == 4 - TZ)
3322      ITState.CurPosition = ~0U; // Done with the IT block after this.
3323    // The instruction must be predicable.
3324    if (!MCID.isPredicable())
3325      return Error(Loc, "instructions in IT block must be predicable");
3326    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
3327    unsigned ITCond = bit ? ITState.Cond :
3328      ARMCC::getOppositeCondition(ITState.Cond);
3329    if (Cond != ITCond) {
3330      // Find the condition code Operand to get its SMLoc information.
3331      SMLoc CondLoc;
3332      for (unsigned i = 1; i < Operands.size(); ++i)
3333        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
3334          CondLoc = Operands[i]->getStartLoc();
3335      return Error(CondLoc, "incorrect condition in IT block; got '" +
3336                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
3337                   "', but expected '" +
3338                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
3339    }
3340  // Check for non-'al' condition codes outside of the IT block.
3341  } else if (isThumbTwo() && MCID.isPredicable() &&
3342             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
3343             ARMCC::AL && Inst.getOpcode() != ARM::tBcc)
3344    return Error(Loc, "predicated instructions must be in IT block");
3345
3346  switch (Inst.getOpcode()) {
3347  case ARM::LDRD:
3348  case ARM::LDRD_PRE:
3349  case ARM::LDRD_POST:
3350  case ARM::LDREXD: {
3351    // Rt2 must be Rt + 1.
3352    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3353    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3354    if (Rt2 != Rt + 1)
3355      return Error(Operands[3]->getStartLoc(),
3356                   "destination operands must be sequential");
3357    return false;
3358  }
3359  case ARM::STRD: {
3360    // Rt2 must be Rt + 1.
3361    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3362    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3363    if (Rt2 != Rt + 1)
3364      return Error(Operands[3]->getStartLoc(),
3365                   "source operands must be sequential");
3366    return false;
3367  }
3368  case ARM::STRD_PRE:
3369  case ARM::STRD_POST:
3370  case ARM::STREXD: {
3371    // Rt2 must be Rt + 1.
3372    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3373    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3374    if (Rt2 != Rt + 1)
3375      return Error(Operands[3]->getStartLoc(),
3376                   "source operands must be sequential");
3377    return false;
3378  }
3379  case ARM::SBFX:
3380  case ARM::UBFX: {
3381    // width must be in range [1, 32-lsb]
3382    unsigned lsb = Inst.getOperand(2).getImm();
3383    unsigned widthm1 = Inst.getOperand(3).getImm();
3384    if (widthm1 >= 32 - lsb)
3385      return Error(Operands[5]->getStartLoc(),
3386                   "bitfield width must be in range [1,32-lsb]");
3387    return false;
3388  }
3389  case ARM::tLDMIA: {
3390    // Thumb LDM instructions are writeback iff the base register is not
3391    // in the register list.
3392    unsigned Rn = Inst.getOperand(0).getReg();
3393    bool hasWritebackToken =
3394      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3395       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3396    bool listContainsBase;
3397    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase))
3398      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3399                   "registers must be in range r0-r7");
3400    // If we should have writeback, then there should be a '!' token.
3401    if (!listContainsBase && !hasWritebackToken)
3402      return Error(Operands[2]->getStartLoc(),
3403                   "writeback operator '!' expected");
3404    // Likewise, if we should not have writeback, there must not be a '!'
3405    if (listContainsBase && hasWritebackToken)
3406      return Error(Operands[3]->getStartLoc(),
3407                   "writeback operator '!' not allowed when base register "
3408                   "in register list");
3409
3410    break;
3411  }
3412  case ARM::tPOP: {
3413    bool listContainsBase;
3414    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3415      return Error(Operands[2]->getStartLoc(),
3416                   "registers must be in range r0-r7 or pc");
3417    break;
3418  }
3419  case ARM::tPUSH: {
3420    bool listContainsBase;
3421    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3422      return Error(Operands[2]->getStartLoc(),
3423                   "registers must be in range r0-r7 or lr");
3424    break;
3425  }
3426  case ARM::tSTMIA_UPD: {
3427    bool listContainsBase;
3428    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3429      return Error(Operands[4]->getStartLoc(),
3430                   "registers must be in range r0-r7");
3431    break;
3432  }
3433  }
3434
3435  return false;
3436}
3437
3438void ARMAsmParser::
3439processInstruction(MCInst &Inst,
3440                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3441  switch (Inst.getOpcode()) {
3442  case ARM::LDMIA_UPD:
3443    // If this is a load of a single register via a 'pop', then we should use
3444    // a post-indexed LDR instruction instead, per the ARM ARM.
3445    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3446        Inst.getNumOperands() == 5) {
3447      MCInst TmpInst;
3448      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3449      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3450      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3451      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3452      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3453      TmpInst.addOperand(MCOperand::CreateImm(4));
3454      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3455      TmpInst.addOperand(Inst.getOperand(3));
3456      Inst = TmpInst;
3457    }
3458    break;
3459  case ARM::STMDB_UPD:
3460    // If this is a store of a single register via a 'push', then we should use
3461    // a pre-indexed STR instruction instead, per the ARM ARM.
3462    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3463        Inst.getNumOperands() == 5) {
3464      MCInst TmpInst;
3465      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3466      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3467      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3468      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3469      TmpInst.addOperand(MCOperand::CreateImm(-4));
3470      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3471      TmpInst.addOperand(Inst.getOperand(3));
3472      Inst = TmpInst;
3473    }
3474    break;
3475  case ARM::tADDi8:
3476    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3477    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3478    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3479    // to encoding T1 if <Rd> is omitted."
3480    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3481      Inst.setOpcode(ARM::tADDi3);
3482    break;
3483  case ARM::tBcc:
3484    // If the conditional is AL, we really want tB.
3485    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3486      Inst.setOpcode(ARM::tB);
3487    break;
3488  case ARM::t2IT: {
3489    // The mask bits for all but the first condition are represented as
3490    // the low bit of the condition code value implies 't'. We currently
3491    // always have 1 implies 't', so XOR toggle the bits if the low bit
3492    // of the condition code is zero. The encoding also expects the low
3493    // bit of the condition to be encoded as bit 4 of the mask operand,
3494    // so mask that in if needed
3495    MCOperand &MO = Inst.getOperand(1);
3496    unsigned Mask = MO.getImm();
3497    unsigned OrigMask = Mask;
3498    unsigned TZ = CountTrailingZeros_32(Mask);
3499    if ((Inst.getOperand(0).getImm() & 1) == 0) {
3500      assert(Mask && TZ <= 3 && "illegal IT mask value!");
3501      for (unsigned i = 3; i != TZ; --i)
3502        Mask ^= 1 << i;
3503    } else
3504      Mask |= 0x10;
3505    MO.setImm(Mask);
3506
3507    // Set up the IT block state according to the IT instruction we just
3508    // matched.
3509    assert(!inITBlock() && "nested IT blocks?!");
3510    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
3511    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
3512    ITState.CurPosition = 0;
3513    ITState.FirstCond = true;
3514    break;
3515  }
3516  }
3517}
3518
3519unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3520  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3521  // suffix depending on whether they're in an IT block or not.
3522  unsigned Opc = Inst.getOpcode();
3523  MCInstrDesc &MCID = getInstDesc(Opc);
3524  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3525    assert(MCID.hasOptionalDef() &&
3526           "optionally flag setting instruction missing optional def operand");
3527    assert(MCID.NumOperands == Inst.getNumOperands() &&
3528           "operand count mismatch!");
3529    // Find the optional-def operand (cc_out).
3530    unsigned OpNo;
3531    for (OpNo = 0;
3532         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3533         ++OpNo)
3534      ;
3535    // If we're parsing Thumb1, reject it completely.
3536    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3537      return Match_MnemonicFail;
3538    // If we're parsing Thumb2, which form is legal depends on whether we're
3539    // in an IT block.
3540    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
3541        !inITBlock())
3542      return Match_RequiresITBlock;
3543    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
3544        inITBlock())
3545      return Match_RequiresNotITBlock;
3546  }
3547  // Some high-register supporting Thumb1 encodings only allow both registers
3548  // to be from r0-r7 when in Thumb2.
3549  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3550           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3551           isARMLowRegister(Inst.getOperand(2).getReg()))
3552    return Match_RequiresThumb2;
3553  // Others only require ARMv6 or later.
3554  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3555           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3556           isARMLowRegister(Inst.getOperand(1).getReg()))
3557    return Match_RequiresV6;
3558  return Match_Success;
3559}
3560
3561bool ARMAsmParser::
3562MatchAndEmitInstruction(SMLoc IDLoc,
3563                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3564                        MCStreamer &Out) {
3565  MCInst Inst;
3566  unsigned ErrorInfo;
3567  unsigned MatchResult;
3568  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3569  switch (MatchResult) {
3570  default: break;
3571  case Match_Success:
3572    // Context sensitive operand constraints aren't handled by the matcher,
3573    // so check them here.
3574    if (validateInstruction(Inst, Operands))
3575      return true;
3576
3577    // Some instructions need post-processing to, for example, tweak which
3578    // encoding is selected.
3579    processInstruction(Inst, Operands);
3580
3581    Out.EmitInstruction(Inst);
3582    return false;
3583  case Match_MissingFeature:
3584    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3585    return true;
3586  case Match_InvalidOperand: {
3587    SMLoc ErrorLoc = IDLoc;
3588    if (ErrorInfo != ~0U) {
3589      if (ErrorInfo >= Operands.size())
3590        return Error(IDLoc, "too few operands for instruction");
3591
3592      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3593      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3594    }
3595
3596    return Error(ErrorLoc, "invalid operand for instruction");
3597  }
3598  case Match_MnemonicFail:
3599    return Error(IDLoc, "invalid instruction");
3600  case Match_ConversionFail:
3601    // The converter function will have already emited a diagnostic.
3602    return true;
3603  case Match_RequiresNotITBlock:
3604    return Error(IDLoc, "flag setting instruction only valid outside IT block");
3605  case Match_RequiresITBlock:
3606    return Error(IDLoc, "instruction only valid inside IT block");
3607  case Match_RequiresV6:
3608    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3609  case Match_RequiresThumb2:
3610    return Error(IDLoc, "instruction variant requires Thumb2");
3611  }
3612
3613  llvm_unreachable("Implement any new match types added!");
3614  return true;
3615}
3616
3617/// parseDirective parses the arm specific directives
3618bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3619  StringRef IDVal = DirectiveID.getIdentifier();
3620  if (IDVal == ".word")
3621    return parseDirectiveWord(4, DirectiveID.getLoc());
3622  else if (IDVal == ".thumb")
3623    return parseDirectiveThumb(DirectiveID.getLoc());
3624  else if (IDVal == ".thumb_func")
3625    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3626  else if (IDVal == ".code")
3627    return parseDirectiveCode(DirectiveID.getLoc());
3628  else if (IDVal == ".syntax")
3629    return parseDirectiveSyntax(DirectiveID.getLoc());
3630  return true;
3631}
3632
3633/// parseDirectiveWord
3634///  ::= .word [ expression (, expression)* ]
3635bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3636  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3637    for (;;) {
3638      const MCExpr *Value;
3639      if (getParser().ParseExpression(Value))
3640        return true;
3641
3642      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3643
3644      if (getLexer().is(AsmToken::EndOfStatement))
3645        break;
3646
3647      // FIXME: Improve diagnostic.
3648      if (getLexer().isNot(AsmToken::Comma))
3649        return Error(L, "unexpected token in directive");
3650      Parser.Lex();
3651    }
3652  }
3653
3654  Parser.Lex();
3655  return false;
3656}
3657
3658/// parseDirectiveThumb
3659///  ::= .thumb
3660bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3661  if (getLexer().isNot(AsmToken::EndOfStatement))
3662    return Error(L, "unexpected token in directive");
3663  Parser.Lex();
3664
3665  // TODO: set thumb mode
3666  // TODO: tell the MC streamer the mode
3667  // getParser().getStreamer().Emit???();
3668  return false;
3669}
3670
3671/// parseDirectiveThumbFunc
3672///  ::= .thumbfunc symbol_name
3673bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3674  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3675  bool isMachO = MAI.hasSubsectionsViaSymbols();
3676  StringRef Name;
3677
3678  // Darwin asm has function name after .thumb_func direction
3679  // ELF doesn't
3680  if (isMachO) {
3681    const AsmToken &Tok = Parser.getTok();
3682    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3683      return Error(L, "unexpected token in .thumb_func directive");
3684    Name = Tok.getString();
3685    Parser.Lex(); // Consume the identifier token.
3686  }
3687
3688  if (getLexer().isNot(AsmToken::EndOfStatement))
3689    return Error(L, "unexpected token in directive");
3690  Parser.Lex();
3691
3692  // FIXME: assuming function name will be the line following .thumb_func
3693  if (!isMachO) {
3694    Name = Parser.getTok().getString();
3695  }
3696
3697  // Mark symbol as a thumb symbol.
3698  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3699  getParser().getStreamer().EmitThumbFunc(Func);
3700  return false;
3701}
3702
3703/// parseDirectiveSyntax
3704///  ::= .syntax unified | divided
3705bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3706  const AsmToken &Tok = Parser.getTok();
3707  if (Tok.isNot(AsmToken::Identifier))
3708    return Error(L, "unexpected token in .syntax directive");
3709  StringRef Mode = Tok.getString();
3710  if (Mode == "unified" || Mode == "UNIFIED")
3711    Parser.Lex();
3712  else if (Mode == "divided" || Mode == "DIVIDED")
3713    return Error(L, "'.syntax divided' arm asssembly not supported");
3714  else
3715    return Error(L, "unrecognized syntax mode in .syntax directive");
3716
3717  if (getLexer().isNot(AsmToken::EndOfStatement))
3718    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3719  Parser.Lex();
3720
3721  // TODO tell the MC streamer the mode
3722  // getParser().getStreamer().Emit???();
3723  return false;
3724}
3725
3726/// parseDirectiveCode
3727///  ::= .code 16 | 32
3728bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3729  const AsmToken &Tok = Parser.getTok();
3730  if (Tok.isNot(AsmToken::Integer))
3731    return Error(L, "unexpected token in .code directive");
3732  int64_t Val = Parser.getTok().getIntVal();
3733  if (Val == 16)
3734    Parser.Lex();
3735  else if (Val == 32)
3736    Parser.Lex();
3737  else
3738    return Error(L, "invalid operand to .code directive");
3739
3740  if (getLexer().isNot(AsmToken::EndOfStatement))
3741    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3742  Parser.Lex();
3743
3744  if (Val == 16) {
3745    if (!isThumb()) {
3746      SwitchMode();
3747      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3748    }
3749  } else {
3750    if (isThumb()) {
3751      SwitchMode();
3752      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3753    }
3754  }
3755
3756  return false;
3757}
3758
3759extern "C" void LLVMInitializeARMAsmLexer();
3760
3761/// Force static initialization.
3762extern "C" void LLVMInitializeARMAsmParser() {
3763  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3764  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3765  LLVMInitializeARMAsmLexer();
3766}
3767
3768#define GET_REGISTER_MATCHER
3769#define GET_MATCHER_IMPLEMENTATION
3770#include "ARMGenAsmMatcher.inc"
3771