ARMAsmParser.cpp revision f95aaf951b628621c9c74bed6c450b8a52a1ae1e 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/SourceMgr.h"
26#include "llvm/Support/TargetRegistry.h"
27#include "llvm/Support/raw_ostream.h"
28#include "llvm/ADT/BitVector.h"
29#include "llvm/ADT/OwningPtr.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallVector.h"
32#include "llvm/ADT/StringExtras.h"
33#include "llvm/ADT/StringSwitch.h"
34#include "llvm/ADT/Twine.h"
35
36using namespace llvm;
37
38namespace {
39
40class ARMOperand;
41
42class ARMAsmParser : public MCTargetAsmParser {
43  MCSubtargetInfo &STI;
44  MCAsmParser &Parser;
45
46  MCAsmParser &getParser() const { return Parser; }
47  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
48
49  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
51
52  int tryParseRegister();
53  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
54  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
55  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
56  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
57  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
58  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
59  const MCExpr *applyPrefixToExpr(const MCExpr *E,
60                                  MCSymbolRefExpr::VariantKind Variant);
61
62
63  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
64                              unsigned &ShiftAmount);
65  bool parseDirectiveWord(unsigned Size, SMLoc L);
66  bool parseDirectiveThumb(SMLoc L);
67  bool parseDirectiveThumbFunc(SMLoc L);
68  bool parseDirectiveCode(SMLoc L);
69  bool parseDirectiveSyntax(SMLoc L);
70
71  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
72                          bool &CarrySetting, unsigned &ProcessorIMod);
73  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
74                             bool &CanAcceptPredicationCode);
75
76  bool isThumb() const {
77    // FIXME: Can tablegen auto-generate this?
78    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
79  }
80  bool isThumbOne() const {
81    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
82  }
83  bool isThumbTwo() const {
84    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
85  }
86  bool hasV6Ops() const {
87    return STI.getFeatureBits() & ARM::HasV6Ops;
88  }
89  void SwitchMode() {
90    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
91    setAvailableFeatures(FB);
92  }
93
94  /// @name Auto-generated Match Functions
95  /// {
96
97#define GET_ASSEMBLER_HEADER
98#include "ARMGenAsmMatcher.inc"
99
100  /// }
101
102  OperandMatchResultTy parseCoprocNumOperand(
103    SmallVectorImpl<MCParsedAsmOperand*>&);
104  OperandMatchResultTy parseCoprocRegOperand(
105    SmallVectorImpl<MCParsedAsmOperand*>&);
106  OperandMatchResultTy parseMemBarrierOptOperand(
107    SmallVectorImpl<MCParsedAsmOperand*>&);
108  OperandMatchResultTy parseProcIFlagsOperand(
109    SmallVectorImpl<MCParsedAsmOperand*>&);
110  OperandMatchResultTy parseMSRMaskOperand(
111    SmallVectorImpl<MCParsedAsmOperand*>&);
112  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
113                                   StringRef Op, int Low, int High);
114  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
115    return parsePKHImm(O, "lsl", 0, 31);
116  }
117  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
118    return parsePKHImm(O, "asr", 1, 32);
119  }
120  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
121  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
122  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
123  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
124  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
125  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
126
127  // Asm Match Converter Methods
128  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
129                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
130  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
131                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
132  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
133                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
134  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
135                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
136  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
137                             const SmallVectorImpl<MCParsedAsmOperand*> &);
138  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
139                             const SmallVectorImpl<MCParsedAsmOperand*> &);
140  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
141                             const SmallVectorImpl<MCParsedAsmOperand*> &);
142  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
143                             const SmallVectorImpl<MCParsedAsmOperand*> &);
144  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
145                  const SmallVectorImpl<MCParsedAsmOperand*> &);
146  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
147                  const SmallVectorImpl<MCParsedAsmOperand*> &);
148  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
149                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
150  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
151                        const SmallVectorImpl<MCParsedAsmOperand*> &);
152
153  bool validateInstruction(MCInst &Inst,
154                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
155  void processInstruction(MCInst &Inst,
156                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
157  bool shouldOmitCCOutOperand(StringRef Mnemonic,
158                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
159
160public:
161  enum ARMMatchResultTy {
162    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
163    Match_RequiresV6,
164    Match_RequiresThumb2
165  };
166
167  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
168    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
169    MCAsmParserExtension::Initialize(_Parser);
170
171    // Initialize the set of available features.
172    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
173  }
174
175  // Implementation of the MCTargetAsmParser interface:
176  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
177  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
178                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
179  bool ParseDirective(AsmToken DirectiveID);
180
181  unsigned checkTargetMatchPredicate(MCInst &Inst);
182
183  bool MatchAndEmitInstruction(SMLoc IDLoc,
184                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
185                               MCStreamer &Out);
186};
187} // end anonymous namespace
188
189namespace {
190
191/// ARMOperand - Instances of this class represent a parsed ARM machine
192/// instruction.
193class ARMOperand : public MCParsedAsmOperand {
194  enum KindTy {
195    CondCode,
196    CCOut,
197    CoprocNum,
198    CoprocReg,
199    Immediate,
200    MemBarrierOpt,
201    Memory,
202    PostIndexRegister,
203    MSRMask,
204    ProcIFlags,
205    Register,
206    RegisterList,
207    DPRRegisterList,
208    SPRRegisterList,
209    ShiftedRegister,
210    ShiftedImmediate,
211    ShifterImmediate,
212    RotateImmediate,
213    BitfieldDescriptor,
214    Token
215  } Kind;
216
217  SMLoc StartLoc, EndLoc;
218  SmallVector<unsigned, 8> Registers;
219
220  union {
221    struct {
222      ARMCC::CondCodes Val;
223    } CC;
224
225    struct {
226      ARM_MB::MemBOpt Val;
227    } MBOpt;
228
229    struct {
230      unsigned Val;
231    } Cop;
232
233    struct {
234      ARM_PROC::IFlags Val;
235    } IFlags;
236
237    struct {
238      unsigned Val;
239    } MMask;
240
241    struct {
242      const char *Data;
243      unsigned Length;
244    } Tok;
245
246    struct {
247      unsigned RegNum;
248    } Reg;
249
250    struct {
251      const MCExpr *Val;
252    } Imm;
253
254    /// Combined record for all forms of ARM address expressions.
255    struct {
256      unsigned BaseRegNum;
257      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
258      // was specified.
259      const MCConstantExpr *OffsetImm;  // Offset immediate value
260      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
261      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
262      unsigned ShiftImm;      // shift for OffsetReg.
263      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
264    } Mem;
265
266    struct {
267      unsigned RegNum;
268      bool isAdd;
269      ARM_AM::ShiftOpc ShiftTy;
270      unsigned ShiftImm;
271    } PostIdxReg;
272
273    struct {
274      bool isASR;
275      unsigned Imm;
276    } ShifterImm;
277    struct {
278      ARM_AM::ShiftOpc ShiftTy;
279      unsigned SrcReg;
280      unsigned ShiftReg;
281      unsigned ShiftImm;
282    } RegShiftedReg;
283    struct {
284      ARM_AM::ShiftOpc ShiftTy;
285      unsigned SrcReg;
286      unsigned ShiftImm;
287    } RegShiftedImm;
288    struct {
289      unsigned Imm;
290    } RotImm;
291    struct {
292      unsigned LSB;
293      unsigned Width;
294    } Bitfield;
295  };
296
297  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
298public:
299  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
300    Kind = o.Kind;
301    StartLoc = o.StartLoc;
302    EndLoc = o.EndLoc;
303    switch (Kind) {
304    case CondCode:
305      CC = o.CC;
306      break;
307    case Token:
308      Tok = o.Tok;
309      break;
310    case CCOut:
311    case Register:
312      Reg = o.Reg;
313      break;
314    case RegisterList:
315    case DPRRegisterList:
316    case SPRRegisterList:
317      Registers = o.Registers;
318      break;
319    case CoprocNum:
320    case CoprocReg:
321      Cop = o.Cop;
322      break;
323    case Immediate:
324      Imm = o.Imm;
325      break;
326    case MemBarrierOpt:
327      MBOpt = o.MBOpt;
328      break;
329    case Memory:
330      Mem = o.Mem;
331      break;
332    case PostIndexRegister:
333      PostIdxReg = o.PostIdxReg;
334      break;
335    case MSRMask:
336      MMask = o.MMask;
337      break;
338    case ProcIFlags:
339      IFlags = o.IFlags;
340      break;
341    case ShifterImmediate:
342      ShifterImm = o.ShifterImm;
343      break;
344    case ShiftedRegister:
345      RegShiftedReg = o.RegShiftedReg;
346      break;
347    case ShiftedImmediate:
348      RegShiftedImm = o.RegShiftedImm;
349      break;
350    case RotateImmediate:
351      RotImm = o.RotImm;
352      break;
353    case BitfieldDescriptor:
354      Bitfield = o.Bitfield;
355      break;
356    }
357  }
358
359  /// getStartLoc - Get the location of the first token of this operand.
360  SMLoc getStartLoc() const { return StartLoc; }
361  /// getEndLoc - Get the location of the last token of this operand.
362  SMLoc getEndLoc() const { return EndLoc; }
363
364  ARMCC::CondCodes getCondCode() const {
365    assert(Kind == CondCode && "Invalid access!");
366    return CC.Val;
367  }
368
369  unsigned getCoproc() const {
370    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
371    return Cop.Val;
372  }
373
374  StringRef getToken() const {
375    assert(Kind == Token && "Invalid access!");
376    return StringRef(Tok.Data, Tok.Length);
377  }
378
379  unsigned getReg() const {
380    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
381    return Reg.RegNum;
382  }
383
384  const SmallVectorImpl<unsigned> &getRegList() const {
385    assert((Kind == RegisterList || Kind == DPRRegisterList ||
386            Kind == SPRRegisterList) && "Invalid access!");
387    return Registers;
388  }
389
390  const MCExpr *getImm() const {
391    assert(Kind == Immediate && "Invalid access!");
392    return Imm.Val;
393  }
394
395  ARM_MB::MemBOpt getMemBarrierOpt() const {
396    assert(Kind == MemBarrierOpt && "Invalid access!");
397    return MBOpt.Val;
398  }
399
400  ARM_PROC::IFlags getProcIFlags() const {
401    assert(Kind == ProcIFlags && "Invalid access!");
402    return IFlags.Val;
403  }
404
405  unsigned getMSRMask() const {
406    assert(Kind == MSRMask && "Invalid access!");
407    return MMask.Val;
408  }
409
410  bool isCoprocNum() const { return Kind == CoprocNum; }
411  bool isCoprocReg() const { return Kind == CoprocReg; }
412  bool isCondCode() const { return Kind == CondCode; }
413  bool isCCOut() const { return Kind == CCOut; }
414  bool isImm() const { return Kind == Immediate; }
415  bool isImm0_255() const {
416    if (Kind != Immediate)
417      return false;
418    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
419    if (!CE) return false;
420    int64_t Value = CE->getValue();
421    return Value >= 0 && Value < 256;
422  }
423  bool isImm0_7() const {
424    if (Kind != Immediate)
425      return false;
426    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
427    if (!CE) return false;
428    int64_t Value = CE->getValue();
429    return Value >= 0 && Value < 8;
430  }
431  bool isImm0_15() const {
432    if (Kind != Immediate)
433      return false;
434    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
435    if (!CE) return false;
436    int64_t Value = CE->getValue();
437    return Value >= 0 && Value < 16;
438  }
439  bool isImm0_31() const {
440    if (Kind != Immediate)
441      return false;
442    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
443    if (!CE) return false;
444    int64_t Value = CE->getValue();
445    return Value >= 0 && Value < 32;
446  }
447  bool isImm1_16() const {
448    if (Kind != Immediate)
449      return false;
450    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
451    if (!CE) return false;
452    int64_t Value = CE->getValue();
453    return Value > 0 && Value < 17;
454  }
455  bool isImm1_32() const {
456    if (Kind != Immediate)
457      return false;
458    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
459    if (!CE) return false;
460    int64_t Value = CE->getValue();
461    return Value > 0 && Value < 33;
462  }
463  bool isImm0_65535() const {
464    if (Kind != Immediate)
465      return false;
466    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
467    if (!CE) return false;
468    int64_t Value = CE->getValue();
469    return Value >= 0 && Value < 65536;
470  }
471  bool isImm0_65535Expr() const {
472    if (Kind != Immediate)
473      return false;
474    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
475    // If it's not a constant expression, it'll generate a fixup and be
476    // handled later.
477    if (!CE) return true;
478    int64_t Value = CE->getValue();
479    return Value >= 0 && Value < 65536;
480  }
481  bool isImm24bit() const {
482    if (Kind != Immediate)
483      return false;
484    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
485    if (!CE) return false;
486    int64_t Value = CE->getValue();
487    return Value >= 0 && Value <= 0xffffff;
488  }
489  bool isImmThumbSR() const {
490    if (Kind != Immediate)
491      return false;
492    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
493    if (!CE) return false;
494    int64_t Value = CE->getValue();
495    return Value > 0 && Value < 33;
496  }
497  bool isPKHLSLImm() const {
498    if (Kind != Immediate)
499      return false;
500    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
501    if (!CE) return false;
502    int64_t Value = CE->getValue();
503    return Value >= 0 && Value < 32;
504  }
505  bool isPKHASRImm() const {
506    if (Kind != Immediate)
507      return false;
508    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
509    if (!CE) return false;
510    int64_t Value = CE->getValue();
511    return Value > 0 && Value <= 32;
512  }
513  bool isARMSOImm() const {
514    if (Kind != Immediate)
515      return false;
516    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
517    if (!CE) return false;
518    int64_t Value = CE->getValue();
519    return ARM_AM::getSOImmVal(Value) != -1;
520  }
521  bool isT2SOImm() const {
522    if (Kind != Immediate)
523      return false;
524    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
525    if (!CE) return false;
526    int64_t Value = CE->getValue();
527    return ARM_AM::getT2SOImmVal(Value) != -1;
528  }
529  bool isSetEndImm() const {
530    if (Kind != Immediate)
531      return false;
532    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
533    if (!CE) return false;
534    int64_t Value = CE->getValue();
535    return Value == 1 || Value == 0;
536  }
537  bool isReg() const { return Kind == Register; }
538  bool isRegList() const { return Kind == RegisterList; }
539  bool isDPRRegList() const { return Kind == DPRRegisterList; }
540  bool isSPRRegList() const { return Kind == SPRRegisterList; }
541  bool isToken() const { return Kind == Token; }
542  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
543  bool isMemory() const { return Kind == Memory; }
544  bool isShifterImm() const { return Kind == ShifterImmediate; }
545  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
546  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
547  bool isRotImm() const { return Kind == RotateImmediate; }
548  bool isBitfield() const { return Kind == BitfieldDescriptor; }
549  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
550  bool isPostIdxReg() const {
551    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
552  }
553  bool isMemNoOffset() const {
554    if (Kind != Memory)
555      return false;
556    // No offset of any kind.
557    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
558  }
559  bool isAddrMode2() const {
560    if (Kind != Memory)
561      return false;
562    // Check for register offset.
563    if (Mem.OffsetRegNum) return true;
564    // Immediate offset in range [-4095, 4095].
565    if (!Mem.OffsetImm) return true;
566    int64_t Val = Mem.OffsetImm->getValue();
567    return Val > -4096 && Val < 4096;
568  }
569  bool isAM2OffsetImm() const {
570    if (Kind != Immediate)
571      return false;
572    // Immediate offset in range [-4095, 4095].
573    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
574    if (!CE) return false;
575    int64_t Val = CE->getValue();
576    return Val > -4096 && Val < 4096;
577  }
578  bool isAddrMode3() const {
579    if (Kind != Memory)
580      return false;
581    // No shifts are legal for AM3.
582    if (Mem.ShiftType != ARM_AM::no_shift) return false;
583    // Check for register offset.
584    if (Mem.OffsetRegNum) return true;
585    // Immediate offset in range [-255, 255].
586    if (!Mem.OffsetImm) return true;
587    int64_t Val = Mem.OffsetImm->getValue();
588    return Val > -256 && Val < 256;
589  }
590  bool isAM3Offset() const {
591    if (Kind != Immediate && Kind != PostIndexRegister)
592      return false;
593    if (Kind == PostIndexRegister)
594      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
595    // Immediate offset in range [-255, 255].
596    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
597    if (!CE) return false;
598    int64_t Val = CE->getValue();
599    // Special case, #-0 is INT32_MIN.
600    return (Val > -256 && Val < 256) || Val == INT32_MIN;
601  }
602  bool isAddrMode5() const {
603    if (Kind != Memory)
604      return false;
605    // Check for register offset.
606    if (Mem.OffsetRegNum) return false;
607    // Immediate offset in range [-1020, 1020] and a multiple of 4.
608    if (!Mem.OffsetImm) return true;
609    int64_t Val = Mem.OffsetImm->getValue();
610    return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
611  }
612  bool isMemRegOffset() const {
613    if (Kind != Memory || !Mem.OffsetRegNum)
614      return false;
615    return true;
616  }
617  bool isMemThumbRR() const {
618    // Thumb reg+reg addressing is simple. Just two registers, a base and
619    // an offset. No shifts, negations or any other complicating factors.
620    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
621        Mem.ShiftType != ARM_AM::no_shift)
622      return false;
623    return isARMLowRegister(Mem.BaseRegNum) &&
624      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
625  }
626  bool isMemThumbRIs4() const {
627    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
628        !isARMLowRegister(Mem.BaseRegNum))
629      return false;
630    // Immediate offset, multiple of 4 in range [0, 124].
631    if (!Mem.OffsetImm) return true;
632    int64_t Val = Mem.OffsetImm->getValue();
633    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
634  }
635  bool isMemThumbRIs2() const {
636    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
637        !isARMLowRegister(Mem.BaseRegNum))
638      return false;
639    // Immediate offset, multiple of 4 in range [0, 62].
640    if (!Mem.OffsetImm) return true;
641    int64_t Val = Mem.OffsetImm->getValue();
642    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
643  }
644  bool isMemThumbRIs1() const {
645    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
646        !isARMLowRegister(Mem.BaseRegNum))
647      return false;
648    // Immediate offset in range [0, 31].
649    if (!Mem.OffsetImm) return true;
650    int64_t Val = Mem.OffsetImm->getValue();
651    return Val >= 0 && Val <= 31;
652  }
653  bool isMemThumbSPI() const {
654    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
655      return false;
656    // Immediate offset, multiple of 4 in range [0, 1020].
657    if (!Mem.OffsetImm) return true;
658    int64_t Val = Mem.OffsetImm->getValue();
659    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
660  }
661  bool isMemImm8Offset() const {
662    if (Kind != Memory || Mem.OffsetRegNum != 0)
663      return false;
664    // Immediate offset in range [-255, 255].
665    if (!Mem.OffsetImm) return true;
666    int64_t Val = Mem.OffsetImm->getValue();
667    return Val > -256 && Val < 256;
668  }
669  bool isMemImm12Offset() const {
670    // If we have an immediate that's not a constant, treat it as a label
671    // reference needing a fixup. If it is a constant, it's something else
672    // and we reject it.
673    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
674      return true;
675
676    if (Kind != Memory || Mem.OffsetRegNum != 0)
677      return false;
678    // Immediate offset in range [-4095, 4095].
679    if (!Mem.OffsetImm) return true;
680    int64_t Val = Mem.OffsetImm->getValue();
681    return Val > -4096 && Val < 4096;
682  }
683  bool isPostIdxImm8() const {
684    if (Kind != Immediate)
685      return false;
686    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
687    if (!CE) return false;
688    int64_t Val = CE->getValue();
689    return Val > -256 && Val < 256;
690  }
691
692  bool isMSRMask() const { return Kind == MSRMask; }
693  bool isProcIFlags() const { return Kind == ProcIFlags; }
694
695  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
696    // Add as immediates when possible.  Null MCExpr = 0.
697    if (Expr == 0)
698      Inst.addOperand(MCOperand::CreateImm(0));
699    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
700      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
701    else
702      Inst.addOperand(MCOperand::CreateExpr(Expr));
703  }
704
705  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
706    assert(N == 2 && "Invalid number of operands!");
707    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
708    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
709    Inst.addOperand(MCOperand::CreateReg(RegNum));
710  }
711
712  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
713    assert(N == 1 && "Invalid number of operands!");
714    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
715  }
716
717  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
718    assert(N == 1 && "Invalid number of operands!");
719    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
720  }
721
722  void addCCOutOperands(MCInst &Inst, unsigned N) const {
723    assert(N == 1 && "Invalid number of operands!");
724    Inst.addOperand(MCOperand::CreateReg(getReg()));
725  }
726
727  void addRegOperands(MCInst &Inst, unsigned N) const {
728    assert(N == 1 && "Invalid number of operands!");
729    Inst.addOperand(MCOperand::CreateReg(getReg()));
730  }
731
732  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
733    assert(N == 3 && "Invalid number of operands!");
734    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
735    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
736    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
737    Inst.addOperand(MCOperand::CreateImm(
738      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
739  }
740
741  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
742    assert(N == 2 && "Invalid number of operands!");
743    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
744    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
745    Inst.addOperand(MCOperand::CreateImm(
746      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
747  }
748
749
750  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
751    assert(N == 1 && "Invalid number of operands!");
752    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
753                                         ShifterImm.Imm));
754  }
755
756  void addRegListOperands(MCInst &Inst, unsigned N) const {
757    assert(N == 1 && "Invalid number of operands!");
758    const SmallVectorImpl<unsigned> &RegList = getRegList();
759    for (SmallVectorImpl<unsigned>::const_iterator
760           I = RegList.begin(), E = RegList.end(); I != E; ++I)
761      Inst.addOperand(MCOperand::CreateReg(*I));
762  }
763
764  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
765    addRegListOperands(Inst, N);
766  }
767
768  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
769    addRegListOperands(Inst, N);
770  }
771
772  void addRotImmOperands(MCInst &Inst, unsigned N) const {
773    assert(N == 1 && "Invalid number of operands!");
774    // Encoded as val>>3. The printer handles display as 8, 16, 24.
775    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
776  }
777
778  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
779    assert(N == 1 && "Invalid number of operands!");
780    // Munge the lsb/width into a bitfield mask.
781    unsigned lsb = Bitfield.LSB;
782    unsigned width = Bitfield.Width;
783    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
784    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
785                      (32 - (lsb + width)));
786    Inst.addOperand(MCOperand::CreateImm(Mask));
787  }
788
789  void addImmOperands(MCInst &Inst, unsigned N) const {
790    assert(N == 1 && "Invalid number of operands!");
791    addExpr(Inst, getImm());
792  }
793
794  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
795    assert(N == 1 && "Invalid number of operands!");
796    addExpr(Inst, getImm());
797  }
798
799  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
800    assert(N == 1 && "Invalid number of operands!");
801    addExpr(Inst, getImm());
802  }
803
804  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
805    assert(N == 1 && "Invalid number of operands!");
806    addExpr(Inst, getImm());
807  }
808
809  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
810    assert(N == 1 && "Invalid number of operands!");
811    addExpr(Inst, getImm());
812  }
813
814  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
815    assert(N == 1 && "Invalid number of operands!");
816    // The constant encodes as the immediate-1, and we store in the instruction
817    // the bits as encoded, so subtract off one here.
818    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
819    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
820  }
821
822  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
823    assert(N == 1 && "Invalid number of operands!");
824    // The constant encodes as the immediate-1, and we store in the instruction
825    // the bits as encoded, so subtract off one here.
826    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
827    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
828  }
829
830  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
831    assert(N == 1 && "Invalid number of operands!");
832    addExpr(Inst, getImm());
833  }
834
835  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
836    assert(N == 1 && "Invalid number of operands!");
837    addExpr(Inst, getImm());
838  }
839
840  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
841    assert(N == 1 && "Invalid number of operands!");
842    addExpr(Inst, getImm());
843  }
844
845  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
846    assert(N == 1 && "Invalid number of operands!");
847    // The constant encodes as the immediate, except for 32, which encodes as
848    // zero.
849    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
850    unsigned Imm = CE->getValue();
851    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
852  }
853
854  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
855    assert(N == 1 && "Invalid number of operands!");
856    addExpr(Inst, getImm());
857  }
858
859  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
860    assert(N == 1 && "Invalid number of operands!");
861    // An ASR value of 32 encodes as 0, so that's how we want to add it to
862    // the instruction as well.
863    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
864    int Val = CE->getValue();
865    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
866  }
867
868  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
869    assert(N == 1 && "Invalid number of operands!");
870    addExpr(Inst, getImm());
871  }
872
873  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
874    assert(N == 1 && "Invalid number of operands!");
875    addExpr(Inst, getImm());
876  }
877
878  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
879    assert(N == 1 && "Invalid number of operands!");
880    addExpr(Inst, getImm());
881  }
882
883  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
884    assert(N == 1 && "Invalid number of operands!");
885    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
886  }
887
888  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
889    assert(N == 1 && "Invalid number of operands!");
890    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
891  }
892
893  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
894    assert(N == 3 && "Invalid number of operands!");
895    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
896    if (!Mem.OffsetRegNum) {
897      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
898      // Special case for #-0
899      if (Val == INT32_MIN) Val = 0;
900      if (Val < 0) Val = -Val;
901      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
902    } else {
903      // For register offset, we encode the shift type and negation flag
904      // here.
905      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
906                              Mem.ShiftImm, Mem.ShiftType);
907    }
908    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
909    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
910    Inst.addOperand(MCOperand::CreateImm(Val));
911  }
912
913  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
914    assert(N == 2 && "Invalid number of operands!");
915    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
916    assert(CE && "non-constant AM2OffsetImm operand!");
917    int32_t Val = CE->getValue();
918    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
919    // Special case for #-0
920    if (Val == INT32_MIN) Val = 0;
921    if (Val < 0) Val = -Val;
922    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
923    Inst.addOperand(MCOperand::CreateReg(0));
924    Inst.addOperand(MCOperand::CreateImm(Val));
925  }
926
927  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
928    assert(N == 3 && "Invalid number of operands!");
929    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
930    if (!Mem.OffsetRegNum) {
931      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
932      // Special case for #-0
933      if (Val == INT32_MIN) Val = 0;
934      if (Val < 0) Val = -Val;
935      Val = ARM_AM::getAM3Opc(AddSub, Val);
936    } else {
937      // For register offset, we encode the shift type and negation flag
938      // here.
939      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
940    }
941    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
942    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
943    Inst.addOperand(MCOperand::CreateImm(Val));
944  }
945
946  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
947    assert(N == 2 && "Invalid number of operands!");
948    if (Kind == PostIndexRegister) {
949      int32_t Val =
950        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
951      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
952      Inst.addOperand(MCOperand::CreateImm(Val));
953      return;
954    }
955
956    // Constant offset.
957    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
958    int32_t Val = CE->getValue();
959    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
960    // Special case for #-0
961    if (Val == INT32_MIN) Val = 0;
962    if (Val < 0) Val = -Val;
963    Val = ARM_AM::getAM3Opc(AddSub, Val);
964    Inst.addOperand(MCOperand::CreateReg(0));
965    Inst.addOperand(MCOperand::CreateImm(Val));
966  }
967
968  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
969    assert(N == 2 && "Invalid number of operands!");
970    // The lower two bits are always zero and as such are not encoded.
971    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
972    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
973    // Special case for #-0
974    if (Val == INT32_MIN) Val = 0;
975    if (Val < 0) Val = -Val;
976    Val = ARM_AM::getAM5Opc(AddSub, Val);
977    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
978    Inst.addOperand(MCOperand::CreateImm(Val));
979  }
980
981  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
982    assert(N == 2 && "Invalid number of operands!");
983    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
984    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
985    Inst.addOperand(MCOperand::CreateImm(Val));
986  }
987
988  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
989    assert(N == 2 && "Invalid number of operands!");
990    // If this is an immediate, it's a label reference.
991    if (Kind == Immediate) {
992      addExpr(Inst, getImm());
993      Inst.addOperand(MCOperand::CreateImm(0));
994      return;
995    }
996
997    // Otherwise, it's a normal memory reg+offset.
998    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
999    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1000    Inst.addOperand(MCOperand::CreateImm(Val));
1001  }
1002
1003  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1004    assert(N == 3 && "Invalid number of operands!");
1005    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1006                                     Mem.ShiftImm, Mem.ShiftType);
1007    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1008    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1009    Inst.addOperand(MCOperand::CreateImm(Val));
1010  }
1011
1012  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1013    assert(N == 2 && "Invalid number of operands!");
1014    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1015    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1016  }
1017
1018  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1019    assert(N == 2 && "Invalid number of operands!");
1020    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1021    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1022    Inst.addOperand(MCOperand::CreateImm(Val));
1023  }
1024
1025  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1026    assert(N == 2 && "Invalid number of operands!");
1027    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1028    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1029    Inst.addOperand(MCOperand::CreateImm(Val));
1030  }
1031
1032  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1033    assert(N == 2 && "Invalid number of operands!");
1034    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1035    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1036    Inst.addOperand(MCOperand::CreateImm(Val));
1037  }
1038
1039  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1040    assert(N == 2 && "Invalid number of operands!");
1041    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1042    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1043    Inst.addOperand(MCOperand::CreateImm(Val));
1044  }
1045
1046  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1047    assert(N == 1 && "Invalid number of operands!");
1048    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1049    assert(CE && "non-constant post-idx-imm8 operand!");
1050    int Imm = CE->getValue();
1051    bool isAdd = Imm >= 0;
1052    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1053    Inst.addOperand(MCOperand::CreateImm(Imm));
1054  }
1055
1056  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1057    assert(N == 2 && "Invalid number of operands!");
1058    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1059    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1060  }
1061
1062  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1063    assert(N == 2 && "Invalid number of operands!");
1064    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1065    // The sign, shift type, and shift amount are encoded in a single operand
1066    // using the AM2 encoding helpers.
1067    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1068    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1069                                     PostIdxReg.ShiftTy);
1070    Inst.addOperand(MCOperand::CreateImm(Imm));
1071  }
1072
1073  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1074    assert(N == 1 && "Invalid number of operands!");
1075    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1076  }
1077
1078  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1079    assert(N == 1 && "Invalid number of operands!");
1080    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1081  }
1082
1083  virtual void print(raw_ostream &OS) const;
1084
1085  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1086    ARMOperand *Op = new ARMOperand(CondCode);
1087    Op->CC.Val = CC;
1088    Op->StartLoc = S;
1089    Op->EndLoc = S;
1090    return Op;
1091  }
1092
1093  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1094    ARMOperand *Op = new ARMOperand(CoprocNum);
1095    Op->Cop.Val = CopVal;
1096    Op->StartLoc = S;
1097    Op->EndLoc = S;
1098    return Op;
1099  }
1100
1101  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1102    ARMOperand *Op = new ARMOperand(CoprocReg);
1103    Op->Cop.Val = CopVal;
1104    Op->StartLoc = S;
1105    Op->EndLoc = S;
1106    return Op;
1107  }
1108
1109  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1110    ARMOperand *Op = new ARMOperand(CCOut);
1111    Op->Reg.RegNum = RegNum;
1112    Op->StartLoc = S;
1113    Op->EndLoc = S;
1114    return Op;
1115  }
1116
1117  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1118    ARMOperand *Op = new ARMOperand(Token);
1119    Op->Tok.Data = Str.data();
1120    Op->Tok.Length = Str.size();
1121    Op->StartLoc = S;
1122    Op->EndLoc = S;
1123    return Op;
1124  }
1125
1126  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1127    ARMOperand *Op = new ARMOperand(Register);
1128    Op->Reg.RegNum = RegNum;
1129    Op->StartLoc = S;
1130    Op->EndLoc = E;
1131    return Op;
1132  }
1133
1134  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1135                                           unsigned SrcReg,
1136                                           unsigned ShiftReg,
1137                                           unsigned ShiftImm,
1138                                           SMLoc S, SMLoc E) {
1139    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1140    Op->RegShiftedReg.ShiftTy = ShTy;
1141    Op->RegShiftedReg.SrcReg = SrcReg;
1142    Op->RegShiftedReg.ShiftReg = ShiftReg;
1143    Op->RegShiftedReg.ShiftImm = ShiftImm;
1144    Op->StartLoc = S;
1145    Op->EndLoc = E;
1146    return Op;
1147  }
1148
1149  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1150                                            unsigned SrcReg,
1151                                            unsigned ShiftImm,
1152                                            SMLoc S, SMLoc E) {
1153    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1154    Op->RegShiftedImm.ShiftTy = ShTy;
1155    Op->RegShiftedImm.SrcReg = SrcReg;
1156    Op->RegShiftedImm.ShiftImm = ShiftImm;
1157    Op->StartLoc = S;
1158    Op->EndLoc = E;
1159    return Op;
1160  }
1161
1162  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1163                                   SMLoc S, SMLoc E) {
1164    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1165    Op->ShifterImm.isASR = isASR;
1166    Op->ShifterImm.Imm = Imm;
1167    Op->StartLoc = S;
1168    Op->EndLoc = E;
1169    return Op;
1170  }
1171
1172  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1173    ARMOperand *Op = new ARMOperand(RotateImmediate);
1174    Op->RotImm.Imm = Imm;
1175    Op->StartLoc = S;
1176    Op->EndLoc = E;
1177    return Op;
1178  }
1179
1180  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1181                                    SMLoc S, SMLoc E) {
1182    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1183    Op->Bitfield.LSB = LSB;
1184    Op->Bitfield.Width = Width;
1185    Op->StartLoc = S;
1186    Op->EndLoc = E;
1187    return Op;
1188  }
1189
1190  static ARMOperand *
1191  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1192                SMLoc StartLoc, SMLoc EndLoc) {
1193    KindTy Kind = RegisterList;
1194
1195    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1196        contains(Regs.front().first))
1197      Kind = DPRRegisterList;
1198    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1199             contains(Regs.front().first))
1200      Kind = SPRRegisterList;
1201
1202    ARMOperand *Op = new ARMOperand(Kind);
1203    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1204           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1205      Op->Registers.push_back(I->first);
1206    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1207    Op->StartLoc = StartLoc;
1208    Op->EndLoc = EndLoc;
1209    return Op;
1210  }
1211
1212  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1213    ARMOperand *Op = new ARMOperand(Immediate);
1214    Op->Imm.Val = Val;
1215    Op->StartLoc = S;
1216    Op->EndLoc = E;
1217    return Op;
1218  }
1219
1220  static ARMOperand *CreateMem(unsigned BaseRegNum,
1221                               const MCConstantExpr *OffsetImm,
1222                               unsigned OffsetRegNum,
1223                               ARM_AM::ShiftOpc ShiftType,
1224                               unsigned ShiftImm,
1225                               bool isNegative,
1226                               SMLoc S, SMLoc E) {
1227    ARMOperand *Op = new ARMOperand(Memory);
1228    Op->Mem.BaseRegNum = BaseRegNum;
1229    Op->Mem.OffsetImm = OffsetImm;
1230    Op->Mem.OffsetRegNum = OffsetRegNum;
1231    Op->Mem.ShiftType = ShiftType;
1232    Op->Mem.ShiftImm = ShiftImm;
1233    Op->Mem.isNegative = isNegative;
1234    Op->StartLoc = S;
1235    Op->EndLoc = E;
1236    return Op;
1237  }
1238
1239  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1240                                      ARM_AM::ShiftOpc ShiftTy,
1241                                      unsigned ShiftImm,
1242                                      SMLoc S, SMLoc E) {
1243    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1244    Op->PostIdxReg.RegNum = RegNum;
1245    Op->PostIdxReg.isAdd = isAdd;
1246    Op->PostIdxReg.ShiftTy = ShiftTy;
1247    Op->PostIdxReg.ShiftImm = ShiftImm;
1248    Op->StartLoc = S;
1249    Op->EndLoc = E;
1250    return Op;
1251  }
1252
1253  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1254    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1255    Op->MBOpt.Val = Opt;
1256    Op->StartLoc = S;
1257    Op->EndLoc = S;
1258    return Op;
1259  }
1260
1261  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1262    ARMOperand *Op = new ARMOperand(ProcIFlags);
1263    Op->IFlags.Val = IFlags;
1264    Op->StartLoc = S;
1265    Op->EndLoc = S;
1266    return Op;
1267  }
1268
1269  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1270    ARMOperand *Op = new ARMOperand(MSRMask);
1271    Op->MMask.Val = MMask;
1272    Op->StartLoc = S;
1273    Op->EndLoc = S;
1274    return Op;
1275  }
1276};
1277
1278} // end anonymous namespace.
1279
1280void ARMOperand::print(raw_ostream &OS) const {
1281  switch (Kind) {
1282  case CondCode:
1283    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1284    break;
1285  case CCOut:
1286    OS << "<ccout " << getReg() << ">";
1287    break;
1288  case CoprocNum:
1289    OS << "<coprocessor number: " << getCoproc() << ">";
1290    break;
1291  case CoprocReg:
1292    OS << "<coprocessor register: " << getCoproc() << ">";
1293    break;
1294  case MSRMask:
1295    OS << "<mask: " << getMSRMask() << ">";
1296    break;
1297  case Immediate:
1298    getImm()->print(OS);
1299    break;
1300  case MemBarrierOpt:
1301    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1302    break;
1303  case Memory:
1304    OS << "<memory "
1305       << " base:" << Mem.BaseRegNum;
1306    OS << ">";
1307    break;
1308  case PostIndexRegister:
1309    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1310       << PostIdxReg.RegNum;
1311    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1312      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1313         << PostIdxReg.ShiftImm;
1314    OS << ">";
1315    break;
1316  case ProcIFlags: {
1317    OS << "<ARM_PROC::";
1318    unsigned IFlags = getProcIFlags();
1319    for (int i=2; i >= 0; --i)
1320      if (IFlags & (1 << i))
1321        OS << ARM_PROC::IFlagsToString(1 << i);
1322    OS << ">";
1323    break;
1324  }
1325  case Register:
1326    OS << "<register " << getReg() << ">";
1327    break;
1328  case ShifterImmediate:
1329    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1330       << " #" << ShifterImm.Imm << ">";
1331    break;
1332  case ShiftedRegister:
1333    OS << "<so_reg_reg "
1334       << RegShiftedReg.SrcReg
1335       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1336       << ", " << RegShiftedReg.ShiftReg << ", "
1337       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1338       << ">";
1339    break;
1340  case ShiftedImmediate:
1341    OS << "<so_reg_imm "
1342       << RegShiftedImm.SrcReg
1343       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1344       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1345       << ">";
1346    break;
1347  case RotateImmediate:
1348    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1349    break;
1350  case BitfieldDescriptor:
1351    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1352       << ", width: " << Bitfield.Width << ">";
1353    break;
1354  case RegisterList:
1355  case DPRRegisterList:
1356  case SPRRegisterList: {
1357    OS << "<register_list ";
1358
1359    const SmallVectorImpl<unsigned> &RegList = getRegList();
1360    for (SmallVectorImpl<unsigned>::const_iterator
1361           I = RegList.begin(), E = RegList.end(); I != E; ) {
1362      OS << *I;
1363      if (++I < E) OS << ", ";
1364    }
1365
1366    OS << ">";
1367    break;
1368  }
1369  case Token:
1370    OS << "'" << getToken() << "'";
1371    break;
1372  }
1373}
1374
1375/// @name Auto-generated Match Functions
1376/// {
1377
1378static unsigned MatchRegisterName(StringRef Name);
1379
1380/// }
1381
1382bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1383                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1384  RegNo = tryParseRegister();
1385
1386  return (RegNo == (unsigned)-1);
1387}
1388
1389/// Try to parse a register name.  The token must be an Identifier when called,
1390/// and if it is a register name the token is eaten and the register number is
1391/// returned.  Otherwise return -1.
1392///
1393int ARMAsmParser::tryParseRegister() {
1394  const AsmToken &Tok = Parser.getTok();
1395  if (Tok.isNot(AsmToken::Identifier)) return -1;
1396
1397  // FIXME: Validate register for the current architecture; we have to do
1398  // validation later, so maybe there is no need for this here.
1399  std::string upperCase = Tok.getString().str();
1400  std::string lowerCase = LowercaseString(upperCase);
1401  unsigned RegNum = MatchRegisterName(lowerCase);
1402  if (!RegNum) {
1403    RegNum = StringSwitch<unsigned>(lowerCase)
1404      .Case("r13", ARM::SP)
1405      .Case("r14", ARM::LR)
1406      .Case("r15", ARM::PC)
1407      .Case("ip", ARM::R12)
1408      .Default(0);
1409  }
1410  if (!RegNum) return -1;
1411
1412  Parser.Lex(); // Eat identifier token.
1413  return RegNum;
1414}
1415
1416// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1417// If a recoverable error occurs, return 1. If an irrecoverable error
1418// occurs, return -1. An irrecoverable error is one where tokens have been
1419// consumed in the process of trying to parse the shifter (i.e., when it is
1420// indeed a shifter operand, but malformed).
1421int ARMAsmParser::tryParseShiftRegister(
1422                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1423  SMLoc S = Parser.getTok().getLoc();
1424  const AsmToken &Tok = Parser.getTok();
1425  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1426
1427  std::string upperCase = Tok.getString().str();
1428  std::string lowerCase = LowercaseString(upperCase);
1429  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1430      .Case("lsl", ARM_AM::lsl)
1431      .Case("lsr", ARM_AM::lsr)
1432      .Case("asr", ARM_AM::asr)
1433      .Case("ror", ARM_AM::ror)
1434      .Case("rrx", ARM_AM::rrx)
1435      .Default(ARM_AM::no_shift);
1436
1437  if (ShiftTy == ARM_AM::no_shift)
1438    return 1;
1439
1440  Parser.Lex(); // Eat the operator.
1441
1442  // The source register for the shift has already been added to the
1443  // operand list, so we need to pop it off and combine it into the shifted
1444  // register operand instead.
1445  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1446  if (!PrevOp->isReg())
1447    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1448  int SrcReg = PrevOp->getReg();
1449  int64_t Imm = 0;
1450  int ShiftReg = 0;
1451  if (ShiftTy == ARM_AM::rrx) {
1452    // RRX Doesn't have an explicit shift amount. The encoder expects
1453    // the shift register to be the same as the source register. Seems odd,
1454    // but OK.
1455    ShiftReg = SrcReg;
1456  } else {
1457    // Figure out if this is shifted by a constant or a register (for non-RRX).
1458    if (Parser.getTok().is(AsmToken::Hash)) {
1459      Parser.Lex(); // Eat hash.
1460      SMLoc ImmLoc = Parser.getTok().getLoc();
1461      const MCExpr *ShiftExpr = 0;
1462      if (getParser().ParseExpression(ShiftExpr)) {
1463        Error(ImmLoc, "invalid immediate shift value");
1464        return -1;
1465      }
1466      // The expression must be evaluatable as an immediate.
1467      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1468      if (!CE) {
1469        Error(ImmLoc, "invalid immediate shift value");
1470        return -1;
1471      }
1472      // Range check the immediate.
1473      // lsl, ror: 0 <= imm <= 31
1474      // lsr, asr: 0 <= imm <= 32
1475      Imm = CE->getValue();
1476      if (Imm < 0 ||
1477          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1478          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1479        Error(ImmLoc, "immediate shift value out of range");
1480        return -1;
1481      }
1482    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1483      ShiftReg = tryParseRegister();
1484      SMLoc L = Parser.getTok().getLoc();
1485      if (ShiftReg == -1) {
1486        Error (L, "expected immediate or register in shift operand");
1487        return -1;
1488      }
1489    } else {
1490      Error (Parser.getTok().getLoc(),
1491                    "expected immediate or register in shift operand");
1492      return -1;
1493    }
1494  }
1495
1496  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1497    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1498                                                         ShiftReg, Imm,
1499                                               S, Parser.getTok().getLoc()));
1500  else
1501    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1502                                               S, Parser.getTok().getLoc()));
1503
1504  return 0;
1505}
1506
1507
1508/// Try to parse a register name.  The token must be an Identifier when called.
1509/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1510/// if there is a "writeback". 'true' if it's not a register.
1511///
1512/// TODO this is likely to change to allow different register types and or to
1513/// parse for a specific register type.
1514bool ARMAsmParser::
1515tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1516  SMLoc S = Parser.getTok().getLoc();
1517  int RegNo = tryParseRegister();
1518  if (RegNo == -1)
1519    return true;
1520
1521  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1522
1523  const AsmToken &ExclaimTok = Parser.getTok();
1524  if (ExclaimTok.is(AsmToken::Exclaim)) {
1525    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1526                                               ExclaimTok.getLoc()));
1527    Parser.Lex(); // Eat exclaim token
1528  }
1529
1530  return false;
1531}
1532
1533/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1534/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1535/// "c5", ...
1536static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1537  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1538  // but efficient.
1539  switch (Name.size()) {
1540  default: break;
1541  case 2:
1542    if (Name[0] != CoprocOp)
1543      return -1;
1544    switch (Name[1]) {
1545    default:  return -1;
1546    case '0': return 0;
1547    case '1': return 1;
1548    case '2': return 2;
1549    case '3': return 3;
1550    case '4': return 4;
1551    case '5': return 5;
1552    case '6': return 6;
1553    case '7': return 7;
1554    case '8': return 8;
1555    case '9': return 9;
1556    }
1557    break;
1558  case 3:
1559    if (Name[0] != CoprocOp || Name[1] != '1')
1560      return -1;
1561    switch (Name[2]) {
1562    default:  return -1;
1563    case '0': return 10;
1564    case '1': return 11;
1565    case '2': return 12;
1566    case '3': return 13;
1567    case '4': return 14;
1568    case '5': return 15;
1569    }
1570    break;
1571  }
1572
1573  return -1;
1574}
1575
1576/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1577/// token must be an Identifier when called, and if it is a coprocessor
1578/// number, the token is eaten and the operand is added to the operand list.
1579ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1580parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1581  SMLoc S = Parser.getTok().getLoc();
1582  const AsmToken &Tok = Parser.getTok();
1583  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1584
1585  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1586  if (Num == -1)
1587    return MatchOperand_NoMatch;
1588
1589  Parser.Lex(); // Eat identifier token.
1590  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1591  return MatchOperand_Success;
1592}
1593
1594/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1595/// token must be an Identifier when called, and if it is a coprocessor
1596/// number, the token is eaten and the operand is added to the operand list.
1597ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1598parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1599  SMLoc S = Parser.getTok().getLoc();
1600  const AsmToken &Tok = Parser.getTok();
1601  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1602
1603  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1604  if (Reg == -1)
1605    return MatchOperand_NoMatch;
1606
1607  Parser.Lex(); // Eat identifier token.
1608  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1609  return MatchOperand_Success;
1610}
1611
1612/// Parse a register list, return it if successful else return null.  The first
1613/// token must be a '{' when called.
1614bool ARMAsmParser::
1615parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1616  assert(Parser.getTok().is(AsmToken::LCurly) &&
1617         "Token is not a Left Curly Brace");
1618  SMLoc S = Parser.getTok().getLoc();
1619
1620  // Read the rest of the registers in the list.
1621  unsigned PrevRegNum = 0;
1622  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1623
1624  do {
1625    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1626    Parser.Lex(); // Eat non-identifier token.
1627
1628    const AsmToken &RegTok = Parser.getTok();
1629    SMLoc RegLoc = RegTok.getLoc();
1630    if (RegTok.isNot(AsmToken::Identifier)) {
1631      Error(RegLoc, "register expected");
1632      return true;
1633    }
1634
1635    int RegNum = tryParseRegister();
1636    if (RegNum == -1) {
1637      Error(RegLoc, "register expected");
1638      return true;
1639    }
1640
1641    if (IsRange) {
1642      int Reg = PrevRegNum;
1643      do {
1644        ++Reg;
1645        Registers.push_back(std::make_pair(Reg, RegLoc));
1646      } while (Reg != RegNum);
1647    } else {
1648      Registers.push_back(std::make_pair(RegNum, RegLoc));
1649    }
1650
1651    PrevRegNum = RegNum;
1652  } while (Parser.getTok().is(AsmToken::Comma) ||
1653           Parser.getTok().is(AsmToken::Minus));
1654
1655  // Process the right curly brace of the list.
1656  const AsmToken &RCurlyTok = Parser.getTok();
1657  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1658    Error(RCurlyTok.getLoc(), "'}' expected");
1659    return true;
1660  }
1661
1662  SMLoc E = RCurlyTok.getLoc();
1663  Parser.Lex(); // Eat right curly brace token.
1664
1665  // Verify the register list.
1666  bool EmittedWarning = false;
1667  unsigned HighRegNum = 0;
1668  BitVector RegMap(32);
1669  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1670    const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1671    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1672
1673    if (RegMap[Reg]) {
1674      Error(RegInfo.second, "register duplicated in register list");
1675      return true;
1676    }
1677
1678    if (!EmittedWarning && Reg < HighRegNum)
1679      Warning(RegInfo.second,
1680              "register not in ascending order in register list");
1681
1682    RegMap.set(Reg);
1683    HighRegNum = std::max(Reg, HighRegNum);
1684  }
1685
1686  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1687  return false;
1688}
1689
1690/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1691ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1692parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1693  SMLoc S = Parser.getTok().getLoc();
1694  const AsmToken &Tok = Parser.getTok();
1695  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1696  StringRef OptStr = Tok.getString();
1697
1698  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1699    .Case("sy",    ARM_MB::SY)
1700    .Case("st",    ARM_MB::ST)
1701    .Case("sh",    ARM_MB::ISH)
1702    .Case("ish",   ARM_MB::ISH)
1703    .Case("shst",  ARM_MB::ISHST)
1704    .Case("ishst", ARM_MB::ISHST)
1705    .Case("nsh",   ARM_MB::NSH)
1706    .Case("un",    ARM_MB::NSH)
1707    .Case("nshst", ARM_MB::NSHST)
1708    .Case("unst",  ARM_MB::NSHST)
1709    .Case("osh",   ARM_MB::OSH)
1710    .Case("oshst", ARM_MB::OSHST)
1711    .Default(~0U);
1712
1713  if (Opt == ~0U)
1714    return MatchOperand_NoMatch;
1715
1716  Parser.Lex(); // Eat identifier token.
1717  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1718  return MatchOperand_Success;
1719}
1720
1721/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1722ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1723parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1724  SMLoc S = Parser.getTok().getLoc();
1725  const AsmToken &Tok = Parser.getTok();
1726  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1727  StringRef IFlagsStr = Tok.getString();
1728
1729  unsigned IFlags = 0;
1730  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1731    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1732    .Case("a", ARM_PROC::A)
1733    .Case("i", ARM_PROC::I)
1734    .Case("f", ARM_PROC::F)
1735    .Default(~0U);
1736
1737    // If some specific iflag is already set, it means that some letter is
1738    // present more than once, this is not acceptable.
1739    if (Flag == ~0U || (IFlags & Flag))
1740      return MatchOperand_NoMatch;
1741
1742    IFlags |= Flag;
1743  }
1744
1745  Parser.Lex(); // Eat identifier token.
1746  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1747  return MatchOperand_Success;
1748}
1749
1750/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1751ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1752parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1753  SMLoc S = Parser.getTok().getLoc();
1754  const AsmToken &Tok = Parser.getTok();
1755  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1756  StringRef Mask = Tok.getString();
1757
1758  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1759  size_t Start = 0, Next = Mask.find('_');
1760  StringRef Flags = "";
1761  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1762  if (Next != StringRef::npos)
1763    Flags = Mask.slice(Next+1, Mask.size());
1764
1765  // FlagsVal contains the complete mask:
1766  // 3-0: Mask
1767  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1768  unsigned FlagsVal = 0;
1769
1770  if (SpecReg == "apsr") {
1771    FlagsVal = StringSwitch<unsigned>(Flags)
1772    .Case("nzcvq",  0x8) // same as CPSR_f
1773    .Case("g",      0x4) // same as CPSR_s
1774    .Case("nzcvqg", 0xc) // same as CPSR_fs
1775    .Default(~0U);
1776
1777    if (FlagsVal == ~0U) {
1778      if (!Flags.empty())
1779        return MatchOperand_NoMatch;
1780      else
1781        FlagsVal = 0; // No flag
1782    }
1783  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1784    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1785      Flags = "fc";
1786    for (int i = 0, e = Flags.size(); i != e; ++i) {
1787      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1788      .Case("c", 1)
1789      .Case("x", 2)
1790      .Case("s", 4)
1791      .Case("f", 8)
1792      .Default(~0U);
1793
1794      // If some specific flag is already set, it means that some letter is
1795      // present more than once, this is not acceptable.
1796      if (FlagsVal == ~0U || (FlagsVal & Flag))
1797        return MatchOperand_NoMatch;
1798      FlagsVal |= Flag;
1799    }
1800  } else // No match for special register.
1801    return MatchOperand_NoMatch;
1802
1803  // Special register without flags are equivalent to "fc" flags.
1804  if (!FlagsVal)
1805    FlagsVal = 0x9;
1806
1807  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1808  if (SpecReg == "spsr")
1809    FlagsVal |= 16;
1810
1811  Parser.Lex(); // Eat identifier token.
1812  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1813  return MatchOperand_Success;
1814}
1815
1816ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1817parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1818            int Low, int High) {
1819  const AsmToken &Tok = Parser.getTok();
1820  if (Tok.isNot(AsmToken::Identifier)) {
1821    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1822    return MatchOperand_ParseFail;
1823  }
1824  StringRef ShiftName = Tok.getString();
1825  std::string LowerOp = LowercaseString(Op);
1826  std::string UpperOp = UppercaseString(Op);
1827  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1828    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1829    return MatchOperand_ParseFail;
1830  }
1831  Parser.Lex(); // Eat shift type token.
1832
1833  // There must be a '#' and a shift amount.
1834  if (Parser.getTok().isNot(AsmToken::Hash)) {
1835    Error(Parser.getTok().getLoc(), "'#' expected");
1836    return MatchOperand_ParseFail;
1837  }
1838  Parser.Lex(); // Eat hash token.
1839
1840  const MCExpr *ShiftAmount;
1841  SMLoc Loc = Parser.getTok().getLoc();
1842  if (getParser().ParseExpression(ShiftAmount)) {
1843    Error(Loc, "illegal expression");
1844    return MatchOperand_ParseFail;
1845  }
1846  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1847  if (!CE) {
1848    Error(Loc, "constant expression expected");
1849    return MatchOperand_ParseFail;
1850  }
1851  int Val = CE->getValue();
1852  if (Val < Low || Val > High) {
1853    Error(Loc, "immediate value out of range");
1854    return MatchOperand_ParseFail;
1855  }
1856
1857  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1858
1859  return MatchOperand_Success;
1860}
1861
1862ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1863parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1864  const AsmToken &Tok = Parser.getTok();
1865  SMLoc S = Tok.getLoc();
1866  if (Tok.isNot(AsmToken::Identifier)) {
1867    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1868    return MatchOperand_ParseFail;
1869  }
1870  int Val = StringSwitch<int>(Tok.getString())
1871    .Case("be", 1)
1872    .Case("le", 0)
1873    .Default(-1);
1874  Parser.Lex(); // Eat the token.
1875
1876  if (Val == -1) {
1877    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1878    return MatchOperand_ParseFail;
1879  }
1880  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1881                                                                  getContext()),
1882                                           S, Parser.getTok().getLoc()));
1883  return MatchOperand_Success;
1884}
1885
1886/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1887/// instructions. Legal values are:
1888///     lsl #n  'n' in [0,31]
1889///     asr #n  'n' in [1,32]
1890///             n == 32 encoded as n == 0.
1891ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1892parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1893  const AsmToken &Tok = Parser.getTok();
1894  SMLoc S = Tok.getLoc();
1895  if (Tok.isNot(AsmToken::Identifier)) {
1896    Error(S, "shift operator 'asr' or 'lsl' expected");
1897    return MatchOperand_ParseFail;
1898  }
1899  StringRef ShiftName = Tok.getString();
1900  bool isASR;
1901  if (ShiftName == "lsl" || ShiftName == "LSL")
1902    isASR = false;
1903  else if (ShiftName == "asr" || ShiftName == "ASR")
1904    isASR = true;
1905  else {
1906    Error(S, "shift operator 'asr' or 'lsl' expected");
1907    return MatchOperand_ParseFail;
1908  }
1909  Parser.Lex(); // Eat the operator.
1910
1911  // A '#' and a shift amount.
1912  if (Parser.getTok().isNot(AsmToken::Hash)) {
1913    Error(Parser.getTok().getLoc(), "'#' expected");
1914    return MatchOperand_ParseFail;
1915  }
1916  Parser.Lex(); // Eat hash token.
1917
1918  const MCExpr *ShiftAmount;
1919  SMLoc E = Parser.getTok().getLoc();
1920  if (getParser().ParseExpression(ShiftAmount)) {
1921    Error(E, "malformed shift expression");
1922    return MatchOperand_ParseFail;
1923  }
1924  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1925  if (!CE) {
1926    Error(E, "shift amount must be an immediate");
1927    return MatchOperand_ParseFail;
1928  }
1929
1930  int64_t Val = CE->getValue();
1931  if (isASR) {
1932    // Shift amount must be in [1,32]
1933    if (Val < 1 || Val > 32) {
1934      Error(E, "'asr' shift amount must be in range [1,32]");
1935      return MatchOperand_ParseFail;
1936    }
1937    // asr #32 encoded as asr #0.
1938    if (Val == 32) Val = 0;
1939  } else {
1940    // Shift amount must be in [1,32]
1941    if (Val < 0 || Val > 31) {
1942      Error(E, "'lsr' shift amount must be in range [0,31]");
1943      return MatchOperand_ParseFail;
1944    }
1945  }
1946
1947  E = Parser.getTok().getLoc();
1948  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1949
1950  return MatchOperand_Success;
1951}
1952
1953/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1954/// of instructions. Legal values are:
1955///     ror #n  'n' in {0, 8, 16, 24}
1956ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1957parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1958  const AsmToken &Tok = Parser.getTok();
1959  SMLoc S = Tok.getLoc();
1960  if (Tok.isNot(AsmToken::Identifier)) {
1961    Error(S, "rotate operator 'ror' expected");
1962    return MatchOperand_ParseFail;
1963  }
1964  StringRef ShiftName = Tok.getString();
1965  if (ShiftName != "ror" && ShiftName != "ROR") {
1966    Error(S, "rotate operator 'ror' expected");
1967    return MatchOperand_ParseFail;
1968  }
1969  Parser.Lex(); // Eat the operator.
1970
1971  // A '#' and a rotate amount.
1972  if (Parser.getTok().isNot(AsmToken::Hash)) {
1973    Error(Parser.getTok().getLoc(), "'#' expected");
1974    return MatchOperand_ParseFail;
1975  }
1976  Parser.Lex(); // Eat hash token.
1977
1978  const MCExpr *ShiftAmount;
1979  SMLoc E = Parser.getTok().getLoc();
1980  if (getParser().ParseExpression(ShiftAmount)) {
1981    Error(E, "malformed rotate expression");
1982    return MatchOperand_ParseFail;
1983  }
1984  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1985  if (!CE) {
1986    Error(E, "rotate amount must be an immediate");
1987    return MatchOperand_ParseFail;
1988  }
1989
1990  int64_t Val = CE->getValue();
1991  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
1992  // normally, zero is represented in asm by omitting the rotate operand
1993  // entirely.
1994  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
1995    Error(E, "'ror' rotate amount must be 8, 16, or 24");
1996    return MatchOperand_ParseFail;
1997  }
1998
1999  E = Parser.getTok().getLoc();
2000  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2001
2002  return MatchOperand_Success;
2003}
2004
2005ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2006parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2007  SMLoc S = Parser.getTok().getLoc();
2008  // The bitfield descriptor is really two operands, the LSB and the width.
2009  if (Parser.getTok().isNot(AsmToken::Hash)) {
2010    Error(Parser.getTok().getLoc(), "'#' expected");
2011    return MatchOperand_ParseFail;
2012  }
2013  Parser.Lex(); // Eat hash token.
2014
2015  const MCExpr *LSBExpr;
2016  SMLoc E = Parser.getTok().getLoc();
2017  if (getParser().ParseExpression(LSBExpr)) {
2018    Error(E, "malformed immediate expression");
2019    return MatchOperand_ParseFail;
2020  }
2021  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2022  if (!CE) {
2023    Error(E, "'lsb' operand must be an immediate");
2024    return MatchOperand_ParseFail;
2025  }
2026
2027  int64_t LSB = CE->getValue();
2028  // The LSB must be in the range [0,31]
2029  if (LSB < 0 || LSB > 31) {
2030    Error(E, "'lsb' operand must be in the range [0,31]");
2031    return MatchOperand_ParseFail;
2032  }
2033  E = Parser.getTok().getLoc();
2034
2035  // Expect another immediate operand.
2036  if (Parser.getTok().isNot(AsmToken::Comma)) {
2037    Error(Parser.getTok().getLoc(), "too few operands");
2038    return MatchOperand_ParseFail;
2039  }
2040  Parser.Lex(); // Eat hash token.
2041  if (Parser.getTok().isNot(AsmToken::Hash)) {
2042    Error(Parser.getTok().getLoc(), "'#' expected");
2043    return MatchOperand_ParseFail;
2044  }
2045  Parser.Lex(); // Eat hash token.
2046
2047  const MCExpr *WidthExpr;
2048  if (getParser().ParseExpression(WidthExpr)) {
2049    Error(E, "malformed immediate expression");
2050    return MatchOperand_ParseFail;
2051  }
2052  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2053  if (!CE) {
2054    Error(E, "'width' operand must be an immediate");
2055    return MatchOperand_ParseFail;
2056  }
2057
2058  int64_t Width = CE->getValue();
2059  // The LSB must be in the range [1,32-lsb]
2060  if (Width < 1 || Width > 32 - LSB) {
2061    Error(E, "'width' operand must be in the range [1,32-lsb]");
2062    return MatchOperand_ParseFail;
2063  }
2064  E = Parser.getTok().getLoc();
2065
2066  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2067
2068  return MatchOperand_Success;
2069}
2070
2071ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2072parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2073  // Check for a post-index addressing register operand. Specifically:
2074  // postidx_reg := '+' register {, shift}
2075  //              | '-' register {, shift}
2076  //              | register {, shift}
2077
2078  // This method must return MatchOperand_NoMatch without consuming any tokens
2079  // in the case where there is no match, as other alternatives take other
2080  // parse methods.
2081  AsmToken Tok = Parser.getTok();
2082  SMLoc S = Tok.getLoc();
2083  bool haveEaten = false;
2084  bool isAdd = true;
2085  int Reg = -1;
2086  if (Tok.is(AsmToken::Plus)) {
2087    Parser.Lex(); // Eat the '+' token.
2088    haveEaten = true;
2089  } else if (Tok.is(AsmToken::Minus)) {
2090    Parser.Lex(); // Eat the '-' token.
2091    isAdd = false;
2092    haveEaten = true;
2093  }
2094  if (Parser.getTok().is(AsmToken::Identifier))
2095    Reg = tryParseRegister();
2096  if (Reg == -1) {
2097    if (!haveEaten)
2098      return MatchOperand_NoMatch;
2099    Error(Parser.getTok().getLoc(), "register expected");
2100    return MatchOperand_ParseFail;
2101  }
2102  SMLoc E = Parser.getTok().getLoc();
2103
2104  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2105  unsigned ShiftImm = 0;
2106  if (Parser.getTok().is(AsmToken::Comma)) {
2107    Parser.Lex(); // Eat the ','.
2108    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2109      return MatchOperand_ParseFail;
2110  }
2111
2112  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2113                                                  ShiftImm, S, E));
2114
2115  return MatchOperand_Success;
2116}
2117
2118ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2119parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2120  // Check for a post-index addressing register operand. Specifically:
2121  // am3offset := '+' register
2122  //              | '-' register
2123  //              | register
2124  //              | # imm
2125  //              | # + imm
2126  //              | # - imm
2127
2128  // This method must return MatchOperand_NoMatch without consuming any tokens
2129  // in the case where there is no match, as other alternatives take other
2130  // parse methods.
2131  AsmToken Tok = Parser.getTok();
2132  SMLoc S = Tok.getLoc();
2133
2134  // Do immediates first, as we always parse those if we have a '#'.
2135  if (Parser.getTok().is(AsmToken::Hash)) {
2136    Parser.Lex(); // Eat the '#'.
2137    // Explicitly look for a '-', as we need to encode negative zero
2138    // differently.
2139    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2140    const MCExpr *Offset;
2141    if (getParser().ParseExpression(Offset))
2142      return MatchOperand_ParseFail;
2143    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2144    if (!CE) {
2145      Error(S, "constant expression expected");
2146      return MatchOperand_ParseFail;
2147    }
2148    SMLoc E = Tok.getLoc();
2149    // Negative zero is encoded as the flag value INT32_MIN.
2150    int32_t Val = CE->getValue();
2151    if (isNegative && Val == 0)
2152      Val = INT32_MIN;
2153
2154    Operands.push_back(
2155      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2156
2157    return MatchOperand_Success;
2158  }
2159
2160
2161  bool haveEaten = false;
2162  bool isAdd = true;
2163  int Reg = -1;
2164  if (Tok.is(AsmToken::Plus)) {
2165    Parser.Lex(); // Eat the '+' token.
2166    haveEaten = true;
2167  } else if (Tok.is(AsmToken::Minus)) {
2168    Parser.Lex(); // Eat the '-' token.
2169    isAdd = false;
2170    haveEaten = true;
2171  }
2172  if (Parser.getTok().is(AsmToken::Identifier))
2173    Reg = tryParseRegister();
2174  if (Reg == -1) {
2175    if (!haveEaten)
2176      return MatchOperand_NoMatch;
2177    Error(Parser.getTok().getLoc(), "register expected");
2178    return MatchOperand_ParseFail;
2179  }
2180  SMLoc E = Parser.getTok().getLoc();
2181
2182  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2183                                                  0, S, E));
2184
2185  return MatchOperand_Success;
2186}
2187
2188/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2189/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2190/// when they refer multiple MIOperands inside a single one.
2191bool ARMAsmParser::
2192cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2193                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2194  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2195
2196  // Create a writeback register dummy placeholder.
2197  Inst.addOperand(MCOperand::CreateImm(0));
2198
2199  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2200  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2201  return true;
2202}
2203
2204/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2205/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2206/// when they refer multiple MIOperands inside a single one.
2207bool ARMAsmParser::
2208cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2209                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2210  // Create a writeback register dummy placeholder.
2211  Inst.addOperand(MCOperand::CreateImm(0));
2212  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2213  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2214  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2215  return true;
2216}
2217
2218/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2219/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2220/// when they refer multiple MIOperands inside a single one.
2221bool ARMAsmParser::
2222cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2223                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2224  // Create a writeback register dummy placeholder.
2225  Inst.addOperand(MCOperand::CreateImm(0));
2226  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2227  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2228  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2229  return true;
2230}
2231
2232/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2233/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2234/// when they refer multiple MIOperands inside a single one.
2235bool ARMAsmParser::
2236cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2237                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2238  // Create a writeback register dummy placeholder.
2239  Inst.addOperand(MCOperand::CreateImm(0));
2240  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2241  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2242  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2243  return true;
2244}
2245
2246/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2247/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2248/// when they refer multiple MIOperands inside a single one.
2249bool ARMAsmParser::
2250cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2251                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2252  // Rt
2253  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2254  // Create a writeback register dummy placeholder.
2255  Inst.addOperand(MCOperand::CreateImm(0));
2256  // addr
2257  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2258  // offset
2259  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2260  // pred
2261  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2262  return true;
2263}
2264
2265/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2266/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2267/// when they refer multiple MIOperands inside a single one.
2268bool ARMAsmParser::
2269cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2270                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2271  // Rt
2272  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2273  // Create a writeback register dummy placeholder.
2274  Inst.addOperand(MCOperand::CreateImm(0));
2275  // addr
2276  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2277  // offset
2278  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2279  // pred
2280  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2281  return true;
2282}
2283
2284/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2285/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2286/// when they refer multiple MIOperands inside a single one.
2287bool ARMAsmParser::
2288cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2289                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2290  // Create a writeback register dummy placeholder.
2291  Inst.addOperand(MCOperand::CreateImm(0));
2292  // Rt
2293  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2294  // addr
2295  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2296  // offset
2297  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2298  // pred
2299  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2300  return true;
2301}
2302
2303/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2304/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2305/// when they refer multiple MIOperands inside a single one.
2306bool ARMAsmParser::
2307cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2308                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2309  // Create a writeback register dummy placeholder.
2310  Inst.addOperand(MCOperand::CreateImm(0));
2311  // Rt
2312  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2313  // addr
2314  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2315  // offset
2316  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2317  // pred
2318  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2319  return true;
2320}
2321
2322/// cvtLdrdPre - Convert parsed operands to MCInst.
2323/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2324/// when they refer multiple MIOperands inside a single one.
2325bool ARMAsmParser::
2326cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2327           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2328  // Rt, Rt2
2329  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2330  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2331  // Create a writeback register dummy placeholder.
2332  Inst.addOperand(MCOperand::CreateImm(0));
2333  // addr
2334  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2335  // pred
2336  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2337  return true;
2338}
2339
2340/// cvtStrdPre - Convert parsed operands to MCInst.
2341/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2342/// when they refer multiple MIOperands inside a single one.
2343bool ARMAsmParser::
2344cvtStrdPre(MCInst &Inst, unsigned Opcode,
2345           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2346  // Create a writeback register dummy placeholder.
2347  Inst.addOperand(MCOperand::CreateImm(0));
2348  // Rt, Rt2
2349  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2350  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2351  // addr
2352  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2353  // pred
2354  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2355  return true;
2356}
2357
2358/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2359/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2360/// when they refer multiple MIOperands inside a single one.
2361bool ARMAsmParser::
2362cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2363                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2364  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2365  // Create a writeback register dummy placeholder.
2366  Inst.addOperand(MCOperand::CreateImm(0));
2367  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2368  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2369  return true;
2370}
2371
2372/// cvtThumbMultiple- Convert parsed operands to MCInst.
2373/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2374/// when they refer multiple MIOperands inside a single one.
2375bool ARMAsmParser::
2376cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2377           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2378  // The second source operand must be the same register as the destination
2379  // operand.
2380  if (Operands.size() == 6 &&
2381      (((ARMOperand*)Operands[3])->getReg() !=
2382       ((ARMOperand*)Operands[5])->getReg()) &&
2383      (((ARMOperand*)Operands[3])->getReg() !=
2384       ((ARMOperand*)Operands[4])->getReg())) {
2385    Error(Operands[3]->getStartLoc(),
2386          "destination register must match source register");
2387    return false;
2388  }
2389  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2390  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2391  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2392  // If we have a three-operand form, use that, else the second source operand
2393  // is just the destination operand again.
2394  if (Operands.size() == 6)
2395    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2396  else
2397    Inst.addOperand(Inst.getOperand(0));
2398  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2399
2400  return true;
2401}
2402
2403/// Parse an ARM memory expression, return false if successful else return true
2404/// or an error.  The first token must be a '[' when called.
2405bool ARMAsmParser::
2406parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2407  SMLoc S, E;
2408  assert(Parser.getTok().is(AsmToken::LBrac) &&
2409         "Token is not a Left Bracket");
2410  S = Parser.getTok().getLoc();
2411  Parser.Lex(); // Eat left bracket token.
2412
2413  const AsmToken &BaseRegTok = Parser.getTok();
2414  int BaseRegNum = tryParseRegister();
2415  if (BaseRegNum == -1)
2416    return Error(BaseRegTok.getLoc(), "register expected");
2417
2418  // The next token must either be a comma or a closing bracket.
2419  const AsmToken &Tok = Parser.getTok();
2420  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2421    return Error(Tok.getLoc(), "malformed memory operand");
2422
2423  if (Tok.is(AsmToken::RBrac)) {
2424    E = Tok.getLoc();
2425    Parser.Lex(); // Eat right bracket token.
2426
2427    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2428                                             0, false, S, E));
2429
2430    return false;
2431  }
2432
2433  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2434  Parser.Lex(); // Eat the comma.
2435
2436  // If we have a '#' it's an immediate offset, else assume it's a register
2437  // offset.
2438  if (Parser.getTok().is(AsmToken::Hash)) {
2439    Parser.Lex(); // Eat the '#'.
2440    E = Parser.getTok().getLoc();
2441
2442    // FIXME: Special case #-0 so we can correctly set the U bit.
2443
2444    const MCExpr *Offset;
2445    if (getParser().ParseExpression(Offset))
2446     return true;
2447
2448    // The expression has to be a constant. Memory references with relocations
2449    // don't come through here, as they use the <label> forms of the relevant
2450    // instructions.
2451    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2452    if (!CE)
2453      return Error (E, "constant expression expected");
2454
2455    // Now we should have the closing ']'
2456    E = Parser.getTok().getLoc();
2457    if (Parser.getTok().isNot(AsmToken::RBrac))
2458      return Error(E, "']' expected");
2459    Parser.Lex(); // Eat right bracket token.
2460
2461    // Don't worry about range checking the value here. That's handled by
2462    // the is*() predicates.
2463    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2464                                             ARM_AM::no_shift, 0, false, S,E));
2465
2466    // If there's a pre-indexing writeback marker, '!', just add it as a token
2467    // operand.
2468    if (Parser.getTok().is(AsmToken::Exclaim)) {
2469      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2470      Parser.Lex(); // Eat the '!'.
2471    }
2472
2473    return false;
2474  }
2475
2476  // The register offset is optionally preceded by a '+' or '-'
2477  bool isNegative = false;
2478  if (Parser.getTok().is(AsmToken::Minus)) {
2479    isNegative = true;
2480    Parser.Lex(); // Eat the '-'.
2481  } else if (Parser.getTok().is(AsmToken::Plus)) {
2482    // Nothing to do.
2483    Parser.Lex(); // Eat the '+'.
2484  }
2485
2486  E = Parser.getTok().getLoc();
2487  int OffsetRegNum = tryParseRegister();
2488  if (OffsetRegNum == -1)
2489    return Error(E, "register expected");
2490
2491  // If there's a shift operator, handle it.
2492  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2493  unsigned ShiftImm = 0;
2494  if (Parser.getTok().is(AsmToken::Comma)) {
2495    Parser.Lex(); // Eat the ','.
2496    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2497      return true;
2498  }
2499
2500  // Now we should have the closing ']'
2501  E = Parser.getTok().getLoc();
2502  if (Parser.getTok().isNot(AsmToken::RBrac))
2503    return Error(E, "']' expected");
2504  Parser.Lex(); // Eat right bracket token.
2505
2506  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2507                                           ShiftType, ShiftImm, isNegative,
2508                                           S, E));
2509
2510  // If there's a pre-indexing writeback marker, '!', just add it as a token
2511  // operand.
2512  if (Parser.getTok().is(AsmToken::Exclaim)) {
2513    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2514    Parser.Lex(); // Eat the '!'.
2515  }
2516
2517  return false;
2518}
2519
2520/// parseMemRegOffsetShift - one of these two:
2521///   ( lsl | lsr | asr | ror ) , # shift_amount
2522///   rrx
2523/// return true if it parses a shift otherwise it returns false.
2524bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2525                                          unsigned &Amount) {
2526  SMLoc Loc = Parser.getTok().getLoc();
2527  const AsmToken &Tok = Parser.getTok();
2528  if (Tok.isNot(AsmToken::Identifier))
2529    return true;
2530  StringRef ShiftName = Tok.getString();
2531  if (ShiftName == "lsl" || ShiftName == "LSL")
2532    St = ARM_AM::lsl;
2533  else if (ShiftName == "lsr" || ShiftName == "LSR")
2534    St = ARM_AM::lsr;
2535  else if (ShiftName == "asr" || ShiftName == "ASR")
2536    St = ARM_AM::asr;
2537  else if (ShiftName == "ror" || ShiftName == "ROR")
2538    St = ARM_AM::ror;
2539  else if (ShiftName == "rrx" || ShiftName == "RRX")
2540    St = ARM_AM::rrx;
2541  else
2542    return Error(Loc, "illegal shift operator");
2543  Parser.Lex(); // Eat shift type token.
2544
2545  // rrx stands alone.
2546  Amount = 0;
2547  if (St != ARM_AM::rrx) {
2548    Loc = Parser.getTok().getLoc();
2549    // A '#' and a shift amount.
2550    const AsmToken &HashTok = Parser.getTok();
2551    if (HashTok.isNot(AsmToken::Hash))
2552      return Error(HashTok.getLoc(), "'#' expected");
2553    Parser.Lex(); // Eat hash token.
2554
2555    const MCExpr *Expr;
2556    if (getParser().ParseExpression(Expr))
2557      return true;
2558    // Range check the immediate.
2559    // lsl, ror: 0 <= imm <= 31
2560    // lsr, asr: 0 <= imm <= 32
2561    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2562    if (!CE)
2563      return Error(Loc, "shift amount must be an immediate");
2564    int64_t Imm = CE->getValue();
2565    if (Imm < 0 ||
2566        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2567        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2568      return Error(Loc, "immediate shift value out of range");
2569    Amount = Imm;
2570  }
2571
2572  return false;
2573}
2574
2575/// Parse a arm instruction operand.  For now this parses the operand regardless
2576/// of the mnemonic.
2577bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2578                                StringRef Mnemonic) {
2579  SMLoc S, E;
2580
2581  // Check if the current operand has a custom associated parser, if so, try to
2582  // custom parse the operand, or fallback to the general approach.
2583  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2584  if (ResTy == MatchOperand_Success)
2585    return false;
2586  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2587  // there was a match, but an error occurred, in which case, just return that
2588  // the operand parsing failed.
2589  if (ResTy == MatchOperand_ParseFail)
2590    return true;
2591
2592  switch (getLexer().getKind()) {
2593  default:
2594    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2595    return true;
2596  case AsmToken::Identifier: {
2597    if (!tryParseRegisterWithWriteBack(Operands))
2598      return false;
2599    int Res = tryParseShiftRegister(Operands);
2600    if (Res == 0) // success
2601      return false;
2602    else if (Res == -1) // irrecoverable error
2603      return true;
2604
2605    // Fall though for the Identifier case that is not a register or a
2606    // special name.
2607  }
2608  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2609  case AsmToken::Dot: {   // . as a branch target
2610    // This was not a register so parse other operands that start with an
2611    // identifier (like labels) as expressions and create them as immediates.
2612    const MCExpr *IdVal;
2613    S = Parser.getTok().getLoc();
2614    if (getParser().ParseExpression(IdVal))
2615      return true;
2616    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2617    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2618    return false;
2619  }
2620  case AsmToken::LBrac:
2621    return parseMemory(Operands);
2622  case AsmToken::LCurly:
2623    return parseRegisterList(Operands);
2624  case AsmToken::Hash:
2625    // #42 -> immediate.
2626    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2627    S = Parser.getTok().getLoc();
2628    Parser.Lex();
2629    const MCExpr *ImmVal;
2630    if (getParser().ParseExpression(ImmVal))
2631      return true;
2632    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2633    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2634    return false;
2635  case AsmToken::Colon: {
2636    // ":lower16:" and ":upper16:" expression prefixes
2637    // FIXME: Check it's an expression prefix,
2638    // e.g. (FOO - :lower16:BAR) isn't legal.
2639    ARMMCExpr::VariantKind RefKind;
2640    if (parsePrefix(RefKind))
2641      return true;
2642
2643    const MCExpr *SubExprVal;
2644    if (getParser().ParseExpression(SubExprVal))
2645      return true;
2646
2647    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2648                                                   getContext());
2649    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2650    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2651    return false;
2652  }
2653  }
2654}
2655
2656// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2657//  :lower16: and :upper16:.
2658bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2659  RefKind = ARMMCExpr::VK_ARM_None;
2660
2661  // :lower16: and :upper16: modifiers
2662  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2663  Parser.Lex(); // Eat ':'
2664
2665  if (getLexer().isNot(AsmToken::Identifier)) {
2666    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2667    return true;
2668  }
2669
2670  StringRef IDVal = Parser.getTok().getIdentifier();
2671  if (IDVal == "lower16") {
2672    RefKind = ARMMCExpr::VK_ARM_LO16;
2673  } else if (IDVal == "upper16") {
2674    RefKind = ARMMCExpr::VK_ARM_HI16;
2675  } else {
2676    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2677    return true;
2678  }
2679  Parser.Lex();
2680
2681  if (getLexer().isNot(AsmToken::Colon)) {
2682    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2683    return true;
2684  }
2685  Parser.Lex(); // Eat the last ':'
2686  return false;
2687}
2688
2689const MCExpr *
2690ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2691                                MCSymbolRefExpr::VariantKind Variant) {
2692  // Recurse over the given expression, rebuilding it to apply the given variant
2693  // to the leftmost symbol.
2694  if (Variant == MCSymbolRefExpr::VK_None)
2695    return E;
2696
2697  switch (E->getKind()) {
2698  case MCExpr::Target:
2699    llvm_unreachable("Can't handle target expr yet");
2700  case MCExpr::Constant:
2701    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2702
2703  case MCExpr::SymbolRef: {
2704    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2705
2706    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2707      return 0;
2708
2709    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2710  }
2711
2712  case MCExpr::Unary:
2713    llvm_unreachable("Can't handle unary expressions yet");
2714
2715  case MCExpr::Binary: {
2716    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2717    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2718    const MCExpr *RHS = BE->getRHS();
2719    if (!LHS)
2720      return 0;
2721
2722    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2723  }
2724  }
2725
2726  assert(0 && "Invalid expression kind!");
2727  return 0;
2728}
2729
2730/// \brief Given a mnemonic, split out possible predication code and carry
2731/// setting letters to form a canonical mnemonic and flags.
2732//
2733// FIXME: Would be nice to autogen this.
2734StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2735                                      unsigned &PredicationCode,
2736                                      bool &CarrySetting,
2737                                      unsigned &ProcessorIMod) {
2738  PredicationCode = ARMCC::AL;
2739  CarrySetting = false;
2740  ProcessorIMod = 0;
2741
2742  // Ignore some mnemonics we know aren't predicated forms.
2743  //
2744  // FIXME: Would be nice to autogen this.
2745  if ((Mnemonic == "movs" && isThumb()) ||
2746      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2747      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2748      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2749      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2750      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2751      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2752      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2753    return Mnemonic;
2754
2755  // First, split out any predication code. Ignore mnemonics we know aren't
2756  // predicated but do have a carry-set and so weren't caught above.
2757  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2758      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2759      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
2760      Mnemonic != "sbcs") {
2761    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2762      .Case("eq", ARMCC::EQ)
2763      .Case("ne", ARMCC::NE)
2764      .Case("hs", ARMCC::HS)
2765      .Case("cs", ARMCC::HS)
2766      .Case("lo", ARMCC::LO)
2767      .Case("cc", ARMCC::LO)
2768      .Case("mi", ARMCC::MI)
2769      .Case("pl", ARMCC::PL)
2770      .Case("vs", ARMCC::VS)
2771      .Case("vc", ARMCC::VC)
2772      .Case("hi", ARMCC::HI)
2773      .Case("ls", ARMCC::LS)
2774      .Case("ge", ARMCC::GE)
2775      .Case("lt", ARMCC::LT)
2776      .Case("gt", ARMCC::GT)
2777      .Case("le", ARMCC::LE)
2778      .Case("al", ARMCC::AL)
2779      .Default(~0U);
2780    if (CC != ~0U) {
2781      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2782      PredicationCode = CC;
2783    }
2784  }
2785
2786  // Next, determine if we have a carry setting bit. We explicitly ignore all
2787  // the instructions we know end in 's'.
2788  if (Mnemonic.endswith("s") &&
2789      !(Mnemonic == "cps" || Mnemonic == "mls" ||
2790        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2791        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2792        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2793        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2794        (Mnemonic == "movs" && isThumb()))) {
2795    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2796    CarrySetting = true;
2797  }
2798
2799  // The "cps" instruction can have a interrupt mode operand which is glued into
2800  // the mnemonic. Check if this is the case, split it and parse the imod op
2801  if (Mnemonic.startswith("cps")) {
2802    // Split out any imod code.
2803    unsigned IMod =
2804      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2805      .Case("ie", ARM_PROC::IE)
2806      .Case("id", ARM_PROC::ID)
2807      .Default(~0U);
2808    if (IMod != ~0U) {
2809      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2810      ProcessorIMod = IMod;
2811    }
2812  }
2813
2814  return Mnemonic;
2815}
2816
2817/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2818/// inclusion of carry set or predication code operands.
2819//
2820// FIXME: It would be nice to autogen this.
2821void ARMAsmParser::
2822getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2823                      bool &CanAcceptPredicationCode) {
2824  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2825      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2826      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2827      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2828      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2829      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2830      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2831      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
2832      // FIXME: We need a better way. This really confused Thumb2
2833      // parsing for 'mov'.
2834      (Mnemonic == "mov" && !isThumbOne())) {
2835    CanAcceptCarrySet = true;
2836  } else {
2837    CanAcceptCarrySet = false;
2838  }
2839
2840  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2841      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2842      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2843      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2844      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2845      Mnemonic == "setend" ||
2846      (Mnemonic == "nop" && isThumbOne()) ||
2847      ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2848      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2849        && !isThumb()) ||
2850      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2851    CanAcceptPredicationCode = false;
2852  } else {
2853    CanAcceptPredicationCode = true;
2854  }
2855
2856  if (isThumb())
2857    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2858        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2859      CanAcceptPredicationCode = false;
2860}
2861
2862bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2863                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2864
2865  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2866  // another does not. Specifically, the MOVW instruction does not. So we
2867  // special case it here and remove the defaulted (non-setting) cc_out
2868  // operand if that's the instruction we're trying to match.
2869  //
2870  // We do this as post-processing of the explicit operands rather than just
2871  // conditionally adding the cc_out in the first place because we need
2872  // to check the type of the parsed immediate operand.
2873  if (Mnemonic == "mov" && Operands.size() > 4 &&
2874      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2875      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2876      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2877    return true;
2878
2879  // Register-register 'add' for thumb does not have a cc_out operand
2880  // when there are only two register operands.
2881  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2882      static_cast<ARMOperand*>(Operands[3])->isReg() &&
2883      static_cast<ARMOperand*>(Operands[4])->isReg() &&
2884      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2885    return true;
2886
2887  return false;
2888}
2889
2890/// Parse an arm instruction mnemonic followed by its operands.
2891bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2892                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2893  // Create the leading tokens for the mnemonic, split by '.' characters.
2894  size_t Start = 0, Next = Name.find('.');
2895  StringRef Mnemonic = Name.slice(Start, Next);
2896
2897  // Split out the predication code and carry setting flag from the mnemonic.
2898  unsigned PredicationCode;
2899  unsigned ProcessorIMod;
2900  bool CarrySetting;
2901  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2902                           ProcessorIMod);
2903
2904  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2905
2906  // FIXME: This is all a pretty gross hack. We should automatically handle
2907  // optional operands like this via tblgen.
2908
2909  // Next, add the CCOut and ConditionCode operands, if needed.
2910  //
2911  // For mnemonics which can ever incorporate a carry setting bit or predication
2912  // code, our matching model involves us always generating CCOut and
2913  // ConditionCode operands to match the mnemonic "as written" and then we let
2914  // the matcher deal with finding the right instruction or generating an
2915  // appropriate error.
2916  bool CanAcceptCarrySet, CanAcceptPredicationCode;
2917  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2918
2919  // If we had a carry-set on an instruction that can't do that, issue an
2920  // error.
2921  if (!CanAcceptCarrySet && CarrySetting) {
2922    Parser.EatToEndOfStatement();
2923    return Error(NameLoc, "instruction '" + Mnemonic +
2924                 "' can not set flags, but 's' suffix specified");
2925  }
2926  // If we had a predication code on an instruction that can't do that, issue an
2927  // error.
2928  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2929    Parser.EatToEndOfStatement();
2930    return Error(NameLoc, "instruction '" + Mnemonic +
2931                 "' is not predicable, but condition code specified");
2932  }
2933
2934  // Add the carry setting operand, if necessary.
2935  //
2936  // FIXME: It would be awesome if we could somehow invent a location such that
2937  // match errors on this operand would print a nice diagnostic about how the
2938  // 's' character in the mnemonic resulted in a CCOut operand.
2939  if (CanAcceptCarrySet)
2940    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2941                                               NameLoc));
2942
2943  // Add the predication code operand, if necessary.
2944  if (CanAcceptPredicationCode) {
2945    Operands.push_back(ARMOperand::CreateCondCode(
2946                         ARMCC::CondCodes(PredicationCode), NameLoc));
2947  }
2948
2949  // Add the processor imod operand, if necessary.
2950  if (ProcessorIMod) {
2951    Operands.push_back(ARMOperand::CreateImm(
2952          MCConstantExpr::Create(ProcessorIMod, getContext()),
2953                                 NameLoc, NameLoc));
2954  } else {
2955    // This mnemonic can't ever accept a imod, but the user wrote
2956    // one (or misspelled another mnemonic).
2957
2958    // FIXME: Issue a nice error.
2959  }
2960
2961  // Add the remaining tokens in the mnemonic.
2962  while (Next != StringRef::npos) {
2963    Start = Next;
2964    Next = Name.find('.', Start + 1);
2965    StringRef ExtraToken = Name.slice(Start, Next);
2966
2967    Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2968  }
2969
2970  // Read the remaining operands.
2971  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2972    // Read the first operand.
2973    if (parseOperand(Operands, Mnemonic)) {
2974      Parser.EatToEndOfStatement();
2975      return true;
2976    }
2977
2978    while (getLexer().is(AsmToken::Comma)) {
2979      Parser.Lex();  // Eat the comma.
2980
2981      // Parse and remember the operand.
2982      if (parseOperand(Operands, Mnemonic)) {
2983        Parser.EatToEndOfStatement();
2984        return true;
2985      }
2986    }
2987  }
2988
2989  if (getLexer().isNot(AsmToken::EndOfStatement)) {
2990    Parser.EatToEndOfStatement();
2991    return TokError("unexpected token in argument list");
2992  }
2993
2994  Parser.Lex(); // Consume the EndOfStatement
2995
2996  // Some instructions, mostly Thumb, have forms for the same mnemonic that
2997  // do and don't have a cc_out optional-def operand. With some spot-checks
2998  // of the operand list, we can figure out which variant we're trying to
2999  // parse and adjust accordingly before actually matching. Reason number
3000  // #317 the table driven matcher doesn't fit well with the ARM instruction
3001  // set.
3002  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
3003    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3004    Operands.erase(Operands.begin() + 1);
3005    delete Op;
3006  }
3007
3008  // ARM mode 'blx' need special handling, as the register operand version
3009  // is predicable, but the label operand version is not. So, we can't rely
3010  // on the Mnemonic based checking to correctly figure out when to put
3011  // a CondCode operand in the list. If we're trying to match the label
3012  // version, remove the CondCode operand here.
3013  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3014      static_cast<ARMOperand*>(Operands[2])->isImm()) {
3015    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3016    Operands.erase(Operands.begin() + 1);
3017    delete Op;
3018  }
3019
3020  // The vector-compare-to-zero instructions have a literal token "#0" at
3021  // the end that comes to here as an immediate operand. Convert it to a
3022  // token to play nicely with the matcher.
3023  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3024      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3025      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3026    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3027    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3028    if (CE && CE->getValue() == 0) {
3029      Operands.erase(Operands.begin() + 5);
3030      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3031      delete Op;
3032    }
3033  }
3034  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3035  // end. Convert it to a token here.
3036  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3037      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3038    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3039    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3040    if (CE && CE->getValue() == 0) {
3041      Operands.erase(Operands.begin() + 5);
3042      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3043      delete Op;
3044    }
3045  }
3046
3047  return false;
3048}
3049
3050// Validate context-sensitive operand constraints.
3051
3052// return 'true' if register list contains non-low GPR registers,
3053// 'false' otherwise. If Reg is in the register list or is HiReg, set
3054// 'containsReg' to true.
3055static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3056                                 unsigned HiReg, bool &containsReg) {
3057  containsReg = false;
3058  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3059    unsigned OpReg = Inst.getOperand(i).getReg();
3060    if (OpReg == Reg)
3061      containsReg = true;
3062    // Anything other than a low register isn't legal here.
3063    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3064      return true;
3065  }
3066  return false;
3067}
3068
3069// FIXME: We would really like to be able to tablegen'erate this.
3070bool ARMAsmParser::
3071validateInstruction(MCInst &Inst,
3072                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3073  switch (Inst.getOpcode()) {
3074  case ARM::LDRD:
3075  case ARM::LDRD_PRE:
3076  case ARM::LDRD_POST:
3077  case ARM::LDREXD: {
3078    // Rt2 must be Rt + 1.
3079    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3080    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3081    if (Rt2 != Rt + 1)
3082      return Error(Operands[3]->getStartLoc(),
3083                   "destination operands must be sequential");
3084    return false;
3085  }
3086  case ARM::STRD: {
3087    // Rt2 must be Rt + 1.
3088    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3089    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3090    if (Rt2 != Rt + 1)
3091      return Error(Operands[3]->getStartLoc(),
3092                   "source operands must be sequential");
3093    return false;
3094  }
3095  case ARM::STRD_PRE:
3096  case ARM::STRD_POST:
3097  case ARM::STREXD: {
3098    // Rt2 must be Rt + 1.
3099    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3100    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3101    if (Rt2 != Rt + 1)
3102      return Error(Operands[3]->getStartLoc(),
3103                   "source operands must be sequential");
3104    return false;
3105  }
3106  case ARM::SBFX:
3107  case ARM::UBFX: {
3108    // width must be in range [1, 32-lsb]
3109    unsigned lsb = Inst.getOperand(2).getImm();
3110    unsigned widthm1 = Inst.getOperand(3).getImm();
3111    if (widthm1 >= 32 - lsb)
3112      return Error(Operands[5]->getStartLoc(),
3113                   "bitfield width must be in range [1,32-lsb]");
3114    return false;
3115  }
3116  case ARM::tLDMIA: {
3117    // Thumb LDM instructions are writeback iff the base register is not
3118    // in the register list.
3119    unsigned Rn = Inst.getOperand(0).getReg();
3120    bool hasWritebackToken =
3121      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3122       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3123    bool listContainsBase;
3124    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase))
3125      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3126                   "registers must be in range r0-r7");
3127    // If we should have writeback, then there should be a '!' token.
3128    if (!listContainsBase && !hasWritebackToken)
3129      return Error(Operands[2]->getStartLoc(),
3130                   "writeback operator '!' expected");
3131    // Likewise, if we should not have writeback, there must not be a '!'
3132    if (listContainsBase && hasWritebackToken)
3133      return Error(Operands[3]->getStartLoc(),
3134                   "writeback operator '!' not allowed when base register "
3135                   "in register list");
3136
3137    break;
3138  }
3139  case ARM::tPOP: {
3140    bool listContainsBase;
3141    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3142      return Error(Operands[2]->getStartLoc(),
3143                   "registers must be in range r0-r7 or pc");
3144    break;
3145  }
3146  case ARM::tPUSH: {
3147    bool listContainsBase;
3148    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3149      return Error(Operands[2]->getStartLoc(),
3150                   "registers must be in range r0-r7 or lr");
3151    break;
3152  }
3153  case ARM::tSTMIA_UPD: {
3154    bool listContainsBase;
3155    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3156      return Error(Operands[4]->getStartLoc(),
3157                   "registers must be in range r0-r7");
3158    break;
3159  }
3160  }
3161
3162  return false;
3163}
3164
3165void ARMAsmParser::
3166processInstruction(MCInst &Inst,
3167                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3168  switch (Inst.getOpcode()) {
3169  case ARM::LDMIA_UPD:
3170    // If this is a load of a single register via a 'pop', then we should use
3171    // a post-indexed LDR instruction instead, per the ARM ARM.
3172    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3173        Inst.getNumOperands() == 5) {
3174      MCInst TmpInst;
3175      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3176      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3177      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3178      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3179      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3180      TmpInst.addOperand(MCOperand::CreateImm(4));
3181      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3182      TmpInst.addOperand(Inst.getOperand(3));
3183      Inst = TmpInst;
3184    }
3185    break;
3186  case ARM::STMDB_UPD:
3187    // If this is a store of a single register via a 'push', then we should use
3188    // a pre-indexed STR instruction instead, per the ARM ARM.
3189    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3190        Inst.getNumOperands() == 5) {
3191      MCInst TmpInst;
3192      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3193      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3194      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3195      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3196      TmpInst.addOperand(MCOperand::CreateImm(-4));
3197      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3198      TmpInst.addOperand(Inst.getOperand(3));
3199      Inst = TmpInst;
3200    }
3201    break;
3202  case ARM::tADDi8:
3203    // If the immediate is in the range 0-7, we really wanted tADDi3.
3204    if (Inst.getOperand(3).getImm() < 8)
3205      Inst.setOpcode(ARM::tADDi3);
3206    break;
3207  case ARM::tBcc:
3208    // If the conditional is AL, we really want tB.
3209    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3210      Inst.setOpcode(ARM::tB);
3211    break;
3212  }
3213}
3214
3215// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3216// the ARMInsts array) instead. Getting that here requires awkward
3217// API changes, though. Better way?
3218namespace llvm {
3219extern MCInstrDesc ARMInsts[];
3220}
3221static MCInstrDesc &getInstDesc(unsigned Opcode) {
3222  return ARMInsts[Opcode];
3223}
3224
3225unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3226  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3227  // suffix depending on whether they're in an IT block or not.
3228  unsigned Opc = Inst.getOpcode();
3229  MCInstrDesc &MCID = getInstDesc(Opc);
3230  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3231    assert(MCID.hasOptionalDef() &&
3232           "optionally flag setting instruction missing optional def operand");
3233    assert(MCID.NumOperands == Inst.getNumOperands() &&
3234           "operand count mismatch!");
3235    // Find the optional-def operand (cc_out).
3236    unsigned OpNo;
3237    for (OpNo = 0;
3238         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3239         ++OpNo)
3240      ;
3241    // If we're parsing Thumb1, reject it completely.
3242    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3243      return Match_MnemonicFail;
3244    // If we're parsing Thumb2, which form is legal depends on whether we're
3245    // in an IT block.
3246    // FIXME: We don't yet do IT blocks, so just always consider it to be
3247    // that we aren't in one until we do.
3248    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3249      return Match_RequiresITBlock;
3250  }
3251  // Some high-register supporting Thumb1 encodings only allow both registers
3252  // to be from r0-r7 when in Thumb2.
3253  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3254           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3255           isARMLowRegister(Inst.getOperand(2).getReg()))
3256    return Match_RequiresThumb2;
3257  // Others only require ARMv6 or later.
3258  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3259           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3260           isARMLowRegister(Inst.getOperand(1).getReg()))
3261    return Match_RequiresV6;
3262  return Match_Success;
3263}
3264
3265bool ARMAsmParser::
3266MatchAndEmitInstruction(SMLoc IDLoc,
3267                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3268                        MCStreamer &Out) {
3269  MCInst Inst;
3270  unsigned ErrorInfo;
3271  unsigned MatchResult;
3272  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3273  switch (MatchResult) {
3274  default: break;
3275  case Match_Success:
3276    // Context sensitive operand constraints aren't handled by the matcher,
3277    // so check them here.
3278    if (validateInstruction(Inst, Operands))
3279      return true;
3280
3281    // Some instructions need post-processing to, for example, tweak which
3282    // encoding is selected.
3283    processInstruction(Inst, Operands);
3284
3285    Out.EmitInstruction(Inst);
3286    return false;
3287  case Match_MissingFeature:
3288    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3289    return true;
3290  case Match_InvalidOperand: {
3291    SMLoc ErrorLoc = IDLoc;
3292    if (ErrorInfo != ~0U) {
3293      if (ErrorInfo >= Operands.size())
3294        return Error(IDLoc, "too few operands for instruction");
3295
3296      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3297      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3298    }
3299
3300    return Error(ErrorLoc, "invalid operand for instruction");
3301  }
3302  case Match_MnemonicFail:
3303    return Error(IDLoc, "invalid instruction");
3304  case Match_ConversionFail:
3305    // The converter function will have already emited a diagnostic.
3306    return true;
3307  case Match_RequiresITBlock:
3308    return Error(IDLoc, "instruction only valid inside IT block");
3309  case Match_RequiresV6:
3310    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3311  case Match_RequiresThumb2:
3312    return Error(IDLoc, "instruction variant requires Thumb2");
3313  }
3314
3315  llvm_unreachable("Implement any new match types added!");
3316  return true;
3317}
3318
3319/// parseDirective parses the arm specific directives
3320bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3321  StringRef IDVal = DirectiveID.getIdentifier();
3322  if (IDVal == ".word")
3323    return parseDirectiveWord(4, DirectiveID.getLoc());
3324  else if (IDVal == ".thumb")
3325    return parseDirectiveThumb(DirectiveID.getLoc());
3326  else if (IDVal == ".thumb_func")
3327    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3328  else if (IDVal == ".code")
3329    return parseDirectiveCode(DirectiveID.getLoc());
3330  else if (IDVal == ".syntax")
3331    return parseDirectiveSyntax(DirectiveID.getLoc());
3332  return true;
3333}
3334
3335/// parseDirectiveWord
3336///  ::= .word [ expression (, expression)* ]
3337bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3338  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3339    for (;;) {
3340      const MCExpr *Value;
3341      if (getParser().ParseExpression(Value))
3342        return true;
3343
3344      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3345
3346      if (getLexer().is(AsmToken::EndOfStatement))
3347        break;
3348
3349      // FIXME: Improve diagnostic.
3350      if (getLexer().isNot(AsmToken::Comma))
3351        return Error(L, "unexpected token in directive");
3352      Parser.Lex();
3353    }
3354  }
3355
3356  Parser.Lex();
3357  return false;
3358}
3359
3360/// parseDirectiveThumb
3361///  ::= .thumb
3362bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3363  if (getLexer().isNot(AsmToken::EndOfStatement))
3364    return Error(L, "unexpected token in directive");
3365  Parser.Lex();
3366
3367  // TODO: set thumb mode
3368  // TODO: tell the MC streamer the mode
3369  // getParser().getStreamer().Emit???();
3370  return false;
3371}
3372
3373/// parseDirectiveThumbFunc
3374///  ::= .thumbfunc symbol_name
3375bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3376  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3377  bool isMachO = MAI.hasSubsectionsViaSymbols();
3378  StringRef Name;
3379
3380  // Darwin asm has function name after .thumb_func direction
3381  // ELF doesn't
3382  if (isMachO) {
3383    const AsmToken &Tok = Parser.getTok();
3384    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3385      return Error(L, "unexpected token in .thumb_func directive");
3386    Name = Tok.getString();
3387    Parser.Lex(); // Consume the identifier token.
3388  }
3389
3390  if (getLexer().isNot(AsmToken::EndOfStatement))
3391    return Error(L, "unexpected token in directive");
3392  Parser.Lex();
3393
3394  // FIXME: assuming function name will be the line following .thumb_func
3395  if (!isMachO) {
3396    Name = Parser.getTok().getString();
3397  }
3398
3399  // Mark symbol as a thumb symbol.
3400  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3401  getParser().getStreamer().EmitThumbFunc(Func);
3402  return false;
3403}
3404
3405/// parseDirectiveSyntax
3406///  ::= .syntax unified | divided
3407bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3408  const AsmToken &Tok = Parser.getTok();
3409  if (Tok.isNot(AsmToken::Identifier))
3410    return Error(L, "unexpected token in .syntax directive");
3411  StringRef Mode = Tok.getString();
3412  if (Mode == "unified" || Mode == "UNIFIED")
3413    Parser.Lex();
3414  else if (Mode == "divided" || Mode == "DIVIDED")
3415    return Error(L, "'.syntax divided' arm asssembly not supported");
3416  else
3417    return Error(L, "unrecognized syntax mode in .syntax directive");
3418
3419  if (getLexer().isNot(AsmToken::EndOfStatement))
3420    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3421  Parser.Lex();
3422
3423  // TODO tell the MC streamer the mode
3424  // getParser().getStreamer().Emit???();
3425  return false;
3426}
3427
3428/// parseDirectiveCode
3429///  ::= .code 16 | 32
3430bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3431  const AsmToken &Tok = Parser.getTok();
3432  if (Tok.isNot(AsmToken::Integer))
3433    return Error(L, "unexpected token in .code directive");
3434  int64_t Val = Parser.getTok().getIntVal();
3435  if (Val == 16)
3436    Parser.Lex();
3437  else if (Val == 32)
3438    Parser.Lex();
3439  else
3440    return Error(L, "invalid operand to .code directive");
3441
3442  if (getLexer().isNot(AsmToken::EndOfStatement))
3443    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3444  Parser.Lex();
3445
3446  if (Val == 16) {
3447    if (!isThumb()) {
3448      SwitchMode();
3449      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3450    }
3451  } else {
3452    if (isThumb()) {
3453      SwitchMode();
3454      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3455    }
3456  }
3457
3458  return false;
3459}
3460
3461extern "C" void LLVMInitializeARMAsmLexer();
3462
3463/// Force static initialization.
3464extern "C" void LLVMInitializeARMAsmParser() {
3465  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3466  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3467  LLVMInitializeARMAsmLexer();
3468}
3469
3470#define GET_REGISTER_MATCHER
3471#define GET_MATCHER_IMPLEMENTATION
3472#include "ARMGenAsmMatcher.inc"
3473