Thumb1InstrInfo.cpp revision 892597943adc02583af32a86b4289f1fb02d2e4f 
1//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMInstrInfo.h"
15#include "ARM.h"
16#include "ARMGenInstrInfo.inc"
17#include "ARMMachineFunctionInfo.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/ADT/SmallVector.h"
21#include "Thumb1InstrInfo.h"
22
23using namespace llvm;
24
25Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) : RI(*this, STI) {
26}
27
28unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
29  return 0;
30}
31
32bool
33Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
34  if (MBB.empty()) return false;
35
36  switch (MBB.back().getOpcode()) {
37  case ARM::tBX_RET:
38  case ARM::tBX_RET_vararg:
39  case ARM::tPOP_RET:
40  case ARM::tB:
41  case ARM::tBR_JTr:
42    return true;
43  default:
44    break;
45  }
46
47  return false;
48}
49
50bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
51                                   MachineBasicBlock::iterator I,
52                                   unsigned DestReg, unsigned SrcReg,
53                                   const TargetRegisterClass *DestRC,
54                                   const TargetRegisterClass *SrcRC) const {
55  DebugLoc DL = DebugLoc::getUnknownLoc();
56  if (I != MBB.end()) DL = I->getDebugLoc();
57
58  if (DestRC == ARM::GPRRegisterClass) {
59    if (SrcRC == ARM::GPRRegisterClass) {
60      BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
61      return true;
62    } else if (SrcRC == ARM::tGPRRegisterClass) {
63      BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
64      return true;
65    }
66  } else if (DestRC == ARM::tGPRRegisterClass) {
67    if (SrcRC == ARM::GPRRegisterClass) {
68      BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
69      return true;
70    } else if (SrcRC == ARM::tGPRRegisterClass) {
71      BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
72      return true;
73    }
74  }
75
76  return false;
77}
78
79bool Thumb1InstrInfo::
80canFoldMemoryOperand(const MachineInstr *MI,
81                     const SmallVectorImpl<unsigned> &Ops) const {
82  if (Ops.size() != 1) return false;
83
84  unsigned OpNum = Ops[0];
85  unsigned Opc = MI->getOpcode();
86  switch (Opc) {
87  default: break;
88  case ARM::tMOVr:
89  case ARM::tMOVtgpr2gpr:
90  case ARM::tMOVgpr2tgpr:
91  case ARM::tMOVgpr2gpr: {
92    if (OpNum == 0) { // move -> store
93      unsigned SrcReg = MI->getOperand(1).getReg();
94      if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
95          !isARMLowRegister(SrcReg))
96        // tSpill cannot take a high register operand.
97        return false;
98    } else {          // move -> load
99      unsigned DstReg = MI->getOperand(0).getReg();
100      if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
101          !isARMLowRegister(DstReg))
102        // tRestore cannot target a high register operand.
103        return false;
104    }
105    return true;
106  }
107  }
108
109  return false;
110}
111
112void Thumb1InstrInfo::
113storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
114                    unsigned SrcReg, bool isKill, int FI,
115                    const TargetRegisterClass *RC) const {
116  DebugLoc DL = DebugLoc::getUnknownLoc();
117  if (I != MBB.end()) DL = I->getDebugLoc();
118
119  assert((RC == ARM::tGPRRegisterClass ||
120          (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
121           isARMLowRegister(SrcReg))) && "Unknown regclass!");
122
123  if (RC == ARM::tGPRRegisterClass) {
124    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
125                   .addReg(SrcReg, getKillRegState(isKill))
126                   .addFrameIndex(FI).addImm(0));
127  }
128}
129
130void Thumb1InstrInfo::
131loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
132                     unsigned DestReg, int FI,
133                     const TargetRegisterClass *RC) const {
134  DebugLoc DL = DebugLoc::getUnknownLoc();
135  if (I != MBB.end()) DL = I->getDebugLoc();
136
137  assert((RC == ARM::tGPRRegisterClass ||
138          (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
139           isARMLowRegister(DestReg))) && "Unknown regclass!");
140
141  if (RC == ARM::tGPRRegisterClass) {
142    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
143                   .addFrameIndex(FI).addImm(0));
144  }
145}
146
147bool Thumb1InstrInfo::
148spillCalleeSavedRegisters(MachineBasicBlock &MBB,
149                          MachineBasicBlock::iterator MI,
150                          const std::vector<CalleeSavedInfo> &CSI) const {
151  if (CSI.empty())
152    return false;
153
154  DebugLoc DL = DebugLoc::getUnknownLoc();
155  if (MI != MBB.end()) DL = MI->getDebugLoc();
156
157  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
158  AddDefaultPred(MIB);
159  MIB.addReg(0); // No write back.
160  for (unsigned i = CSI.size(); i != 0; --i) {
161    unsigned Reg = CSI[i-1].getReg();
162    // Add the callee-saved register as live-in. It's killed at the spill.
163    MBB.addLiveIn(Reg);
164    MIB.addReg(Reg, RegState::Kill);
165  }
166  return true;
167}
168
169bool Thumb1InstrInfo::
170restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
171                            MachineBasicBlock::iterator MI,
172                            const std::vector<CalleeSavedInfo> &CSI) const {
173  MachineFunction &MF = *MBB.getParent();
174  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
175  if (CSI.empty())
176    return false;
177
178  bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
179  DebugLoc DL = MI->getDebugLoc();
180  MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
181  AddDefaultPred(MIB);
182  MIB.addReg(0); // No write back.
183
184  bool NumRegs = 0;
185  for (unsigned i = CSI.size(); i != 0; --i) {
186    unsigned Reg = CSI[i-1].getReg();
187    if (Reg == ARM::LR) {
188      // Special epilogue for vararg functions. See emitEpilogue
189      if (isVarArg)
190        continue;
191      Reg = ARM::PC;
192      (*MIB).setDesc(get(ARM::tPOP_RET));
193      MI = MBB.erase(MI);
194    }
195    MIB.addReg(Reg, getDefRegState(true));
196    ++NumRegs;
197  }
198
199  // It's illegal to emit pop instruction without operands.
200  if (NumRegs)
201    MBB.insert(MI, &*MIB);
202
203  return true;
204}
205
206MachineInstr *Thumb1InstrInfo::
207foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
208                      const SmallVectorImpl<unsigned> &Ops, int FI) const {
209  if (Ops.size() != 1) return NULL;
210
211  unsigned OpNum = Ops[0];
212  unsigned Opc = MI->getOpcode();
213  MachineInstr *NewMI = NULL;
214  switch (Opc) {
215  default: break;
216  case ARM::tMOVr:
217  case ARM::tMOVtgpr2gpr:
218  case ARM::tMOVgpr2tgpr:
219  case ARM::tMOVgpr2gpr: {
220    if (OpNum == 0) { // move -> store
221      unsigned SrcReg = MI->getOperand(1).getReg();
222      bool isKill = MI->getOperand(1).isKill();
223      if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
224          !isARMLowRegister(SrcReg))
225        // tSpill cannot take a high register operand.
226        break;
227      NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
228                             .addReg(SrcReg, getKillRegState(isKill))
229                             .addFrameIndex(FI).addImm(0));
230    } else {          // move -> load
231      unsigned DstReg = MI->getOperand(0).getReg();
232      if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
233          !isARMLowRegister(DstReg))
234        // tRestore cannot target a high register operand.
235        break;
236      bool isDead = MI->getOperand(0).isDead();
237      NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
238                             .addReg(DstReg,
239                                     RegState::Define | getDeadRegState(isDead))
240                             .addFrameIndex(FI).addImm(0));
241    }
242    break;
243  }
244  }
245
246  return NewMI;
247}
248