Thumb1InstrInfo.cpp revision b53cc014d0f47b898c9daca34566c16dda6c4c1e 
1//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMInstrInfo.h"
15#include "ARM.h"
16#include "ARMGenInstrInfo.inc"
17#include "ARMMachineFunctionInfo.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/ADT/SmallVector.h"
21#include "Thumb1InstrInfo.h"
22
23using namespace llvm;
24
25Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
26  : ARMBaseInstrInfo(STI), RI(*this, STI) {
27}
28
29unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
30  return 0;
31}
32
33unsigned
34Thumb1InstrInfo::unsignedOffsetOpcodeToSigned(unsigned opcode,
35                                              unsigned *NumBits) const {
36  return 0;
37}
38
39unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
40  switch (Op) {
41  case ARMII::ADDri: return ARM::tADDi8;
42  case ARMII::ADDrs: return 0;
43  case ARMII::ADDrr: return ARM::tADDrr;
44  case ARMII::B: return ARM::tB;
45  case ARMII::Bcc: return ARM::tBcc;
46  case ARMII::BR_JTr: return ARM::tBR_JTr;
47  case ARMII::BR_JTm: return 0;
48  case ARMII::BR_JTadd: return 0;
49  case ARMII::BX_RET: return ARM::tBX_RET;
50  case ARMII::FCPYS: return 0;
51  case ARMII::FCPYD: return 0;
52  case ARMII::FLDD: return 0;
53  case ARMII::FLDS: return 0;
54  case ARMII::FSTD: return 0;
55  case ARMII::FSTS: return 0;
56  case ARMII::LDR: return ARM::tLDR;
57  case ARMII::MOVr: return ARM::tMOVr;
58  case ARMII::STR: return ARM::tSTR;
59  case ARMII::SUBri: return ARM::tSUBi8;
60  case ARMII::SUBrs: return 0;
61  case ARMII::SUBrr: return ARM::tSUBrr;
62  case ARMII::VMOVD: return 0;
63  case ARMII::VMOVQ: return 0;
64  default:
65    break;
66  }
67
68  return 0;
69}
70
71bool
72Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
73  if (MBB.empty()) return false;
74
75  switch (MBB.back().getOpcode()) {
76  case ARM::tBX_RET:
77  case ARM::tBX_RET_vararg:
78  case ARM::tPOP_RET:
79  case ARM::tB:
80  case ARM::tBR_JTr:
81    return true;
82  default:
83    break;
84  }
85
86  return false;
87}
88
89bool Thumb1InstrInfo::isMoveInstr(const MachineInstr &MI,
90                                  unsigned &SrcReg, unsigned &DstReg,
91                                  unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
92  SrcSubIdx = DstSubIdx = 0; // No sub-registers.
93
94  unsigned oc = MI.getOpcode();
95  switch (oc) {
96  default:
97    return false;
98  case ARM::tMOVr:
99  case ARM::tMOVhir2lor:
100  case ARM::tMOVlor2hir:
101  case ARM::tMOVhir2hir:
102    assert(MI.getDesc().getNumOperands() >= 2 &&
103           MI.getOperand(0).isReg() &&
104           MI.getOperand(1).isReg() &&
105           "Invalid Thumb MOV instruction");
106    SrcReg = MI.getOperand(1).getReg();
107    DstReg = MI.getOperand(0).getReg();
108    return true;
109  }
110}
111
112unsigned Thumb1InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
113                                              int &FrameIndex) const {
114  switch (MI->getOpcode()) {
115  default: break;
116  case ARM::tRestore:
117    if (MI->getOperand(1).isFI() &&
118        MI->getOperand(2).isImm() &&
119        MI->getOperand(2).getImm() == 0) {
120      FrameIndex = MI->getOperand(1).getIndex();
121      return MI->getOperand(0).getReg();
122    }
123    break;
124  }
125  return 0;
126}
127
128unsigned Thumb1InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
129                                             int &FrameIndex) const {
130  switch (MI->getOpcode()) {
131  default: break;
132  case ARM::tSpill:
133    if (MI->getOperand(1).isFI() &&
134        MI->getOperand(2).isImm() &&
135        MI->getOperand(2).getImm() == 0) {
136      FrameIndex = MI->getOperand(1).getIndex();
137      return MI->getOperand(0).getReg();
138    }
139    break;
140  }
141  return 0;
142}
143
144bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
145                                   MachineBasicBlock::iterator I,
146                                   unsigned DestReg, unsigned SrcReg,
147                                   const TargetRegisterClass *DestRC,
148                                   const TargetRegisterClass *SrcRC) const {
149  DebugLoc DL = DebugLoc::getUnknownLoc();
150  if (I != MBB.end()) DL = I->getDebugLoc();
151
152  if (DestRC == ARM::GPRRegisterClass) {
153    if (SrcRC == ARM::GPRRegisterClass) {
154      BuildMI(MBB, I, DL, get(ARM::tMOVhir2hir), DestReg).addReg(SrcReg);
155      return true;
156    } else if (SrcRC == ARM::tGPRRegisterClass) {
157      BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
158      return true;
159    }
160  } else if (DestRC == ARM::tGPRRegisterClass) {
161    if (SrcRC == ARM::GPRRegisterClass) {
162      BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
163      return true;
164    } else if (SrcRC == ARM::tGPRRegisterClass) {
165      BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
166      return true;
167    }
168  }
169
170  return false;
171}
172
173bool Thumb1InstrInfo::
174canFoldMemoryOperand(const MachineInstr *MI,
175                     const SmallVectorImpl<unsigned> &Ops) const {
176  if (Ops.size() != 1) return false;
177
178  unsigned OpNum = Ops[0];
179  unsigned Opc = MI->getOpcode();
180  switch (Opc) {
181  default: break;
182  case ARM::tMOVr:
183  case ARM::tMOVlor2hir:
184  case ARM::tMOVhir2lor:
185  case ARM::tMOVhir2hir: {
186    if (OpNum == 0) { // move -> store
187      unsigned SrcReg = MI->getOperand(1).getReg();
188      if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
189        // tSpill cannot take a high register operand.
190        return false;
191    } else {          // move -> load
192      unsigned DstReg = MI->getOperand(0).getReg();
193      if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
194        // tRestore cannot target a high register operand.
195        return false;
196    }
197    return true;
198  }
199  }
200
201  return false;
202}
203
204void Thumb1InstrInfo::
205storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
206                    unsigned SrcReg, bool isKill, int FI,
207                    const TargetRegisterClass *RC) const {
208  DebugLoc DL = DebugLoc::getUnknownLoc();
209  if (I != MBB.end()) DL = I->getDebugLoc();
210
211  assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
212
213  if (RC == ARM::tGPRRegisterClass) {
214    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
215                   .addReg(SrcReg, getKillRegState(isKill))
216                   .addFrameIndex(FI).addImm(0));
217  }
218}
219
220void Thumb1InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
221                                     bool isKill,
222                                     SmallVectorImpl<MachineOperand> &Addr,
223                                     const TargetRegisterClass *RC,
224                                     SmallVectorImpl<MachineInstr*> &NewMIs) const{
225  DebugLoc DL = DebugLoc::getUnknownLoc();
226  unsigned Opc = 0;
227
228  assert(RC == ARM::GPRRegisterClass && "Unknown regclass!");
229  if (RC == ARM::GPRRegisterClass) {
230    Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
231  }
232
233  MachineInstrBuilder MIB =
234    BuildMI(MF, DL,  get(Opc)).addReg(SrcReg, getKillRegState(isKill));
235  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
236    MIB.addOperand(Addr[i]);
237  AddDefaultPred(MIB);
238  NewMIs.push_back(MIB);
239  return;
240}
241
242void Thumb1InstrInfo::
243loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
244                     unsigned DestReg, int FI,
245                     const TargetRegisterClass *RC) const {
246  DebugLoc DL = DebugLoc::getUnknownLoc();
247  if (I != MBB.end()) DL = I->getDebugLoc();
248
249  assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
250
251  if (RC == ARM::tGPRRegisterClass) {
252    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
253                   .addFrameIndex(FI).addImm(0));
254  }
255}
256
257void Thumb1InstrInfo::
258loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
259                SmallVectorImpl<MachineOperand> &Addr,
260                const TargetRegisterClass *RC,
261                SmallVectorImpl<MachineInstr*> &NewMIs) const {
262  DebugLoc DL = DebugLoc::getUnknownLoc();
263  unsigned Opc = 0;
264
265  if (RC == ARM::GPRRegisterClass) {
266    Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
267  }
268
269  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
270  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
271    MIB.addOperand(Addr[i]);
272  AddDefaultPred(MIB);
273  NewMIs.push_back(MIB);
274  return;
275}
276
277bool Thumb1InstrInfo::
278spillCalleeSavedRegisters(MachineBasicBlock &MBB,
279                          MachineBasicBlock::iterator MI,
280                          const std::vector<CalleeSavedInfo> &CSI) const {
281  if (CSI.empty())
282    return false;
283
284  DebugLoc DL = DebugLoc::getUnknownLoc();
285  if (MI != MBB.end()) DL = MI->getDebugLoc();
286
287  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
288  for (unsigned i = CSI.size(); i != 0; --i) {
289    unsigned Reg = CSI[i-1].getReg();
290    // Add the callee-saved register as live-in. It's killed at the spill.
291    MBB.addLiveIn(Reg);
292    MIB.addReg(Reg, RegState::Kill);
293  }
294  return true;
295}
296
297bool Thumb1InstrInfo::
298restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
299                            MachineBasicBlock::iterator MI,
300                            const std::vector<CalleeSavedInfo> &CSI) const {
301  MachineFunction &MF = *MBB.getParent();
302  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
303  if (CSI.empty())
304    return false;
305
306  bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
307  MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
308  for (unsigned i = CSI.size(); i != 0; --i) {
309    unsigned Reg = CSI[i-1].getReg();
310    if (Reg == ARM::LR) {
311      // Special epilogue for vararg functions. See emitEpilogue
312      if (isVarArg)
313        continue;
314      Reg = ARM::PC;
315      PopMI->setDesc(get(ARM::tPOP_RET));
316      MI = MBB.erase(MI);
317    }
318    PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
319  }
320
321  // It's illegal to emit pop instruction without operands.
322  if (PopMI->getNumOperands() > 0)
323    MBB.insert(MI, PopMI);
324
325  return true;
326}
327
328MachineInstr *Thumb1InstrInfo::
329foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
330                      const SmallVectorImpl<unsigned> &Ops, int FI) const {
331  if (Ops.size() != 1) return NULL;
332
333  unsigned OpNum = Ops[0];
334  unsigned Opc = MI->getOpcode();
335  MachineInstr *NewMI = NULL;
336  switch (Opc) {
337  default: break;
338  case ARM::tMOVr:
339  case ARM::tMOVlor2hir:
340  case ARM::tMOVhir2lor:
341  case ARM::tMOVhir2hir: {
342    if (OpNum == 0) { // move -> store
343      unsigned SrcReg = MI->getOperand(1).getReg();
344      bool isKill = MI->getOperand(1).isKill();
345      if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
346        // tSpill cannot take a high register operand.
347        break;
348      NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
349                             .addReg(SrcReg, getKillRegState(isKill))
350                             .addFrameIndex(FI).addImm(0));
351    } else {          // move -> load
352      unsigned DstReg = MI->getOperand(0).getReg();
353      if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
354        // tRestore cannot target a high register operand.
355        break;
356      bool isDead = MI->getOperand(0).isDead();
357      NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
358                             .addReg(DstReg,
359                                     RegState::Define | getDeadRegState(isDead))
360                             .addFrameIndex(FI).addImm(0));
361    }
362    break;
363  }
364  }
365
366  return NewMI;
367}
368