Thumb2RegisterInfo.cpp revision 62d1723a9cbce2019aac862f51952a58146a6bf0 
1//===- Thumb2RegisterInfo.cpp - Thumb-2 Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-2 implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMMachineFunctionInfo.h"
18#include "ARMSubtarget.h"
19#include "Thumb2InstrInfo.h"
20#include "Thumb2RegisterInfo.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/Target/TargetFrameInfo.h"
32#include "llvm/Target/TargetMachine.h"
33#include "llvm/ADT/BitVector.h"
34#include "llvm/ADT/SmallVector.h"
35#include "llvm/Support/ErrorHandling.h"
36using namespace llvm;
37
38Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
39                                       const ARMSubtarget &sti)
40  : ARMBaseRegisterInfo(tii, sti) {
41}
42
43/// emitLoadConstPool - Emits a load from constpool to materialize the
44/// specified immediate.
45void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
46                                           MachineBasicBlock::iterator &MBBI,
47                                           DebugLoc dl,
48                                           unsigned DestReg, unsigned SubIdx,
49                                           int Val,
50                                           ARMCC::CondCodes Pred,
51                                           unsigned PredReg) const {
52  MachineFunction &MF = *MBB.getParent();
53  MachineConstantPool *ConstantPool = MF.getConstantPool();
54  Constant *C = ConstantInt::get(
55           Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
56  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
57
58  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
59    .addReg(DestReg, getDefRegState(true), SubIdx)
60    .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0);
61}
62
63bool Thumb2RegisterInfo::
64requiresRegisterScavenging(const MachineFunction &MF) const {
65  return true;
66}
67