Thumb2SizeReduction.cpp revision ee04a6d3a40c3017124e3fd89a0db473a2824498
1//===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "t2-reduce-size" 11#include "ARM.h" 12#include "ARMBaseRegisterInfo.h" 13#include "ARMBaseInstrInfo.h" 14#include "ARMSubtarget.h" 15#include "Thumb2InstrInfo.h" 16#include "MCTargetDesc/ARMAddressingModes.h" 17#include "llvm/CodeGen/MachineInstr.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/MachineFunctionPass.h" 20#include "llvm/Support/CommandLine.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Support/raw_ostream.h" 23#include "llvm/ADT/DenseMap.h" 24#include "llvm/ADT/Statistic.h" 25using namespace llvm; 26 27STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones"); 28STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones"); 29STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones"); 30 31static cl::opt<int> ReduceLimit("t2-reduce-limit", 32 cl::init(-1), cl::Hidden); 33static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2", 34 cl::init(-1), cl::Hidden); 35static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3", 36 cl::init(-1), cl::Hidden); 37 38namespace { 39 /// ReduceTable - A static table with information on mapping from wide 40 /// opcodes to narrow 41 struct ReduceEntry { 42 unsigned WideOpc; // Wide opcode 43 unsigned NarrowOpc1; // Narrow opcode to transform to 44 unsigned NarrowOpc2; // Narrow opcode when it's two-address 45 uint8_t Imm1Limit; // Limit of immediate field (bits) 46 uint8_t Imm2Limit; // Limit of immediate field when it's two-address 47 unsigned LowRegs1 : 1; // Only possible if low-registers are used 48 unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr) 49 unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa. 50 // 1 - No cc field. 51 // 2 - Always set CPSR. 52 unsigned PredCC2 : 2; 53 unsigned PartFlag : 1; // 16-bit instruction does partial flag update 54 unsigned Special : 1; // Needs to be dealt with specially 55 }; 56 57 static const ReduceEntry ReduceTable[] = { 58 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, PF, S 59 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0 }, 60 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1 }, 61 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0 }, 62 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1 }, 63 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1 }, 64 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0 }, 65 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0 }, 66 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0 }, 67 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0 }, 68 //FIXME: Disable CMN, as CCodes are backwards from compare expectations 69 //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0,0 }, 70 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0 }, 71 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1 }, 72 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0 }, 73 // FIXME: adr.n immediate offset must be multiple of 4. 74 //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0,0 }, 75 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0 }, 76 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0 }, 77 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0 }, 78 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0 }, 79 // FIXME: tMOVi8 and tMVN also partially update CPSR but they are less 80 // likely to cause issue in the loop. As a size / performance workaround, 81 // they are not marked as such. 82 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,0 }, 83 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,1 }, 84 // FIXME: Do we need the 16-bit 'S' variant? 85 { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0 }, 86 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0 }, 87 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0 }, 88 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0 }, 89 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0 }, 90 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0 }, 91 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0 }, 92 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0 }, 93 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1 }, 94 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1 }, 95 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0 }, 96 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0 }, 97 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0 }, 98 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0 }, 99 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0 }, 100 { ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,0 }, 101 { ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,0 }, 102 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0 }, 103 { ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,0 }, 104 { ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,0 }, 105 106 // FIXME: Clean this up after splitting each Thumb load / store opcode 107 // into multiple ones. 108 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1 }, 109 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1 }, 110 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1 }, 111 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1 }, 112 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1 }, 113 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1 }, 114 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1 }, 115 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1 }, 116 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1 }, 117 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1 }, 118 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1 }, 119 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1 }, 120 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1 }, 121 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1 }, 122 123 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1 }, 124 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1 }, 125 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1 }, 126 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent 127 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1 }, 128 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1 }, 129 }; 130 131 class Thumb2SizeReduce : public MachineFunctionPass { 132 public: 133 static char ID; 134 Thumb2SizeReduce(); 135 136 const Thumb2InstrInfo *TII; 137 const ARMSubtarget *STI; 138 139 virtual bool runOnMachineFunction(MachineFunction &MF); 140 141 virtual const char *getPassName() const { 142 return "Thumb2 instruction size reduction pass"; 143 } 144 145 private: 146 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable. 147 DenseMap<unsigned, unsigned> ReduceOpcodeMap; 148 149 bool canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use); 150 151 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry, 152 bool is2Addr, ARMCC::CondCodes Pred, 153 bool LiveCPSR, bool &HasCC, bool &CCDead); 154 155 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, 156 const ReduceEntry &Entry); 157 158 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, 159 const ReduceEntry &Entry, bool LiveCPSR, 160 MachineInstr *CPSRDef); 161 162 /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address 163 /// instruction. 164 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI, 165 const ReduceEntry &Entry, 166 bool LiveCPSR, MachineInstr *CPSRDef); 167 168 /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit 169 /// non-two-address instruction. 170 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI, 171 const ReduceEntry &Entry, 172 bool LiveCPSR, MachineInstr *CPSRDef); 173 174 /// ReduceMBB - Reduce width of instructions in the specified basic block. 175 bool ReduceMBB(MachineBasicBlock &MBB); 176 }; 177 char Thumb2SizeReduce::ID = 0; 178} 179 180Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(ID) { 181 for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) { 182 unsigned FromOpc = ReduceTable[i].WideOpc; 183 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second) 184 assert(false && "Duplicated entries?"); 185 } 186} 187 188static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { 189 for (const unsigned *Regs = MCID.ImplicitDefs; *Regs; ++Regs) 190 if (*Regs == ARM::CPSR) 191 return true; 192 return false; 193} 194 195/// canAddPseudoFlagDep - For A9 (and other out-of-order) implementations, 196/// the 's' 16-bit instruction partially update CPSR. Abort the 197/// transformation to avoid adding false dependency on last CPSR setting 198/// instruction which hurts the ability for out-of-order execution engine 199/// to do register renaming magic. 200/// This function checks if there is a read-of-write dependency between the 201/// last instruction that defines the CPSR and the current instruction. If there 202/// is, then there is no harm done since the instruction cannot be retired 203/// before the CPSR setting instruction anyway. 204/// Note, we are not doing full dependency analysis here for the sake of compile 205/// time. We're not looking for cases like: 206/// r0 = muls ... 207/// r1 = add.w r0, ... 208/// ... 209/// = mul.w r1 210/// In this case it would have been ok to narrow the mul.w to muls since there 211/// are indirect RAW dependency between the muls and the mul.w 212bool 213Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use) { 214 if (!Def || !STI->avoidCPSRPartialUpdate()) 215 return false; 216 217 SmallSet<unsigned, 2> Defs; 218 for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) { 219 const MachineOperand &MO = Def->getOperand(i); 220 if (!MO.isReg() || MO.isUndef() || MO.isUse()) 221 continue; 222 unsigned Reg = MO.getReg(); 223 if (Reg == 0 || Reg == ARM::CPSR) 224 continue; 225 Defs.insert(Reg); 226 } 227 228 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 229 const MachineOperand &MO = Use->getOperand(i); 230 if (!MO.isReg() || MO.isUndef() || MO.isDef()) 231 continue; 232 unsigned Reg = MO.getReg(); 233 if (Defs.count(Reg)) 234 return false; 235 } 236 237 // No read-after-write dependency. The narrowing will add false dependency. 238 return true; 239} 240 241bool 242Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry, 243 bool is2Addr, ARMCC::CondCodes Pred, 244 bool LiveCPSR, bool &HasCC, bool &CCDead) { 245 if ((is2Addr && Entry.PredCC2 == 0) || 246 (!is2Addr && Entry.PredCC1 == 0)) { 247 if (Pred == ARMCC::AL) { 248 // Not predicated, must set CPSR. 249 if (!HasCC) { 250 // Original instruction was not setting CPSR, but CPSR is not 251 // currently live anyway. It's ok to set it. The CPSR def is 252 // dead though. 253 if (!LiveCPSR) { 254 HasCC = true; 255 CCDead = true; 256 return true; 257 } 258 return false; 259 } 260 } else { 261 // Predicated, must not set CPSR. 262 if (HasCC) 263 return false; 264 } 265 } else if ((is2Addr && Entry.PredCC2 == 2) || 266 (!is2Addr && Entry.PredCC1 == 2)) { 267 /// Old opcode has an optional def of CPSR. 268 if (HasCC) 269 return true; 270 // If old opcode does not implicitly define CPSR, then it's not ok since 271 // these new opcodes' CPSR def is not meant to be thrown away. e.g. CMP. 272 if (!HasImplicitCPSRDef(MI->getDesc())) 273 return false; 274 HasCC = true; 275 } else { 276 // 16-bit instruction does not set CPSR. 277 if (HasCC) 278 return false; 279 } 280 281 return true; 282} 283 284static bool VerifyLowRegs(MachineInstr *MI) { 285 unsigned Opc = MI->getOpcode(); 286 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA || 287 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD || 288 Opc == ARM::t2LDMDB_UPD); 289 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD); 290 bool isSPOk = isPCOk || isLROk; 291 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 292 const MachineOperand &MO = MI->getOperand(i); 293 if (!MO.isReg() || MO.isImplicit()) 294 continue; 295 unsigned Reg = MO.getReg(); 296 if (Reg == 0 || Reg == ARM::CPSR) 297 continue; 298 if (isPCOk && Reg == ARM::PC) 299 continue; 300 if (isLROk && Reg == ARM::LR) 301 continue; 302 if (Reg == ARM::SP) { 303 if (isSPOk) 304 continue; 305 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)) 306 // Special case for these ldr / str with sp as base register. 307 continue; 308 } 309 if (!isARMLowRegister(Reg)) 310 return false; 311 } 312 return true; 313} 314 315bool 316Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, 317 const ReduceEntry &Entry) { 318 if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt)) 319 return false; 320 321 unsigned Scale = 1; 322 bool HasImmOffset = false; 323 bool HasShift = false; 324 bool HasOffReg = true; 325 bool isLdStMul = false; 326 unsigned Opc = Entry.NarrowOpc1; 327 unsigned OpNum = 3; // First 'rest' of operands. 328 uint8_t ImmLimit = Entry.Imm1Limit; 329 330 switch (Entry.WideOpc) { 331 default: 332 llvm_unreachable("Unexpected Thumb2 load / store opcode!"); 333 case ARM::t2LDRi12: 334 case ARM::t2STRi12: 335 if (MI->getOperand(1).getReg() == ARM::SP) { 336 Opc = Entry.NarrowOpc2; 337 ImmLimit = Entry.Imm2Limit; 338 HasOffReg = false; 339 } 340 341 Scale = 4; 342 HasImmOffset = true; 343 HasOffReg = false; 344 break; 345 case ARM::t2LDRBi12: 346 case ARM::t2STRBi12: 347 HasImmOffset = true; 348 HasOffReg = false; 349 break; 350 case ARM::t2LDRHi12: 351 case ARM::t2STRHi12: 352 Scale = 2; 353 HasImmOffset = true; 354 HasOffReg = false; 355 break; 356 case ARM::t2LDRs: 357 case ARM::t2LDRBs: 358 case ARM::t2LDRHs: 359 case ARM::t2LDRSBs: 360 case ARM::t2LDRSHs: 361 case ARM::t2STRs: 362 case ARM::t2STRBs: 363 case ARM::t2STRHs: 364 HasShift = true; 365 OpNum = 4; 366 break; 367 case ARM::t2LDMIA: 368 case ARM::t2LDMDB: { 369 unsigned BaseReg = MI->getOperand(0).getReg(); 370 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA) 371 return false; 372 373 // For the non-writeback version (this one), the base register must be 374 // one of the registers being loaded. 375 bool isOK = false; 376 for (unsigned i = 4; i < MI->getNumOperands(); ++i) { 377 if (MI->getOperand(i).getReg() == BaseReg) { 378 isOK = true; 379 break; 380 } 381 } 382 383 if (!isOK) 384 return false; 385 386 OpNum = 0; 387 isLdStMul = true; 388 break; 389 } 390 case ARM::t2LDMIA_RET: { 391 unsigned BaseReg = MI->getOperand(1).getReg(); 392 if (BaseReg != ARM::SP) 393 return false; 394 Opc = Entry.NarrowOpc2; // tPOP_RET 395 OpNum = 2; 396 isLdStMul = true; 397 break; 398 } 399 case ARM::t2LDMIA_UPD: 400 case ARM::t2LDMDB_UPD: 401 case ARM::t2STMIA_UPD: 402 case ARM::t2STMDB_UPD: { 403 OpNum = 0; 404 405 unsigned BaseReg = MI->getOperand(1).getReg(); 406 if (BaseReg == ARM::SP && 407 (Entry.WideOpc == ARM::t2LDMIA_UPD || 408 Entry.WideOpc == ARM::t2STMDB_UPD)) { 409 Opc = Entry.NarrowOpc2; // tPOP or tPUSH 410 OpNum = 2; 411 } else if (!isARMLowRegister(BaseReg) || 412 (Entry.WideOpc != ARM::t2LDMIA_UPD && 413 Entry.WideOpc != ARM::t2STMIA_UPD)) { 414 return false; 415 } 416 417 isLdStMul = true; 418 break; 419 } 420 } 421 422 unsigned OffsetReg = 0; 423 bool OffsetKill = false; 424 if (HasShift) { 425 OffsetReg = MI->getOperand(2).getReg(); 426 OffsetKill = MI->getOperand(2).isKill(); 427 428 if (MI->getOperand(3).getImm()) 429 // Thumb1 addressing mode doesn't support shift. 430 return false; 431 } 432 433 unsigned OffsetImm = 0; 434 if (HasImmOffset) { 435 OffsetImm = MI->getOperand(2).getImm(); 436 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale; 437 438 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset) 439 // Make sure the immediate field fits. 440 return false; 441 } 442 443 // Add the 16-bit load / store instruction. 444 DebugLoc dl = MI->getDebugLoc(); 445 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc)); 446 if (!isLdStMul) { 447 MIB.addOperand(MI->getOperand(0)); 448 MIB.addOperand(MI->getOperand(1)); 449 450 if (HasImmOffset) 451 MIB.addImm(OffsetImm / Scale); 452 453 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); 454 455 if (HasOffReg) 456 MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); 457 } 458 459 // Transfer the rest of operands. 460 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum) 461 MIB.addOperand(MI->getOperand(OpNum)); 462 463 // Transfer memoperands. 464 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 465 466 // Transfer MI flags. 467 MIB.setMIFlags(MI->getFlags()); 468 469 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); 470 471 MBB.erase(MI); 472 ++NumLdSts; 473 return true; 474} 475 476bool 477Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, 478 const ReduceEntry &Entry, 479 bool LiveCPSR, MachineInstr *CPSRDef) { 480 unsigned Opc = MI->getOpcode(); 481 if (Opc == ARM::t2ADDri) { 482 // If the source register is SP, try to reduce to tADDrSPi, otherwise 483 // it's a normal reduce. 484 if (MI->getOperand(1).getReg() != ARM::SP) { 485 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef)) 486 return true; 487 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); 488 } 489 // Try to reduce to tADDrSPi. 490 unsigned Imm = MI->getOperand(2).getImm(); 491 // The immediate must be in range, the destination register must be a low 492 // reg, the predicate must be "always" and the condition flags must not 493 // be being set. 494 if (Imm & 3 || Imm > 1020) 495 return false; 496 if (!isARMLowRegister(MI->getOperand(0).getReg())) 497 return false; 498 if (MI->getOperand(3).getImm() != ARMCC::AL) 499 return false; 500 const MCInstrDesc &MCID = MI->getDesc(); 501 if (MCID.hasOptionalDef() && 502 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) 503 return false; 504 505 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), 506 TII->get(ARM::tADDrSPi)) 507 .addOperand(MI->getOperand(0)) 508 .addOperand(MI->getOperand(1)) 509 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four. 510 511 // Transfer MI flags. 512 MIB.setMIFlags(MI->getFlags()); 513 514 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB); 515 516 MBB.erase(MI); 517 ++NumNarrows; 518 return true; 519 } 520 521 if (Entry.LowRegs1 && !VerifyLowRegs(MI)) 522 return false; 523 524 const MCInstrDesc &MCID = MI->getDesc(); 525 if (MCID.mayLoad() || MCID.mayStore()) 526 return ReduceLoadStore(MBB, MI, Entry); 527 528 switch (Opc) { 529 default: break; 530 case ARM::t2ADDSri: 531 case ARM::t2ADDSrr: { 532 unsigned PredReg = 0; 533 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { 534 switch (Opc) { 535 default: break; 536 case ARM::t2ADDSri: { 537 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef)) 538 return true; 539 // fallthrough 540 } 541 case ARM::t2ADDSrr: 542 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); 543 } 544 } 545 break; 546 } 547 case ARM::t2RSBri: 548 case ARM::t2RSBSri: 549 if (MI->getOperand(2).getImm() == 0) 550 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); 551 break; 552 case ARM::t2MOVi16: 553 // Can convert only 'pure' immediate operands, not immediates obtained as 554 // globals' addresses. 555 if (MI->getOperand(1).isImm()) 556 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); 557 break; 558 case ARM::t2CMPrr: { 559 // Try to reduce to the lo-reg only version first. Why there are two 560 // versions of the instruction is a mystery. 561 // It would be nice to just have two entries in the master table that 562 // are prioritized, but the table assumes a unique entry for each 563 // source insn opcode. So for now, we hack a local entry record to use. 564 static const ReduceEntry NarrowEntry = 565 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1 }; 566 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef)) 567 return true; 568 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); 569 } 570 } 571 return false; 572} 573 574bool 575Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI, 576 const ReduceEntry &Entry, 577 bool LiveCPSR, MachineInstr *CPSRDef) { 578 579 if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr)) 580 return false; 581 582 unsigned Reg0 = MI->getOperand(0).getReg(); 583 unsigned Reg1 = MI->getOperand(1).getReg(); 584 if (Reg0 != Reg1) { 585 // Try to commute the operands to make it a 2-address instruction. 586 unsigned CommOpIdx1, CommOpIdx2; 587 if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) || 588 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0) 589 return false; 590 MachineInstr *CommutedMI = TII->commuteInstruction(MI); 591 if (!CommutedMI) 592 return false; 593 } 594 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) 595 return false; 596 if (Entry.Imm2Limit) { 597 unsigned Imm = MI->getOperand(2).getImm(); 598 unsigned Limit = (1 << Entry.Imm2Limit) - 1; 599 if (Imm > Limit) 600 return false; 601 } else { 602 unsigned Reg2 = MI->getOperand(2).getReg(); 603 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) 604 return false; 605 } 606 607 // Check if it's possible / necessary to transfer the predicate. 608 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2); 609 unsigned PredReg = 0; 610 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 611 bool SkipPred = false; 612 if (Pred != ARMCC::AL) { 613 if (!NewMCID.isPredicable()) 614 // Can't transfer predicate, fail. 615 return false; 616 } else { 617 SkipPred = !NewMCID.isPredicable(); 618 } 619 620 bool HasCC = false; 621 bool CCDead = false; 622 const MCInstrDesc &MCID = MI->getDesc(); 623 if (MCID.hasOptionalDef()) { 624 unsigned NumOps = MCID.getNumOperands(); 625 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); 626 if (HasCC && MI->getOperand(NumOps-1).isDead()) 627 CCDead = true; 628 } 629 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead)) 630 return false; 631 632 // Avoid adding a false dependency on partial flag update by some 16-bit 633 // instructions which has the 's' bit set. 634 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC && 635 canAddPseudoFlagDep(CPSRDef, MI)) 636 return false; 637 638 // Add the 16-bit instruction. 639 DebugLoc dl = MI->getDebugLoc(); 640 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewMCID); 641 MIB.addOperand(MI->getOperand(0)); 642 if (NewMCID.hasOptionalDef()) { 643 if (HasCC) 644 AddDefaultT1CC(MIB, CCDead); 645 else 646 AddNoT1CC(MIB); 647 } 648 649 // Transfer the rest of operands. 650 unsigned NumOps = MCID.getNumOperands(); 651 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 652 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) 653 continue; 654 if (SkipPred && MCID.OpInfo[i].isPredicate()) 655 continue; 656 MIB.addOperand(MI->getOperand(i)); 657 } 658 659 // Transfer MI flags. 660 MIB.setMIFlags(MI->getFlags()); 661 662 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); 663 664 MBB.erase(MI); 665 ++Num2Addrs; 666 return true; 667} 668 669bool 670Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI, 671 const ReduceEntry &Entry, 672 bool LiveCPSR, MachineInstr *CPSRDef) { 673 if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit)) 674 return false; 675 676 unsigned Limit = ~0U; 677 if (Entry.Imm1Limit) 678 Limit = (1 << Entry.Imm1Limit) - 1; 679 680 const MCInstrDesc &MCID = MI->getDesc(); 681 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { 682 if (MCID.OpInfo[i].isPredicate()) 683 continue; 684 const MachineOperand &MO = MI->getOperand(i); 685 if (MO.isReg()) { 686 unsigned Reg = MO.getReg(); 687 if (!Reg || Reg == ARM::CPSR) 688 continue; 689 if (Entry.LowRegs1 && !isARMLowRegister(Reg)) 690 return false; 691 } else if (MO.isImm() && 692 !MCID.OpInfo[i].isPredicate()) { 693 if (((unsigned)MO.getImm()) > Limit) 694 return false; 695 } 696 } 697 698 // Check if it's possible / necessary to transfer the predicate. 699 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1); 700 unsigned PredReg = 0; 701 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 702 bool SkipPred = false; 703 if (Pred != ARMCC::AL) { 704 if (!NewMCID.isPredicable()) 705 // Can't transfer predicate, fail. 706 return false; 707 } else { 708 SkipPred = !NewMCID.isPredicable(); 709 } 710 711 bool HasCC = false; 712 bool CCDead = false; 713 if (MCID.hasOptionalDef()) { 714 unsigned NumOps = MCID.getNumOperands(); 715 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); 716 if (HasCC && MI->getOperand(NumOps-1).isDead()) 717 CCDead = true; 718 } 719 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead)) 720 return false; 721 722 // Avoid adding a false dependency on partial flag update by some 16-bit 723 // instructions which has the 's' bit set. 724 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC && 725 canAddPseudoFlagDep(CPSRDef, MI)) 726 return false; 727 728 // Add the 16-bit instruction. 729 DebugLoc dl = MI->getDebugLoc(); 730 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewMCID); 731 MIB.addOperand(MI->getOperand(0)); 732 if (NewMCID.hasOptionalDef()) { 733 if (HasCC) 734 AddDefaultT1CC(MIB, CCDead); 735 else 736 AddNoT1CC(MIB); 737 } 738 739 // Transfer the rest of operands. 740 unsigned NumOps = MCID.getNumOperands(); 741 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 742 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) 743 continue; 744 if ((MCID.getOpcode() == ARM::t2RSBSri || 745 MCID.getOpcode() == ARM::t2RSBri) && i == 2) 746 // Skip the zero immediate operand, it's now implicit. 747 continue; 748 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate()); 749 if (SkipPred && isPred) 750 continue; 751 const MachineOperand &MO = MI->getOperand(i); 752 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) 753 // Skip implicit def of CPSR. Either it's modeled as an optional 754 // def now or it's already an implicit def on the new instruction. 755 continue; 756 MIB.addOperand(MO); 757 } 758 if (!MCID.isPredicable() && NewMCID.isPredicable()) 759 AddDefaultPred(MIB); 760 761 // Transfer MI flags. 762 MIB.setMIFlags(MI->getFlags()); 763 764 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); 765 766 MBB.erase(MI); 767 ++NumNarrows; 768 return true; 769} 770 771static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) { 772 bool HasDef = false; 773 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 774 const MachineOperand &MO = MI.getOperand(i); 775 if (!MO.isReg() || MO.isUndef() || MO.isUse()) 776 continue; 777 if (MO.getReg() != ARM::CPSR) 778 continue; 779 780 DefCPSR = true; 781 if (!MO.isDead()) 782 HasDef = true; 783 } 784 785 return HasDef || LiveCPSR; 786} 787 788static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) { 789 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 790 const MachineOperand &MO = MI.getOperand(i); 791 if (!MO.isReg() || MO.isUndef() || MO.isDef()) 792 continue; 793 if (MO.getReg() != ARM::CPSR) 794 continue; 795 assert(LiveCPSR && "CPSR liveness tracking is wrong!"); 796 if (MO.isKill()) { 797 LiveCPSR = false; 798 break; 799 } 800 } 801 802 return LiveCPSR; 803} 804 805bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) { 806 bool Modified = false; 807 808 // Yes, CPSR could be livein. 809 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR); 810 MachineInstr *CPSRDef = 0; 811 812 MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); 813 MachineBasicBlock::iterator NextMII; 814 for (; MII != E; MII = NextMII) { 815 NextMII = llvm::next(MII); 816 817 MachineInstr *MI = &*MII; 818 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR); 819 820 unsigned Opcode = MI->getOpcode(); 821 DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode); 822 if (OPI != ReduceOpcodeMap.end()) { 823 const ReduceEntry &Entry = ReduceTable[OPI->second]; 824 // Ignore "special" cases for now. 825 if (Entry.Special) { 826 if (ReduceSpecial(MBB, MI, Entry, LiveCPSR, CPSRDef)) { 827 Modified = true; 828 MachineBasicBlock::iterator I = prior(NextMII); 829 MI = &*I; 830 } 831 goto ProcessNext; 832 } 833 834 // Try to transform to a 16-bit two-address instruction. 835 if (Entry.NarrowOpc2 && 836 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef)) { 837 Modified = true; 838 MachineBasicBlock::iterator I = prior(NextMII); 839 MI = &*I; 840 goto ProcessNext; 841 } 842 843 // Try to transform to a 16-bit non-two-address instruction. 844 if (Entry.NarrowOpc1 && 845 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef)) { 846 Modified = true; 847 MachineBasicBlock::iterator I = prior(NextMII); 848 MI = &*I; 849 } 850 } 851 852 ProcessNext: 853 bool DefCPSR = false; 854 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR); 855 if (MI->getDesc().isCall()) 856 // Calls don't really set CPSR. 857 CPSRDef = 0; 858 else if (DefCPSR) 859 // This is the last CPSR defining instruction. 860 CPSRDef = MI; 861 } 862 863 return Modified; 864} 865 866bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) { 867 const TargetMachine &TM = MF.getTarget(); 868 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo()); 869 STI = &TM.getSubtarget<ARMSubtarget>(); 870 871 bool Modified = false; 872 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) 873 Modified |= ReduceMBB(*I); 874 return Modified; 875} 876 877/// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size 878/// reduction pass. 879FunctionPass *llvm::createThumb2SizeReductionPass() { 880 return new Thumb2SizeReduce(); 881} 882