131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- SPURegisterInfo.cpp - Cell SPU Register Information ---------------===// 2564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel// 3564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel// The LLVM Compiler Infrastructure 4564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel// 8564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel//===----------------------------------------------------------------------===// 9564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel// 106f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman// This file contains the Cell implementation of the TargetRegisterInfo class. 11564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel// 12564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel//===----------------------------------------------------------------------===// 13564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 14564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#define DEBUG_TYPE "reginfo" 15564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "SPURegisterInfo.h" 1679aa3417eb6f58d668aadfedf075240a41d35a26Craig Topper#include "SPU.h" 17564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "SPUInstrBuilder.h" 18564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "SPUSubtarget.h" 19564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "SPUMachineFunction.h" 2016c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "SPUFrameLowering.h" 21564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/Constants.h" 22564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/Type.h" 23564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/CodeGen/ValueTypes.h" 24564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/CodeGen/MachineInstrBuilder.h" 25564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/CodeGen/MachineModuleInfo.h" 26564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/CodeGen/MachineFunction.h" 27564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/CodeGen/MachineFrameInfo.h" 2884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 29e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner#include "llvm/CodeGen/RegisterScavenging.h" 30564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/CodeGen/ValueTypes.h" 3116c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "llvm/Target/TargetFrameLowering.h" 32564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/Target/TargetInstrInfo.h" 33564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/Target/TargetMachine.h" 34564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/Target/TargetOptions.h" 35564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/Support/CommandLine.h" 36564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/Support/Debug.h" 37dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/ErrorHandling.h" 38564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/Support/MathExtras.h" 39dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 40564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/ADT/BitVector.h" 41564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include "llvm/ADT/STLExtras.h" 42564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel#include <cstdlib> 4373f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng 4473f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#define GET_REGINFO_TARGET_DESC 45a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include "SPUGenRegisterInfo.inc" 46564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 47564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michelusing namespace llvm; 48564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 49564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel/// getRegisterNumbering - Given the enum value for some register, e.g. 50564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel/// PPC::F14, return the number that it corresponds to (e.g. 14). 51564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michelunsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) { 52564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel using namespace SPU; 53564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel switch (RegEnum) { 54564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R0: return 0; 55564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R1: return 1; 56564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R2: return 2; 57564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R3: return 3; 58564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R4: return 4; 59564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R5: return 5; 60564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R6: return 6; 61564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R7: return 7; 62564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R8: return 8; 63564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R9: return 9; 64564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R10: return 10; 65564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R11: return 11; 66564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R12: return 12; 67564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R13: return 13; 68564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R14: return 14; 69564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R15: return 15; 70564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R16: return 16; 71564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R17: return 17; 72564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R18: return 18; 73564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R19: return 19; 74564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R20: return 20; 75564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R21: return 21; 76564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R22: return 22; 77564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R23: return 23; 78564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R24: return 24; 79564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R25: return 25; 80564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R26: return 26; 81564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R27: return 27; 82564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R28: return 28; 83564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R29: return 29; 84564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R30: return 30; 85564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R31: return 31; 86564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R32: return 32; 87564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R33: return 33; 88564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R34: return 34; 89564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R35: return 35; 90564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R36: return 36; 91564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R37: return 37; 92564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R38: return 38; 93564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R39: return 39; 94564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R40: return 40; 95564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R41: return 41; 96564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R42: return 42; 97564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R43: return 43; 98564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R44: return 44; 99564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R45: return 45; 100564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R46: return 46; 101564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R47: return 47; 102564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R48: return 48; 103564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R49: return 49; 104564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R50: return 50; 105564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R51: return 51; 106564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R52: return 52; 107564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R53: return 53; 108564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R54: return 54; 109564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R55: return 55; 110564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R56: return 56; 111564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R57: return 57; 112564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R58: return 58; 113564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R59: return 59; 114564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R60: return 60; 115564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R61: return 61; 116564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R62: return 62; 117564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R63: return 63; 118564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R64: return 64; 119564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R65: return 65; 120564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R66: return 66; 121564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R67: return 67; 122564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R68: return 68; 123564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R69: return 69; 124564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R70: return 70; 125564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R71: return 71; 126564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R72: return 72; 127564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R73: return 73; 128564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R74: return 74; 129564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R75: return 75; 130564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R76: return 76; 131564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R77: return 77; 132564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R78: return 78; 133564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R79: return 79; 134564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R80: return 80; 135564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R81: return 81; 136564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R82: return 82; 137564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R83: return 83; 138564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R84: return 84; 139564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R85: return 85; 140564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R86: return 86; 141564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R87: return 87; 142564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R88: return 88; 143564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R89: return 89; 144564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R90: return 90; 145564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R91: return 91; 146564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R92: return 92; 147564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R93: return 93; 148564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R94: return 94; 149564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R95: return 95; 150564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R96: return 96; 151564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R97: return 97; 152564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R98: return 98; 153564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R99: return 99; 154564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R100: return 100; 155564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R101: return 101; 156564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R102: return 102; 157564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R103: return 103; 158564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R104: return 104; 159564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R105: return 105; 160564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R106: return 106; 161564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R107: return 107; 162564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R108: return 108; 163564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R109: return 109; 164564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R110: return 110; 165564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R111: return 111; 166564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R112: return 112; 167564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R113: return 113; 168564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R114: return 114; 169564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R115: return 115; 170564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R116: return 116; 171564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R117: return 117; 172564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R118: return 118; 173564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R119: return 119; 174564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R120: return 120; 175564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R121: return 121; 176564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R122: return 122; 177564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R123: return 123; 178564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R124: return 124; 179564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R125: return 125; 180564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R126: return 126; 181564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel case SPU::R127: return 127; 182564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel default: 18375361b69f3f327842b9dad69fa7f28ae3b688412Chris Lattner report_fatal_error("Unhandled reg in SPURegisterInfo::getRegisterNumbering"); 184564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel } 185564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel} 186564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 187564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott MichelSPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget, 188564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel const TargetInstrInfo &tii) : 1890e6a052331f674dd70e28af41f654a7874405eabEvan Cheng SPUGenRegisterInfo(SPU::R0), Subtarget(subtarget), TII(tii) 190564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel{ 191564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel} 192564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 193770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng/// getPointerRegClass - Return the register class to use to hold pointers. 194770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng/// This is used for addressing modes. 1952cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerconst TargetRegisterClass * 196397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund OlesenSPURegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 197397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const { 198770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng return &SPU::R32CRegClass; 199770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng} 200770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng 201015f228861ef9b337366f92f637d4e8d624bb006Craig Topperconst uint16_t * 202564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott MichelSPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const 203564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel{ 204564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel // Cell ABI calling convention 205015f228861ef9b337366f92f637d4e8d624bb006Craig Topper static const uint16_t SPU_CalleeSaveRegs[] = { 206564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R80, SPU::R81, SPU::R82, SPU::R83, 207564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R84, SPU::R85, SPU::R86, SPU::R87, 208564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R88, SPU::R89, SPU::R90, SPU::R91, 209564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R92, SPU::R93, SPU::R94, SPU::R95, 210564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R96, SPU::R97, SPU::R98, SPU::R99, 211564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R100, SPU::R101, SPU::R102, SPU::R103, 212564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R104, SPU::R105, SPU::R106, SPU::R107, 213564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R108, SPU::R109, SPU::R110, SPU::R111, 214564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R112, SPU::R113, SPU::R114, SPU::R115, 215564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R116, SPU::R117, SPU::R118, SPU::R119, 216564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R120, SPU::R121, SPU::R122, SPU::R123, 217564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R124, SPU::R125, SPU::R126, SPU::R127, 218564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R2, /* environment pointer */ 219564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R1, /* stack pointer */ 220564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPU::R0, /* link register */ 221564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 0 /* end */ 222564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel }; 22302d711b93e3e0d2f0dae278360abe35305913e23Scott Michel 224564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel return SPU_CalleeSaveRegs; 225564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel} 226564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 227564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel/*! 228564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is 229564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel generally unused) are the Cell's reserved registers 230564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel */ 231564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott MichelBitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const { 232564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel BitVector Reserved(getNumRegs()); 2337f9ba9bb3c969eab32118dd21f15b4b74843c5c1Scott Michel Reserved.set(SPU::R0); // LR 2347f9ba9bb3c969eab32118dd21f15b4b74843c5c1Scott Michel Reserved.set(SPU::R1); // SP 2357f9ba9bb3c969eab32118dd21f15b4b74843c5c1Scott Michel Reserved.set(SPU::R2); // environment pointer 236564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel return Reserved; 237564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel} 238564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 239564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel//===----------------------------------------------------------------------===// 240564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel// Stack Frame Processing methods 241564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel//===----------------------------------------------------------------------===// 242564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 243564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel//-------------------------------------------------------------------------- 244564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michelvoid 245564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott MichelSPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF, 246564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel MachineBasicBlock &MBB, 247564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel MachineBasicBlock::iterator I) 248564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel const 249564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel{ 250564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 251564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel MBB.erase(I); 252564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel} 253564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 254fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbachvoid 255564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott MichelSPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 256dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630Jim Grosbach RegScavenger *RS) const 257564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel{ 258564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel unsigned i = 0; 259564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel MachineInstr &MI = *II; 260564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel MachineBasicBlock &MBB = *MI.getParent(); 261564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel MachineFunction &MF = *MBB.getParent(); 262564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel MachineFrameInfo *MFI = MF.getFrameInfo(); 263e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner DebugLoc dl = II->getDebugLoc(); 264564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 265d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman while (!MI.getOperand(i).isFI()) { 266564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel ++i; 267564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 268564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel } 269564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 270564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel MachineOperand &SPOp = MI.getOperand(i); 2718aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner int FrameIndex = SPOp.getIndex(); 272564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 273564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel // Now add the frame object offset to the offset from r1. 274564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel int Offset = MFI->getObjectOffset(FrameIndex); 275564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 27602d711b93e3e0d2f0dae278360abe35305913e23Scott Michel // Most instructions, except for generated FrameIndex additions using AIr32 27702d711b93e3e0d2f0dae278360abe35305913e23Scott Michel // and ILAr32, have the immediate in operand 1. AIr32 and ILAr32 have the 27802d711b93e3e0d2f0dae278360abe35305913e23Scott Michel // immediate in operand 2. 27902d711b93e3e0d2f0dae278360abe35305913e23Scott Michel unsigned OpNo = 1; 28002d711b93e3e0d2f0dae278360abe35305913e23Scott Michel if (MI.getOpcode() == SPU::AIr32 || MI.getOpcode() == SPU::ILAr32) 28102d711b93e3e0d2f0dae278360abe35305913e23Scott Michel OpNo = 2; 28202d711b93e3e0d2f0dae278360abe35305913e23Scott Michel 283564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel MachineOperand &MO = MI.getOperand(OpNo); 284564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 285564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel // Offset is biased by $lr's slot at the bottom. 28616c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov Offset += MO.getImm() + MFI->getStackSize() + SPUFrameLowering::minStackSize(); 287564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel assert((Offset & 0xf) == 0 2889a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner && "16-byte alignment violated in eliminateFrameIndex"); 289564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 290564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel // Replace the FrameIndex with base register with $sp (aka $r1) 291564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel SPOp.ChangeToRegister(SPU::R1, false); 292e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner 293e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner // if 'Offset' doesn't fit to the D-form instruction's 294e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner // immediate, convert the instruction to X-form 295e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner // if the instruction is not an AI (which takes a s10 immediate), assume 296e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner // it is a load/store that can take a s14 immediate 2977e09debcf17b2430ee95e547460ccc0fff4b0a87Benjamin Kramer if ((MI.getOpcode() == SPU::AIr32 && !isInt<10>(Offset)) 2987e09debcf17b2430ee95e547460ccc0fff4b0a87Benjamin Kramer || !isInt<14>(Offset)) { 299e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner int newOpcode = convertDFormToXForm(MI.getOpcode()); 300e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj); 301e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg ) 302e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner .addImm(Offset); 303e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner BuildMI(MBB, II, dl, TII.get(newOpcode), MI.getOperand(0).getReg()) 304e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner .addReg(tmpReg, RegState::Kill) 305e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner .addReg(SPU::R1); 306e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner // remove the replaced D-form instruction 307e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner MBB.erase(II); 308564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel } else { 309564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel MO.ChangeToImmediate(Offset); 310564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel } 311564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel} 312564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 313564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michelunsigned 314b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David GreeneSPURegisterInfo::getFrameRegister(const MachineFunction &MF) const 315564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel{ 316564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel return SPU::R1; 317564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel} 318564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michel 319564427eabdc4cb25e1bc9eb15c589e9451fc29a2Scott Michelint 320e27e02b1a48a715be93952a7cef49cdd19e9593bChris LattnerSPURegisterInfo::convertDFormToXForm(int dFormOpcode) const 321e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner{ 32233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov switch(dFormOpcode) 323e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner { 324e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner case SPU::AIr32: return SPU::Ar32; 325e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner case SPU::LQDr32: return SPU::LQXr32; 326e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner case SPU::LQDr128: return SPU::LQXr128; 327e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner case SPU::LQDv16i8: return SPU::LQXv16i8; 32899534bb81a0d945edd61d4db17549bde8449f94cKalle Raiskila case SPU::LQDv4i32: return SPU::LQXv4i32; 329e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner case SPU::LQDv4f32: return SPU::LQXv4f32; 330e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner case SPU::STQDr32: return SPU::STQXr32; 331e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner case SPU::STQDr128: return SPU::STQXr128; 332e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner case SPU::STQDv16i8: return SPU::STQXv16i8; 333e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner case SPU::STQDv4i32: return SPU::STQXv4i32; 334e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner case SPU::STQDv4f32: return SPU::STQXv4f32; 335e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner 336e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner default: assert( false && "Unhandled D to X-form conversion"); 337e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner } 338e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner // default will assert, but need to return something to keep the 339e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner // compiler happy. 340e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner return dFormOpcode; 341e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner} 342e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner 343e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner// TODO this is already copied from PPC. Could this convenience function 344e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner// be moved to the RegScavenger class? 34533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikovunsigned 34633464912237efaa0ed7060829e66b59055bdd48bAnton KorobeynikovSPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II, 347e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner RegScavenger *RS, 34833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov const TargetRegisterClass *RC, 349e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner int SPAdj) const 350e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner{ 351e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner assert(RS && "Register scavenging must be on"); 352e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner unsigned Reg = RS->FindUnusedReg(RC); 353e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner if (Reg == 0) 354e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner Reg = RS->scavengeRegister(RC, II, SPAdj); 355e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner assert( Reg && "Register scavenger failed"); 356e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner return Reg; 357e27e02b1a48a715be93952a7cef49cdd19e9593bChris Lattner} 358