SPURegisterInfo.cpp revision ca1267c02b025cc719190b05f9e1a5d174a9caf7 
1//===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Cell implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "reginfo"
15#include "SPU.h"
16#include "SPURegisterInfo.h"
17#include "SPURegisterNames.h"
18#include "SPUInstrBuilder.h"
19#include "SPUSubtarget.h"
20#include "SPUMachineFunction.h"
21#include "SPUFrameInfo.h"
22#include "llvm/Constants.h"
23#include "llvm/Type.h"
24#include "llvm/CodeGen/ValueTypes.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineModuleInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/SelectionDAGNodes.h"
32#include "llvm/CodeGen/ValueTypes.h"
33#include "llvm/Target/TargetFrameInfo.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/MathExtras.h"
40#include "llvm/ADT/BitVector.h"
41#include "llvm/ADT/STLExtras.h"
42#include <cstdlib>
43#include <iostream>
44
45using namespace llvm;
46
47/// getRegisterNumbering - Given the enum value for some register, e.g.
48/// PPC::F14, return the number that it corresponds to (e.g. 14).
49unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
50  using namespace SPU;
51  switch (RegEnum) {
52  case SPU::R0: return 0;
53  case SPU::R1: return 1;
54  case SPU::R2: return 2;
55  case SPU::R3: return 3;
56  case SPU::R4: return 4;
57  case SPU::R5: return 5;
58  case SPU::R6: return 6;
59  case SPU::R7: return 7;
60  case SPU::R8: return 8;
61  case SPU::R9: return 9;
62  case SPU::R10: return 10;
63  case SPU::R11: return 11;
64  case SPU::R12: return 12;
65  case SPU::R13: return 13;
66  case SPU::R14: return 14;
67  case SPU::R15: return 15;
68  case SPU::R16: return 16;
69  case SPU::R17: return 17;
70  case SPU::R18: return 18;
71  case SPU::R19: return 19;
72  case SPU::R20: return 20;
73  case SPU::R21: return 21;
74  case SPU::R22: return 22;
75  case SPU::R23: return 23;
76  case SPU::R24: return 24;
77  case SPU::R25: return 25;
78  case SPU::R26: return 26;
79  case SPU::R27: return 27;
80  case SPU::R28: return 28;
81  case SPU::R29: return 29;
82  case SPU::R30: return 30;
83  case SPU::R31: return 31;
84  case SPU::R32: return 32;
85  case SPU::R33: return 33;
86  case SPU::R34: return 34;
87  case SPU::R35: return 35;
88  case SPU::R36: return 36;
89  case SPU::R37: return 37;
90  case SPU::R38: return 38;
91  case SPU::R39: return 39;
92  case SPU::R40: return 40;
93  case SPU::R41: return 41;
94  case SPU::R42: return 42;
95  case SPU::R43: return 43;
96  case SPU::R44: return 44;
97  case SPU::R45: return 45;
98  case SPU::R46: return 46;
99  case SPU::R47: return 47;
100  case SPU::R48: return 48;
101  case SPU::R49: return 49;
102  case SPU::R50: return 50;
103  case SPU::R51: return 51;
104  case SPU::R52: return 52;
105  case SPU::R53: return 53;
106  case SPU::R54: return 54;
107  case SPU::R55: return 55;
108  case SPU::R56: return 56;
109  case SPU::R57: return 57;
110  case SPU::R58: return 58;
111  case SPU::R59: return 59;
112  case SPU::R60: return 60;
113  case SPU::R61: return 61;
114  case SPU::R62: return 62;
115  case SPU::R63: return 63;
116  case SPU::R64: return 64;
117  case SPU::R65: return 65;
118  case SPU::R66: return 66;
119  case SPU::R67: return 67;
120  case SPU::R68: return 68;
121  case SPU::R69: return 69;
122  case SPU::R70: return 70;
123  case SPU::R71: return 71;
124  case SPU::R72: return 72;
125  case SPU::R73: return 73;
126  case SPU::R74: return 74;
127  case SPU::R75: return 75;
128  case SPU::R76: return 76;
129  case SPU::R77: return 77;
130  case SPU::R78: return 78;
131  case SPU::R79: return 79;
132  case SPU::R80: return 80;
133  case SPU::R81: return 81;
134  case SPU::R82: return 82;
135  case SPU::R83: return 83;
136  case SPU::R84: return 84;
137  case SPU::R85: return 85;
138  case SPU::R86: return 86;
139  case SPU::R87: return 87;
140  case SPU::R88: return 88;
141  case SPU::R89: return 89;
142  case SPU::R90: return 90;
143  case SPU::R91: return 91;
144  case SPU::R92: return 92;
145  case SPU::R93: return 93;
146  case SPU::R94: return 94;
147  case SPU::R95: return 95;
148  case SPU::R96: return 96;
149  case SPU::R97: return 97;
150  case SPU::R98: return 98;
151  case SPU::R99: return 99;
152  case SPU::R100: return 100;
153  case SPU::R101: return 101;
154  case SPU::R102: return 102;
155  case SPU::R103: return 103;
156  case SPU::R104: return 104;
157  case SPU::R105: return 105;
158  case SPU::R106: return 106;
159  case SPU::R107: return 107;
160  case SPU::R108: return 108;
161  case SPU::R109: return 109;
162  case SPU::R110: return 110;
163  case SPU::R111: return 111;
164  case SPU::R112: return 112;
165  case SPU::R113: return 113;
166  case SPU::R114: return 114;
167  case SPU::R115: return 115;
168  case SPU::R116: return 116;
169  case SPU::R117: return 117;
170  case SPU::R118: return 118;
171  case SPU::R119: return 119;
172  case SPU::R120: return 120;
173  case SPU::R121: return 121;
174  case SPU::R122: return 122;
175  case SPU::R123: return 123;
176  case SPU::R124: return 124;
177  case SPU::R125: return 125;
178  case SPU::R126: return 126;
179  case SPU::R127: return 127;
180  default:
181    std::cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n";
182    abort();
183  }
184}
185
186SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
187                                 const TargetInstrInfo &tii) :
188  SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
189  Subtarget(subtarget),
190  TII(tii)
191{
192}
193
194// SPU's 128-bit registers used for argument passing:
195static const unsigned SPU_ArgRegs[] = {
196  SPU::R3,  SPU::R4,  SPU::R5,  SPU::R6,  SPU::R7,  SPU::R8,  SPU::R9,
197  SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
198  SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
199  SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
200  SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
201  SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
202  SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
203  SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
204  SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
205  SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
206  SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
207};
208
209const unsigned *
210SPURegisterInfo::getArgRegs()
211{
212  return SPU_ArgRegs;
213}
214
215unsigned
216SPURegisterInfo::getNumArgRegs()
217{
218  return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
219}
220
221const unsigned *
222SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
223{
224  // Cell ABI calling convention
225  static const unsigned SPU_CalleeSaveRegs[] = {
226    SPU::R80, SPU::R81, SPU::R82, SPU::R83,
227    SPU::R84, SPU::R85, SPU::R86, SPU::R87,
228    SPU::R88, SPU::R89, SPU::R90, SPU::R91,
229    SPU::R92, SPU::R93, SPU::R94, SPU::R95,
230    SPU::R96, SPU::R97, SPU::R98, SPU::R99,
231    SPU::R100, SPU::R101, SPU::R102, SPU::R103,
232    SPU::R104, SPU::R105, SPU::R106, SPU::R107,
233    SPU::R108, SPU::R109, SPU::R110, SPU::R111,
234    SPU::R112, SPU::R113, SPU::R114, SPU::R115,
235    SPU::R116, SPU::R117, SPU::R118, SPU::R119,
236    SPU::R120, SPU::R121, SPU::R122, SPU::R123,
237    SPU::R124, SPU::R125, SPU::R126, SPU::R127,
238    SPU::R2,    /* environment pointer */
239    SPU::R1,    /* stack pointer */
240    SPU::R0,    /* link register */
241    0 /* end */
242  };
243
244  return SPU_CalleeSaveRegs;
245}
246
247const TargetRegisterClass* const*
248SPURegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
249{
250  // Cell ABI Calling Convention
251  static const TargetRegisterClass * const SPU_CalleeSaveRegClasses[] = {
252    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
253    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
254    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
255    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
256    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
257    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
258    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
259    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
260    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
261    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
262    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
263    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
264    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
265    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
266    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
267    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
268    &SPU::GPRCRegClass, /* environment pointer */
269    &SPU::GPRCRegClass, /* stack pointer */
270    &SPU::GPRCRegClass, /* link register */
271    0 /* end */
272  };
273
274  return SPU_CalleeSaveRegClasses;
275}
276
277/*!
278 R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
279 generally unused) are the Cell's reserved registers
280 */
281BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
282  BitVector Reserved(getNumRegs());
283  Reserved.set(SPU::R0);                // LR
284  Reserved.set(SPU::R1);                // SP
285  Reserved.set(SPU::R2);                // environment pointer
286  return Reserved;
287}
288
289//===----------------------------------------------------------------------===//
290// Stack Frame Processing methods
291//===----------------------------------------------------------------------===//
292
293// needsFP - Return true if the specified function should have a dedicated frame
294// pointer register.  This is true if the function has variable sized allocas or
295// if frame pointer elimination is disabled.
296//
297static bool needsFP(const MachineFunction &MF) {
298  const MachineFrameInfo *MFI = MF.getFrameInfo();
299  return NoFramePointerElim || MFI->hasVarSizedObjects();
300}
301
302//--------------------------------------------------------------------------
303// hasFP - Return true if the specified function actually has a dedicated frame
304// pointer register.  This is true if the function needs a frame pointer and has
305// a non-zero stack size.
306bool
307SPURegisterInfo::hasFP(const MachineFunction &MF) const {
308  const MachineFrameInfo *MFI = MF.getFrameInfo();
309  return MFI->getStackSize() && needsFP(MF);
310}
311
312//--------------------------------------------------------------------------
313void
314SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
315                                               MachineBasicBlock &MBB,
316                                               MachineBasicBlock::iterator I)
317  const
318{
319  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
320  MBB.erase(I);
321}
322
323void
324SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
325                                     RegScavenger *RS) const
326{
327  unsigned i = 0;
328  MachineInstr &MI = *II;
329  MachineBasicBlock &MBB = *MI.getParent();
330  MachineFunction &MF = *MBB.getParent();
331  MachineFrameInfo *MFI = MF.getFrameInfo();
332
333  while (!MI.getOperand(i).isFrameIndex()) {
334    ++i;
335    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
336  }
337
338  MachineOperand &SPOp = MI.getOperand(i);
339  int FrameIndex = SPOp.getIndex();
340
341  // Now add the frame object offset to the offset from r1.
342  int Offset = MFI->getObjectOffset(FrameIndex);
343
344  // Most instructions, except for generated FrameIndex additions using AIr32,
345  // have the immediate in operand 1. AIr32, in this case, has the immediate
346  // in operand 2.
347  unsigned OpNo = (MI.getOpcode() != SPU::AIr32 ? 1 : 2);
348  MachineOperand &MO = MI.getOperand(OpNo);
349
350  // Offset is biased by $lr's slot at the bottom.
351  Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
352  assert((Offset & 0xf) == 0
353         && "16-byte alignment violated in eliminateFrameIndex");
354
355  // Replace the FrameIndex with base register with $sp (aka $r1)
356  SPOp.ChangeToRegister(SPU::R1, false);
357  if (Offset > SPUFrameInfo::maxFrameOffset()
358      || Offset < SPUFrameInfo::minFrameOffset()) {
359    cerr << "Large stack adjustment ("
360         << Offset
361         << ") in SPURegisterInfo::eliminateFrameIndex.";
362  } else {
363    MO.ChangeToImmediate(Offset);
364  }
365}
366
367/// determineFrameLayout - Determine the size of the frame and maximum call
368/// frame size.
369void
370SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const
371{
372  MachineFrameInfo *MFI = MF.getFrameInfo();
373
374  // Get the number of bytes to allocate from the FrameInfo
375  unsigned FrameSize = MFI->getStackSize();
376
377  // Get the alignments provided by the target, and the maximum alignment
378  // (if any) of the fixed frame objects.
379  unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
380  unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment());
381  assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
382  unsigned AlignMask = Align - 1;
383
384  // Get the maximum call frame size of all the calls.
385  unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
386
387  // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
388  // that allocations will be aligned.
389  if (MFI->hasVarSizedObjects())
390    maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
391
392  // Update maximum call frame size.
393  MFI->setMaxCallFrameSize(maxCallFrameSize);
394
395  // Include call frame size in total.
396  FrameSize += maxCallFrameSize;
397
398  // Make sure the frame is aligned.
399  FrameSize = (FrameSize + AlignMask) & ~AlignMask;
400
401  // Update frame info.
402  MFI->setStackSize(FrameSize);
403}
404
405void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
406                                                           RegScavenger *RS)
407  const {
408#if 0
409  //  Save and clear the LR state.
410  SPUFunctionInfo *FI = MF.getInfo<SPUFunctionInfo>();
411  FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
412#endif
413  // Mark LR and SP unused, since the prolog spills them to stack and
414  // we don't want anyone else to spill them for us.
415  //
416  // Also, unless R2 is really used someday, don't spill it automatically.
417  MF.getRegInfo().setPhysRegUnused(SPU::R0);
418  MF.getRegInfo().setPhysRegUnused(SPU::R1);
419  MF.getRegInfo().setPhysRegUnused(SPU::R2);
420}
421
422void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
423{
424  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
425  MachineBasicBlock::iterator MBBI = MBB.begin();
426  MachineFrameInfo *MFI = MF.getFrameInfo();
427  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
428
429  // Prepare for debug frame info.
430  bool hasDebugInfo = MMI && MMI->hasDebugInfo();
431  unsigned FrameLabelId = 0;
432
433  // Move MBBI back to the beginning of the function.
434  MBBI = MBB.begin();
435
436  // Work out frame sizes.
437  determineFrameLayout(MF);
438  int FrameSize = MFI->getStackSize();
439
440  assert((FrameSize & 0xf) == 0
441         && "SPURegisterInfo::emitPrologue: FrameSize not aligned");
442
443  if (FrameSize > 0) {
444    FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
445    if (hasDebugInfo) {
446      // Mark effective beginning of when frame pointer becomes valid.
447      FrameLabelId = MMI->NextLabelID();
448      BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(FrameLabelId).addImm(0);
449    }
450
451    // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
452    // for the ABI
453    BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
454      .addReg(SPU::R1);
455    if (isS10Constant(FrameSize)) {
456      // Spill $sp to adjusted $sp
457      BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
458        .addReg(SPU::R1);
459      // Adjust $sp by required amout
460      BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
461        .addImm(FrameSize);
462    } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
463      // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
464      // $r2 to adjust $sp:
465      BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
466        .addImm(-16)
467        .addReg(SPU::R1);
468      BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
469        .addImm(FrameSize);
470      BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1)
471        .addReg(SPU::R2)
472        .addReg(SPU::R1);
473      BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
474        .addReg(SPU::R1)
475        .addReg(SPU::R2);
476      BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2)
477        .addReg(SPU::R2)
478        .addImm(16);
479      BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
480        .addReg(SPU::R2)
481        .addReg(SPU::R1);
482    } else {
483      cerr << "Unhandled frame size: " << FrameSize << "\n";
484      abort();
485    }
486
487    if (hasDebugInfo) {
488      std::vector<MachineMove> &Moves = MMI->getFrameMoves();
489
490      // Show update of SP.
491      MachineLocation SPDst(MachineLocation::VirtualFP);
492      MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize);
493      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
494
495      // Add callee saved registers to move list.
496      const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
497      for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
498        int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
499        unsigned Reg = CSI[I].getReg();
500        if (Reg == SPU::R0) continue;
501        MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
502        MachineLocation CSSrc(Reg);
503        Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
504      }
505
506      // Mark effective beginning of when frame pointer is ready.
507      unsigned ReadyLabelId = MMI->NextLabelID();
508      BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(ReadyLabelId).addImm(0);
509
510      MachineLocation FPDst(SPU::R1);
511      MachineLocation FPSrc(MachineLocation::VirtualFP);
512      Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
513    }
514  } else {
515    // This is a leaf function -- insert a branch hint iff there are
516    // sufficient number instructions in the basic block. Note that
517    // this is just a best guess based on the basic block's size.
518    if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) {
519      MachineBasicBlock::iterator MBBI = prior(MBB.end());
520      // Insert terminator label
521      unsigned BranchLabelId = MMI->NextLabelID();
522      BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId).addImm(0);
523    }
524  }
525}
526
527void
528SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
529{
530  MachineBasicBlock::iterator MBBI = prior(MBB.end());
531  const MachineFrameInfo *MFI = MF.getFrameInfo();
532  int FrameSize = MFI->getStackSize();
533  int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
534
535  assert(MBBI->getOpcode() == SPU::RET &&
536         "Can only insert epilog into returning blocks");
537  assert((FrameSize & 0xf) == 0
538         && "SPURegisterInfo::emitEpilogue: FrameSize not aligned");
539  if (FrameSize > 0) {
540    FrameSize = FrameSize + SPUFrameInfo::minStackSize();
541    if (isS10Constant(FrameSize + LinkSlotOffset)) {
542      // Reload $lr, adjust $sp by required amount
543      // Note: We do this to slightly improve dual issue -- not by much, but it
544      // is an opportunity for dual issue.
545      BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
546        .addImm(FrameSize + LinkSlotOffset)
547        .addReg(SPU::R1);
548      BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1)
549        .addReg(SPU::R1)
550        .addImm(FrameSize);
551    } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
552      // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
553      // $r2 to adjust $sp:
554      BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
555        .addImm(16)
556        .addReg(SPU::R1);
557      BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
558        .addImm(FrameSize);
559      BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
560        .addReg(SPU::R1)
561        .addReg(SPU::R2);
562      BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
563        .addImm(16)
564        .addReg(SPU::R2);
565      BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2).
566        addReg(SPU::R2)
567        .addImm(16);
568      BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
569        .addReg(SPU::R2)
570        .addReg(SPU::R1);
571    } else {
572      cerr << "Unhandled frame size: " << FrameSize << "\n";
573      abort();
574    }
575   }
576}
577
578unsigned
579SPURegisterInfo::getRARegister() const
580{
581  return SPU::R0;
582}
583
584unsigned
585SPURegisterInfo::getFrameRegister(MachineFunction &MF) const
586{
587  return SPU::R1;
588}
589
590void
591SPURegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const
592{
593  // Initial state of the frame pointer is R1.
594  MachineLocation Dst(MachineLocation::VirtualFP);
595  MachineLocation Src(SPU::R1, 0);
596  Moves.push_back(MachineMove(0, Dst, Src));
597}
598
599
600int
601SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
602  // FIXME: Most probably dwarf numbers differs for Linux and Darwin
603  return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
604}
605
606#include "SPUGenRegisterInfo.inc"
607