SPURegisterInfo.cpp revision eecfa369eb91838fbd833183717b2579a0127acb 
1//===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Cell implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "reginfo"
15#include "SPU.h"
16#include "SPURegisterInfo.h"
17#include "SPURegisterNames.h"
18#include "SPUInstrBuilder.h"
19#include "SPUSubtarget.h"
20#include "SPUMachineFunction.h"
21#include "SPUFrameInfo.h"
22#include "llvm/Constants.h"
23#include "llvm/Type.h"
24#include "llvm/CodeGen/ValueTypes.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineModuleInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/SelectionDAGNodes.h"
32#include "llvm/CodeGen/ValueTypes.h"
33#include "llvm/Target/TargetFrameInfo.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/MathExtras.h"
40#include "llvm/ADT/BitVector.h"
41#include "llvm/ADT/STLExtras.h"
42#include <cstdlib>
43
44using namespace llvm;
45
46/// getRegisterNumbering - Given the enum value for some register, e.g.
47/// PPC::F14, return the number that it corresponds to (e.g. 14).
48unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
49  using namespace SPU;
50  switch (RegEnum) {
51  case SPU::R0: return 0;
52  case SPU::R1: return 1;
53  case SPU::R2: return 2;
54  case SPU::R3: return 3;
55  case SPU::R4: return 4;
56  case SPU::R5: return 5;
57  case SPU::R6: return 6;
58  case SPU::R7: return 7;
59  case SPU::R8: return 8;
60  case SPU::R9: return 9;
61  case SPU::R10: return 10;
62  case SPU::R11: return 11;
63  case SPU::R12: return 12;
64  case SPU::R13: return 13;
65  case SPU::R14: return 14;
66  case SPU::R15: return 15;
67  case SPU::R16: return 16;
68  case SPU::R17: return 17;
69  case SPU::R18: return 18;
70  case SPU::R19: return 19;
71  case SPU::R20: return 20;
72  case SPU::R21: return 21;
73  case SPU::R22: return 22;
74  case SPU::R23: return 23;
75  case SPU::R24: return 24;
76  case SPU::R25: return 25;
77  case SPU::R26: return 26;
78  case SPU::R27: return 27;
79  case SPU::R28: return 28;
80  case SPU::R29: return 29;
81  case SPU::R30: return 30;
82  case SPU::R31: return 31;
83  case SPU::R32: return 32;
84  case SPU::R33: return 33;
85  case SPU::R34: return 34;
86  case SPU::R35: return 35;
87  case SPU::R36: return 36;
88  case SPU::R37: return 37;
89  case SPU::R38: return 38;
90  case SPU::R39: return 39;
91  case SPU::R40: return 40;
92  case SPU::R41: return 41;
93  case SPU::R42: return 42;
94  case SPU::R43: return 43;
95  case SPU::R44: return 44;
96  case SPU::R45: return 45;
97  case SPU::R46: return 46;
98  case SPU::R47: return 47;
99  case SPU::R48: return 48;
100  case SPU::R49: return 49;
101  case SPU::R50: return 50;
102  case SPU::R51: return 51;
103  case SPU::R52: return 52;
104  case SPU::R53: return 53;
105  case SPU::R54: return 54;
106  case SPU::R55: return 55;
107  case SPU::R56: return 56;
108  case SPU::R57: return 57;
109  case SPU::R58: return 58;
110  case SPU::R59: return 59;
111  case SPU::R60: return 60;
112  case SPU::R61: return 61;
113  case SPU::R62: return 62;
114  case SPU::R63: return 63;
115  case SPU::R64: return 64;
116  case SPU::R65: return 65;
117  case SPU::R66: return 66;
118  case SPU::R67: return 67;
119  case SPU::R68: return 68;
120  case SPU::R69: return 69;
121  case SPU::R70: return 70;
122  case SPU::R71: return 71;
123  case SPU::R72: return 72;
124  case SPU::R73: return 73;
125  case SPU::R74: return 74;
126  case SPU::R75: return 75;
127  case SPU::R76: return 76;
128  case SPU::R77: return 77;
129  case SPU::R78: return 78;
130  case SPU::R79: return 79;
131  case SPU::R80: return 80;
132  case SPU::R81: return 81;
133  case SPU::R82: return 82;
134  case SPU::R83: return 83;
135  case SPU::R84: return 84;
136  case SPU::R85: return 85;
137  case SPU::R86: return 86;
138  case SPU::R87: return 87;
139  case SPU::R88: return 88;
140  case SPU::R89: return 89;
141  case SPU::R90: return 90;
142  case SPU::R91: return 91;
143  case SPU::R92: return 92;
144  case SPU::R93: return 93;
145  case SPU::R94: return 94;
146  case SPU::R95: return 95;
147  case SPU::R96: return 96;
148  case SPU::R97: return 97;
149  case SPU::R98: return 98;
150  case SPU::R99: return 99;
151  case SPU::R100: return 100;
152  case SPU::R101: return 101;
153  case SPU::R102: return 102;
154  case SPU::R103: return 103;
155  case SPU::R104: return 104;
156  case SPU::R105: return 105;
157  case SPU::R106: return 106;
158  case SPU::R107: return 107;
159  case SPU::R108: return 108;
160  case SPU::R109: return 109;
161  case SPU::R110: return 110;
162  case SPU::R111: return 111;
163  case SPU::R112: return 112;
164  case SPU::R113: return 113;
165  case SPU::R114: return 114;
166  case SPU::R115: return 115;
167  case SPU::R116: return 116;
168  case SPU::R117: return 117;
169  case SPU::R118: return 118;
170  case SPU::R119: return 119;
171  case SPU::R120: return 120;
172  case SPU::R121: return 121;
173  case SPU::R122: return 122;
174  case SPU::R123: return 123;
175  case SPU::R124: return 124;
176  case SPU::R125: return 125;
177  case SPU::R126: return 126;
178  case SPU::R127: return 127;
179  default:
180    cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n";
181    abort();
182  }
183}
184
185SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
186                                 const TargetInstrInfo &tii) :
187  SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
188  Subtarget(subtarget),
189  TII(tii)
190{
191}
192
193// SPU's 128-bit registers used for argument passing:
194static const unsigned SPU_ArgRegs[] = {
195  SPU::R3,  SPU::R4,  SPU::R5,  SPU::R6,  SPU::R7,  SPU::R8,  SPU::R9,
196  SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
197  SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
198  SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
199  SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
200  SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
201  SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
202  SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
203  SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
204  SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
205  SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
206};
207
208const unsigned *
209SPURegisterInfo::getArgRegs()
210{
211  return SPU_ArgRegs;
212}
213
214unsigned
215SPURegisterInfo::getNumArgRegs()
216{
217  return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
218}
219
220const unsigned *
221SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
222{
223  // Cell ABI calling convention
224  static const unsigned SPU_CalleeSaveRegs[] = {
225    SPU::R80, SPU::R81, SPU::R82, SPU::R83,
226    SPU::R84, SPU::R85, SPU::R86, SPU::R87,
227    SPU::R88, SPU::R89, SPU::R90, SPU::R91,
228    SPU::R92, SPU::R93, SPU::R94, SPU::R95,
229    SPU::R96, SPU::R97, SPU::R98, SPU::R99,
230    SPU::R100, SPU::R101, SPU::R102, SPU::R103,
231    SPU::R104, SPU::R105, SPU::R106, SPU::R107,
232    SPU::R108, SPU::R109, SPU::R110, SPU::R111,
233    SPU::R112, SPU::R113, SPU::R114, SPU::R115,
234    SPU::R116, SPU::R117, SPU::R118, SPU::R119,
235    SPU::R120, SPU::R121, SPU::R122, SPU::R123,
236    SPU::R124, SPU::R125, SPU::R126, SPU::R127,
237    SPU::R2,    /* environment pointer */
238    SPU::R1,    /* stack pointer */
239    SPU::R0,    /* link register */
240    0 /* end */
241  };
242
243  return SPU_CalleeSaveRegs;
244}
245
246const TargetRegisterClass* const*
247SPURegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
248{
249  // Cell ABI Calling Convention
250  static const TargetRegisterClass * const SPU_CalleeSaveRegClasses[] = {
251    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
252    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
253    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
254    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
255    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
256    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
257    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
258    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
259    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
260    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
261    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
262    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
263    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
264    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
265    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
266    &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
267    &SPU::GPRCRegClass, /* environment pointer */
268    &SPU::GPRCRegClass, /* stack pointer */
269    &SPU::GPRCRegClass, /* link register */
270    0 /* end */
271  };
272
273  return SPU_CalleeSaveRegClasses;
274}
275
276/*!
277 R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
278 generally unused) are the Cell's reserved registers
279 */
280BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
281  BitVector Reserved(getNumRegs());
282  Reserved.set(SPU::R0);                // LR
283  Reserved.set(SPU::R1);                // SP
284  Reserved.set(SPU::R2);                // environment pointer
285  return Reserved;
286}
287
288//===----------------------------------------------------------------------===//
289// Stack Frame Processing methods
290//===----------------------------------------------------------------------===//
291
292// needsFP - Return true if the specified function should have a dedicated frame
293// pointer register.  This is true if the function has variable sized allocas or
294// if frame pointer elimination is disabled.
295//
296static bool needsFP(const MachineFunction &MF) {
297  const MachineFrameInfo *MFI = MF.getFrameInfo();
298  return NoFramePointerElim || MFI->hasVarSizedObjects();
299}
300
301//--------------------------------------------------------------------------
302// hasFP - Return true if the specified function actually has a dedicated frame
303// pointer register.  This is true if the function needs a frame pointer and has
304// a non-zero stack size.
305bool
306SPURegisterInfo::hasFP(const MachineFunction &MF) const {
307  const MachineFrameInfo *MFI = MF.getFrameInfo();
308  return MFI->getStackSize() && needsFP(MF);
309}
310
311//--------------------------------------------------------------------------
312void
313SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
314                                               MachineBasicBlock &MBB,
315                                               MachineBasicBlock::iterator I)
316  const
317{
318  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
319  MBB.erase(I);
320}
321
322void
323SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
324                                     RegScavenger *RS) const
325{
326  unsigned i = 0;
327  MachineInstr &MI = *II;
328  MachineBasicBlock &MBB = *MI.getParent();
329  MachineFunction &MF = *MBB.getParent();
330  MachineFrameInfo *MFI = MF.getFrameInfo();
331
332  while (!MI.getOperand(i).isFrameIndex()) {
333    ++i;
334    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
335  }
336
337  MachineOperand &SPOp = MI.getOperand(i);
338  int FrameIndex = SPOp.getIndex();
339
340  // Now add the frame object offset to the offset from r1.
341  int Offset = MFI->getObjectOffset(FrameIndex);
342
343  // Most instructions, except for generated FrameIndex additions using AIr32,
344  // have the immediate in operand 1. AIr32, in this case, has the immediate
345  // in operand 2.
346  unsigned OpNo = (MI.getOpcode() != SPU::AIr32 ? 1 : 2);
347  MachineOperand &MO = MI.getOperand(OpNo);
348
349  // Offset is biased by $lr's slot at the bottom.
350  Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
351  assert((Offset & 0xf) == 0
352         && "16-byte alignment violated in eliminateFrameIndex");
353
354  // Replace the FrameIndex with base register with $sp (aka $r1)
355  SPOp.ChangeToRegister(SPU::R1, false);
356  if (Offset > SPUFrameInfo::maxFrameOffset()
357      || Offset < SPUFrameInfo::minFrameOffset()) {
358    cerr << "Large stack adjustment ("
359         << Offset
360         << ") in SPURegisterInfo::eliminateFrameIndex.";
361  } else {
362    MO.ChangeToImmediate(Offset);
363  }
364}
365
366/// determineFrameLayout - Determine the size of the frame and maximum call
367/// frame size.
368void
369SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const
370{
371  MachineFrameInfo *MFI = MF.getFrameInfo();
372
373  // Get the number of bytes to allocate from the FrameInfo
374  unsigned FrameSize = MFI->getStackSize();
375
376  // Get the alignments provided by the target, and the maximum alignment
377  // (if any) of the fixed frame objects.
378  unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
379  unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment());
380  assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
381  unsigned AlignMask = Align - 1;
382
383  // Get the maximum call frame size of all the calls.
384  unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
385
386  // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
387  // that allocations will be aligned.
388  if (MFI->hasVarSizedObjects())
389    maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
390
391  // Update maximum call frame size.
392  MFI->setMaxCallFrameSize(maxCallFrameSize);
393
394  // Include call frame size in total.
395  FrameSize += maxCallFrameSize;
396
397  // Make sure the frame is aligned.
398  FrameSize = (FrameSize + AlignMask) & ~AlignMask;
399
400  // Update frame info.
401  MFI->setStackSize(FrameSize);
402}
403
404void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
405                                                           RegScavenger *RS)
406  const {
407#if 0
408  //  Save and clear the LR state.
409  SPUFunctionInfo *FI = MF.getInfo<SPUFunctionInfo>();
410  FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
411#endif
412  // Mark LR and SP unused, since the prolog spills them to stack and
413  // we don't want anyone else to spill them for us.
414  //
415  // Also, unless R2 is really used someday, don't spill it automatically.
416  MF.getRegInfo().setPhysRegUnused(SPU::R0);
417  MF.getRegInfo().setPhysRegUnused(SPU::R1);
418  MF.getRegInfo().setPhysRegUnused(SPU::R2);
419}
420
421void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
422{
423  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
424  MachineBasicBlock::iterator MBBI = MBB.begin();
425  MachineFrameInfo *MFI = MF.getFrameInfo();
426  MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
427
428  // Prepare for debug frame info.
429  bool hasDebugInfo = MMI && MMI->hasDebugInfo();
430  unsigned FrameLabelId = 0;
431
432  // Move MBBI back to the beginning of the function.
433  MBBI = MBB.begin();
434
435  // Work out frame sizes.
436  determineFrameLayout(MF);
437  int FrameSize = MFI->getStackSize();
438
439  assert((FrameSize & 0xf) == 0
440         && "SPURegisterInfo::emitPrologue: FrameSize not aligned");
441
442  if (FrameSize > 0) {
443    FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
444    if (hasDebugInfo) {
445      // Mark effective beginning of when frame pointer becomes valid.
446      FrameLabelId = MMI->NextLabelID();
447      BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(FrameLabelId).addImm(0);
448    }
449
450    // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
451    // for the ABI
452    BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
453      .addReg(SPU::R1);
454    if (isS10Constant(FrameSize)) {
455      // Spill $sp to adjusted $sp
456      BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
457        .addReg(SPU::R1);
458      // Adjust $sp by required amout
459      BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
460        .addImm(FrameSize);
461    } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
462      // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
463      // $r2 to adjust $sp:
464      BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
465        .addImm(-16)
466        .addReg(SPU::R1);
467      BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
468        .addImm(FrameSize);
469      BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1)
470        .addReg(SPU::R2)
471        .addReg(SPU::R1);
472      BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
473        .addReg(SPU::R1)
474        .addReg(SPU::R2);
475      BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2)
476        .addReg(SPU::R2)
477        .addImm(16);
478      BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
479        .addReg(SPU::R2)
480        .addReg(SPU::R1);
481    } else {
482      cerr << "Unhandled frame size: " << FrameSize << "\n";
483      abort();
484    }
485
486    if (hasDebugInfo) {
487      std::vector<MachineMove> &Moves = MMI->getFrameMoves();
488
489      // Show update of SP.
490      MachineLocation SPDst(MachineLocation::VirtualFP);
491      MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize);
492      Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
493
494      // Add callee saved registers to move list.
495      const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
496      for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
497        int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
498        unsigned Reg = CSI[I].getReg();
499        if (Reg == SPU::R0) continue;
500        MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
501        MachineLocation CSSrc(Reg);
502        Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
503      }
504
505      // Mark effective beginning of when frame pointer is ready.
506      unsigned ReadyLabelId = MMI->NextLabelID();
507      BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(ReadyLabelId).addImm(0);
508
509      MachineLocation FPDst(SPU::R1);
510      MachineLocation FPSrc(MachineLocation::VirtualFP);
511      Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
512    }
513  } else {
514    // This is a leaf function -- insert a branch hint iff there are
515    // sufficient number instructions in the basic block. Note that
516    // this is just a best guess based on the basic block's size.
517    if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) {
518      MachineBasicBlock::iterator MBBI = prior(MBB.end());
519      // Insert terminator label
520      unsigned BranchLabelId = MMI->NextLabelID();
521      BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId).addImm(0);
522    }
523  }
524}
525
526void
527SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
528{
529  MachineBasicBlock::iterator MBBI = prior(MBB.end());
530  const MachineFrameInfo *MFI = MF.getFrameInfo();
531  int FrameSize = MFI->getStackSize();
532  int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
533
534  assert(MBBI->getOpcode() == SPU::RET &&
535         "Can only insert epilog into returning blocks");
536  assert((FrameSize & 0xf) == 0
537         && "SPURegisterInfo::emitEpilogue: FrameSize not aligned");
538  if (FrameSize > 0) {
539    FrameSize = FrameSize + SPUFrameInfo::minStackSize();
540    if (isS10Constant(FrameSize + LinkSlotOffset)) {
541      // Reload $lr, adjust $sp by required amount
542      // Note: We do this to slightly improve dual issue -- not by much, but it
543      // is an opportunity for dual issue.
544      BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
545        .addImm(FrameSize + LinkSlotOffset)
546        .addReg(SPU::R1);
547      BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1)
548        .addReg(SPU::R1)
549        .addImm(FrameSize);
550    } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
551      // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
552      // $r2 to adjust $sp:
553      BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
554        .addImm(16)
555        .addReg(SPU::R1);
556      BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
557        .addImm(FrameSize);
558      BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
559        .addReg(SPU::R1)
560        .addReg(SPU::R2);
561      BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
562        .addImm(16)
563        .addReg(SPU::R2);
564      BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2).
565        addReg(SPU::R2)
566        .addImm(16);
567      BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
568        .addReg(SPU::R2)
569        .addReg(SPU::R1);
570    } else {
571      cerr << "Unhandled frame size: " << FrameSize << "\n";
572      abort();
573    }
574   }
575}
576
577unsigned
578SPURegisterInfo::getRARegister() const
579{
580  return SPU::R0;
581}
582
583unsigned
584SPURegisterInfo::getFrameRegister(MachineFunction &MF) const
585{
586  return SPU::R1;
587}
588
589void
590SPURegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const
591{
592  // Initial state of the frame pointer is R1.
593  MachineLocation Dst(MachineLocation::VirtualFP);
594  MachineLocation Src(SPU::R1, 0);
595  Moves.push_back(MachineMove(0, Dst, Src));
596}
597
598
599int
600SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
601  // FIXME: Most probably dwarf numbers differs for Linux and Darwin
602  return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
603}
604
605#include "SPUGenRegisterInfo.inc"
606