HexagonSubtarget.cpp revision d410eaba04211d53a523a518a5e315eb24c1072f 
1//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the Hexagon specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonSubtarget.h"
15#include "Hexagon.h"
16#include "llvm/Support/CommandLine.h"
17#include "llvm/Support/ErrorHandling.h"
18using namespace llvm;
19
20#define GET_SUBTARGETINFO_CTOR
21#define GET_SUBTARGETINFO_TARGET_DESC
22#include "HexagonGenSubtargetInfo.inc"
23
24static cl::opt<bool>
25EnableV3("enable-hexagon-v3", cl::Hidden,
26         cl::desc("Enable Hexagon V3 instructions."));
27
28static cl::opt<bool>
29EnableMemOps(
30    "enable-hexagon-memops",
31    cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed,
32    cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
33
34HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
35  HexagonGenSubtargetInfo(TT, CPU, FS),
36  HexagonArchVersion(V1),
37  CPUString(CPU.str()) {
38  ParseSubtargetFeatures(CPU, FS);
39
40  switch(HexagonArchVersion) {
41  case HexagonSubtarget::V2:
42    break;
43  case HexagonSubtarget::V3:
44    EnableV3 = true;
45    break;
46  case HexagonSubtarget::V4:
47    break;
48  default:
49    llvm_unreachable("Unknown Architecture Version.");
50  }
51
52  // Initialize scheduling itinerary for the specified CPU.
53  InstrItins = getInstrItineraryForCPU(CPUString);
54
55  // Max issue per cycle == bundle width.
56  InstrItins.IssueWidth = 4;
57
58  if (EnableMemOps)
59    UseMemOps = true;
60  else
61    UseMemOps = false;
62}
63