MipsInstrInfo.cpp revision 22fee2dff4c43b551aefa44a96ca74fcade6bfac
1//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MipsInstrInfo.h" 15#include "MipsTargetMachine.h" 16#include "MipsMachineFunction.h" 17#include "llvm/ADT/STLExtras.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/MachineRegisterInfo.h" 20#include "llvm/Support/ErrorHandling.h" 21 22#define GET_INSTRINFO_MC_DESC 23#include "MipsGenInstrInfo.inc" 24 25using namespace llvm; 26 27MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm) 28 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)), 29 TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 30 31static bool isZeroImm(const MachineOperand &op) { 32 return op.isImm() && op.getImm() == 0; 33} 34 35/// isLoadFromStackSlot - If the specified machine instruction is a direct 36/// load from a stack slot, return the virtual or physical register number of 37/// the destination along with the FrameIndex of the loaded stack slot. If 38/// not, return 0. This predicate must return 0 if the instruction has 39/// any side effects other than loading from the stack slot. 40unsigned MipsInstrInfo:: 41isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const 42{ 43 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) || 44 (MI->getOpcode() == Mips::LDC1)) { 45 if ((MI->getOperand(2).isFI()) && // is a stack slot 46 (MI->getOperand(1).isImm()) && // the imm is zero 47 (isZeroImm(MI->getOperand(1)))) { 48 FrameIndex = MI->getOperand(2).getIndex(); 49 return MI->getOperand(0).getReg(); 50 } 51 } 52 53 return 0; 54} 55 56/// isStoreToStackSlot - If the specified machine instruction is a direct 57/// store to a stack slot, return the virtual or physical register number of 58/// the source reg along with the FrameIndex of the loaded stack slot. If 59/// not, return 0. This predicate must return 0 if the instruction has 60/// any side effects other than storing to the stack slot. 61unsigned MipsInstrInfo:: 62isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const 63{ 64 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) || 65 (MI->getOpcode() == Mips::SDC1)) { 66 if ((MI->getOperand(2).isFI()) && // is a stack slot 67 (MI->getOperand(1).isImm()) && // the imm is zero 68 (isZeroImm(MI->getOperand(1)))) { 69 FrameIndex = MI->getOperand(2).getIndex(); 70 return MI->getOperand(0).getReg(); 71 } 72 } 73 return 0; 74} 75 76/// insertNoop - If data hazard condition is found insert the target nop 77/// instruction. 78void MipsInstrInfo:: 79insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const 80{ 81 DebugLoc DL; 82 BuildMI(MBB, MI, DL, get(Mips::NOP)); 83} 84 85void MipsInstrInfo:: 86copyPhysReg(MachineBasicBlock &MBB, 87 MachineBasicBlock::iterator I, DebugLoc DL, 88 unsigned DestReg, unsigned SrcReg, 89 bool KillSrc) const { 90 bool DestCPU = Mips::CPURegsRegClass.contains(DestReg); 91 bool SrcCPU = Mips::CPURegsRegClass.contains(SrcReg); 92 93 // CPU-CPU is the most common. 94 if (DestCPU && SrcCPU) { 95 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) 96 .addReg(SrcReg, getKillRegState(KillSrc)); 97 return; 98 } 99 100 // Copy to CPU from other registers. 101 if (DestCPU) { 102 if (Mips::CCRRegClass.contains(SrcReg)) 103 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg) 104 .addReg(SrcReg, getKillRegState(KillSrc)); 105 else if (Mips::FGR32RegClass.contains(SrcReg)) 106 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg) 107 .addReg(SrcReg, getKillRegState(KillSrc)); 108 else if (SrcReg == Mips::HI) 109 BuildMI(MBB, I, DL, get(Mips::MFHI), DestReg); 110 else if (SrcReg == Mips::LO) 111 BuildMI(MBB, I, DL, get(Mips::MFLO), DestReg); 112 else 113 llvm_unreachable("Copy to CPU from invalid register"); 114 return; 115 } 116 117 // Copy to other registers from CPU. 118 if (SrcCPU) { 119 if (Mips::CCRRegClass.contains(DestReg)) 120 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg) 121 .addReg(SrcReg, getKillRegState(KillSrc)); 122 else if (Mips::FGR32RegClass.contains(DestReg)) 123 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg) 124 .addReg(SrcReg, getKillRegState(KillSrc)); 125 else if (DestReg == Mips::HI) 126 BuildMI(MBB, I, DL, get(Mips::MTHI)) 127 .addReg(SrcReg, getKillRegState(KillSrc)); 128 else if (DestReg == Mips::LO) 129 BuildMI(MBB, I, DL, get(Mips::MTLO)) 130 .addReg(SrcReg, getKillRegState(KillSrc)); 131 else 132 llvm_unreachable("Copy from CPU to invalid register"); 133 return; 134 } 135 136 if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) { 137 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg) 138 .addReg(SrcReg, getKillRegState(KillSrc)); 139 return; 140 } 141 142 if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) { 143 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg) 144 .addReg(SrcReg, getKillRegState(KillSrc)); 145 return; 146 } 147 148 if (Mips::CCRRegClass.contains(DestReg, SrcReg)) { 149 BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg) 150 .addReg(SrcReg, getKillRegState(KillSrc)); 151 return; 152 } 153 llvm_unreachable("Cannot copy registers"); 154} 155 156void MipsInstrInfo:: 157storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 158 unsigned SrcReg, bool isKill, int FI, 159 const TargetRegisterClass *RC, 160 const TargetRegisterInfo *TRI) const { 161 DebugLoc DL; 162 if (I != MBB.end()) DL = I->getDebugLoc(); 163 164 if (RC == Mips::CPURegsRegisterClass) 165 BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill)) 166 .addImm(0).addFrameIndex(FI); 167 else if (RC == Mips::FGR32RegisterClass) 168 BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill)) 169 .addImm(0).addFrameIndex(FI); 170 else if (RC == Mips::AFGR64RegisterClass) { 171 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) { 172 BuildMI(MBB, I, DL, get(Mips::SDC1)) 173 .addReg(SrcReg, getKillRegState(isKill)) 174 .addImm(0).addFrameIndex(FI); 175 } else { 176 const TargetRegisterInfo *TRI = 177 MBB.getParent()->getTarget().getRegisterInfo(); 178 const unsigned *SubSet = TRI->getSubRegisters(SrcReg); 179 BuildMI(MBB, I, DL, get(Mips::SWC1)) 180 .addReg(SubSet[0], getKillRegState(isKill)) 181 .addImm(0).addFrameIndex(FI); 182 BuildMI(MBB, I, DL, get(Mips::SWC1)) 183 .addReg(SubSet[1], getKillRegState(isKill)) 184 .addImm(4).addFrameIndex(FI); 185 } 186 } else 187 llvm_unreachable("Register class not handled!"); 188} 189 190void MipsInstrInfo:: 191loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 192 unsigned DestReg, int FI, 193 const TargetRegisterClass *RC, 194 const TargetRegisterInfo *TRI) const 195{ 196 DebugLoc DL; 197 if (I != MBB.end()) DL = I->getDebugLoc(); 198 199 if (RC == Mips::CPURegsRegisterClass) 200 BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI); 201 else if (RC == Mips::FGR32RegisterClass) 202 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI); 203 else if (RC == Mips::AFGR64RegisterClass) { 204 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) { 205 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI); 206 } else { 207 const TargetRegisterInfo *TRI = 208 MBB.getParent()->getTarget().getRegisterInfo(); 209 const unsigned *SubSet = TRI->getSubRegisters(DestReg); 210 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0]) 211 .addImm(0).addFrameIndex(FI); 212 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1]) 213 .addImm(4).addFrameIndex(FI); 214 } 215 } else 216 llvm_unreachable("Register class not handled!"); 217} 218 219//===----------------------------------------------------------------------===// 220// Branch Analysis 221//===----------------------------------------------------------------------===// 222 223static unsigned GetAnalyzableBrOpc(unsigned Opc) { 224 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || 225 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || 226 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? Opc : 0; 227} 228 229/// GetOppositeBranchOpc - Return the inverse of the specified 230/// opcode, e.g. turning BEQ to BNE. 231unsigned Mips::GetOppositeBranchOpc(unsigned Opc) 232{ 233 switch (Opc) { 234 default: llvm_unreachable("Illegal opcode!"); 235 case Mips::BEQ : return Mips::BNE; 236 case Mips::BNE : return Mips::BEQ; 237 case Mips::BGTZ : return Mips::BLEZ; 238 case Mips::BGEZ : return Mips::BLTZ; 239 case Mips::BLTZ : return Mips::BGEZ; 240 case Mips::BLEZ : return Mips::BGTZ; 241 case Mips::BC1T : return Mips::BC1F; 242 case Mips::BC1F : return Mips::BC1T; 243 } 244} 245 246static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc, 247 MachineBasicBlock *&BB, 248 SmallVectorImpl<MachineOperand>& Cond) { 249 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch"); 250 int NumOp = Inst->getNumExplicitOperands(); 251 252 // for both int and fp branches, the last explicit operand is the 253 // MBB. 254 BB = Inst->getOperand(NumOp-1).getMBB(); 255 Cond.push_back(MachineOperand::CreateImm(Opc)); 256 257 for (int i=0; i<NumOp-1; i++) 258 Cond.push_back(Inst->getOperand(i)); 259} 260 261bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 262 MachineBasicBlock *&TBB, 263 MachineBasicBlock *&FBB, 264 SmallVectorImpl<MachineOperand> &Cond, 265 bool AllowModify) const 266{ 267 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 268 269 // Skip all the debug instructions. 270 while (I != REnd && I->isDebugValue()) 271 ++I; 272 273 if (I == REnd || !isUnpredicatedTerminator(&*I)) { 274 // If this block ends with no branches (it just falls through to its succ) 275 // just return false, leaving TBB/FBB null. 276 TBB = FBB = NULL; 277 return false; 278 } 279 280 MachineInstr *LastInst = &*I; 281 unsigned LastOpc = LastInst->getOpcode(); 282 283 // Not an analyzable branch (must be an indirect jump). 284 if (!GetAnalyzableBrOpc(LastOpc)) 285 return true; 286 287 // Get the second to last instruction in the block. 288 unsigned SecondLastOpc = 0; 289 MachineInstr *SecondLastInst = NULL; 290 291 if (++I != REnd) { 292 SecondLastInst = &*I; 293 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode()); 294 295 // Not an analyzable branch (must be an indirect jump). 296 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc) 297 return true; 298 } 299 300 // If there is only one terminator instruction, process it. 301 if (!SecondLastOpc) { 302 // Unconditional branch 303 if (LastOpc == Mips::J) { 304 TBB = LastInst->getOperand(0).getMBB(); 305 return false; 306 } 307 308 // Conditional branch 309 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); 310 return false; 311 } 312 313 // If we reached here, there are two branches. 314 // If there are three terminators, we don't know what sort of block this is. 315 if (++I != REnd && isUnpredicatedTerminator(&*I)) 316 return true; 317 318 // If second to last instruction is an unconditional branch, 319 // analyze it and remove the last instruction. 320 if (SecondLastOpc == Mips::J) { 321 // Return if the last instruction cannot be removed. 322 if (!AllowModify) 323 return true; 324 325 TBB = SecondLastInst->getOperand(0).getMBB(); 326 LastInst->eraseFromParent(); 327 return false; 328 } 329 330 // Conditional branch followed by an unconditional branch. 331 // The last one must be unconditional. 332 if (LastOpc != Mips::J) 333 return true; 334 335 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); 336 FBB = LastInst->getOperand(0).getMBB(); 337 338 return false; 339} 340 341void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, 342 MachineBasicBlock *TBB, DebugLoc DL, 343 const SmallVectorImpl<MachineOperand>& Cond) 344 const { 345 unsigned Opc = Cond[0].getImm(); 346 const MCInstrDesc &MCID = get(Opc); 347 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); 348 349 for (unsigned i = 1; i < Cond.size(); ++i) 350 MIB.addReg(Cond[i].getReg()); 351 352 MIB.addMBB(TBB); 353} 354 355unsigned MipsInstrInfo:: 356InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 357 MachineBasicBlock *FBB, 358 const SmallVectorImpl<MachineOperand> &Cond, 359 DebugLoc DL) const { 360 // Shouldn't be a fall through. 361 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 362 363 // # of condition operands: 364 // Unconditional branches: 0 365 // Floating point branches: 1 (opc) 366 // Int BranchZero: 2 (opc, reg) 367 // Int Branch: 3 (opc, reg0, reg1) 368 assert((Cond.size() <= 3) && 369 "# of Mips branch conditions must be <= 3!"); 370 371 // Two-way Conditional branch. 372 if (FBB) { 373 BuildCondBr(MBB, TBB, DL, Cond); 374 BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB); 375 return 2; 376 } 377 378 // One way branch. 379 // Unconditional branch. 380 if (Cond.empty()) 381 BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB); 382 else // Conditional branch. 383 BuildCondBr(MBB, TBB, DL, Cond); 384 return 1; 385} 386 387unsigned MipsInstrInfo:: 388RemoveBranch(MachineBasicBlock &MBB) const 389{ 390 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 391 MachineBasicBlock::reverse_iterator FirstBr; 392 unsigned removed; 393 394 // Skip all the debug instructions. 395 while (I != REnd && I->isDebugValue()) 396 ++I; 397 398 FirstBr = I; 399 400 // Up to 2 branches are removed. 401 // Note that indirect branches are not removed. 402 for(removed = 0; I != REnd && removed < 2; ++I, ++removed) 403 if (!GetAnalyzableBrOpc(I->getOpcode())) 404 break; 405 406 MBB.erase(I.base(), FirstBr.base()); 407 408 return removed; 409} 410 411/// ReverseBranchCondition - Return the inverse opcode of the 412/// specified Branch instruction. 413bool MipsInstrInfo:: 414ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 415{ 416 assert( (Cond.size() && Cond.size() <= 3) && 417 "Invalid Mips branch condition!"); 418 Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm())); 419 return false; 420} 421 422/// getGlobalBaseReg - Return a virtual register initialized with the 423/// the global base register value. Output instructions required to 424/// initialize the register in the function entry block, if necessary. 425/// 426unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 427 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>(); 428 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg(); 429 if (GlobalBaseReg != 0) 430 return GlobalBaseReg; 431 432 // Insert the set of GlobalBaseReg into the first MBB of the function 433 MachineBasicBlock &FirstMBB = MF->front(); 434 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 435 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 436 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 437 438 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass); 439 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), 440 GlobalBaseReg).addReg(Mips::GP); 441 RegInfo.addLiveIn(Mips::GP); 442 443 MipsFI->setGlobalBaseReg(GlobalBaseReg); 444 return GlobalBaseReg; 445} 446