MipsInstrInfo.cpp revision 4552c9a3b34ad9b2085635266348d0d9b95514a6
1//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MipsInstrInfo.h" 15#include "MipsTargetMachine.h" 16#include "MipsMachineFunction.h" 17#include "llvm/ADT/STLExtras.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/MachineRegisterInfo.h" 20#include "llvm/Support/ErrorHandling.h" 21#include "MipsGenInstrInfo.inc" 22 23using namespace llvm; 24 25MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm) 26 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)), 27 TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 28 29static bool isZeroImm(const MachineOperand &op) { 30 return op.isImm() && op.getImm() == 0; 31} 32 33/// isLoadFromStackSlot - If the specified machine instruction is a direct 34/// load from a stack slot, return the virtual or physical register number of 35/// the destination along with the FrameIndex of the loaded stack slot. If 36/// not, return 0. This predicate must return 0 if the instruction has 37/// any side effects other than loading from the stack slot. 38unsigned MipsInstrInfo:: 39isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const 40{ 41 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) || 42 (MI->getOpcode() == Mips::LDC1)) { 43 if ((MI->getOperand(2).isFI()) && // is a stack slot 44 (MI->getOperand(1).isImm()) && // the imm is zero 45 (isZeroImm(MI->getOperand(1)))) { 46 FrameIndex = MI->getOperand(2).getIndex(); 47 return MI->getOperand(0).getReg(); 48 } 49 } 50 51 return 0; 52} 53 54/// isStoreToStackSlot - If the specified machine instruction is a direct 55/// store to a stack slot, return the virtual or physical register number of 56/// the source reg along with the FrameIndex of the loaded stack slot. If 57/// not, return 0. This predicate must return 0 if the instruction has 58/// any side effects other than storing to the stack slot. 59unsigned MipsInstrInfo:: 60isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const 61{ 62 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) || 63 (MI->getOpcode() == Mips::SDC1)) { 64 if ((MI->getOperand(2).isFI()) && // is a stack slot 65 (MI->getOperand(1).isImm()) && // the imm is zero 66 (isZeroImm(MI->getOperand(1)))) { 67 FrameIndex = MI->getOperand(2).getIndex(); 68 return MI->getOperand(0).getReg(); 69 } 70 } 71 return 0; 72} 73 74/// insertNoop - If data hazard condition is found insert the target nop 75/// instruction. 76void MipsInstrInfo:: 77insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const 78{ 79 DebugLoc DL; 80 BuildMI(MBB, MI, DL, get(Mips::NOP)); 81} 82 83void MipsInstrInfo:: 84copyPhysReg(MachineBasicBlock &MBB, 85 MachineBasicBlock::iterator I, DebugLoc DL, 86 unsigned DestReg, unsigned SrcReg, 87 bool KillSrc) const { 88 bool DestCPU = Mips::CPURegsRegClass.contains(DestReg); 89 bool SrcCPU = Mips::CPURegsRegClass.contains(SrcReg); 90 91 // CPU-CPU is the most common. 92 if (DestCPU && SrcCPU) { 93 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) 94 .addReg(SrcReg, getKillRegState(KillSrc)); 95 return; 96 } 97 98 // Copy to CPU from other registers. 99 if (DestCPU) { 100 if (Mips::CCRRegClass.contains(SrcReg)) 101 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg) 102 .addReg(SrcReg, getKillRegState(KillSrc)); 103 else if (Mips::FGR32RegClass.contains(SrcReg)) 104 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg) 105 .addReg(SrcReg, getKillRegState(KillSrc)); 106 else if (SrcReg == Mips::HI) 107 BuildMI(MBB, I, DL, get(Mips::MFHI), DestReg); 108 else if (SrcReg == Mips::LO) 109 BuildMI(MBB, I, DL, get(Mips::MFLO), DestReg); 110 else 111 llvm_unreachable("Copy to CPU from invalid register"); 112 return; 113 } 114 115 // Copy to other registers from CPU. 116 if (SrcCPU) { 117 if (Mips::CCRRegClass.contains(DestReg)) 118 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg) 119 .addReg(SrcReg, getKillRegState(KillSrc)); 120 else if (Mips::FGR32RegClass.contains(DestReg)) 121 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg) 122 .addReg(SrcReg, getKillRegState(KillSrc)); 123 else if (DestReg == Mips::HI) 124 BuildMI(MBB, I, DL, get(Mips::MTHI)) 125 .addReg(SrcReg, getKillRegState(KillSrc)); 126 else if (DestReg == Mips::LO) 127 BuildMI(MBB, I, DL, get(Mips::MTLO)) 128 .addReg(SrcReg, getKillRegState(KillSrc)); 129 else 130 llvm_unreachable("Copy from CPU to invalid register"); 131 return; 132 } 133 134 if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) { 135 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg) 136 .addReg(SrcReg, getKillRegState(KillSrc)); 137 return; 138 } 139 140 if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) { 141 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg) 142 .addReg(SrcReg, getKillRegState(KillSrc)); 143 return; 144 } 145 146 if (Mips::CCRRegClass.contains(DestReg, SrcReg)) { 147 BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg) 148 .addReg(SrcReg, getKillRegState(KillSrc)); 149 return; 150 } 151 llvm_unreachable("Cannot copy registers"); 152} 153 154void MipsInstrInfo:: 155storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 156 unsigned SrcReg, bool isKill, int FI, 157 const TargetRegisterClass *RC, 158 const TargetRegisterInfo *TRI) const { 159 DebugLoc DL; 160 if (I != MBB.end()) DL = I->getDebugLoc(); 161 162 if (RC == Mips::CPURegsRegisterClass) 163 BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill)) 164 .addImm(0).addFrameIndex(FI); 165 else if (RC == Mips::FGR32RegisterClass) 166 BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill)) 167 .addImm(0).addFrameIndex(FI); 168 else if (RC == Mips::AFGR64RegisterClass) { 169 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) { 170 BuildMI(MBB, I, DL, get(Mips::SDC1)) 171 .addReg(SrcReg, getKillRegState(isKill)) 172 .addImm(0).addFrameIndex(FI); 173 } else { 174 const TargetRegisterInfo *TRI = 175 MBB.getParent()->getTarget().getRegisterInfo(); 176 const unsigned *SubSet = TRI->getSubRegisters(SrcReg); 177 BuildMI(MBB, I, DL, get(Mips::SWC1)) 178 .addReg(SubSet[0], getKillRegState(isKill)) 179 .addImm(0).addFrameIndex(FI); 180 BuildMI(MBB, I, DL, get(Mips::SWC1)) 181 .addReg(SubSet[1], getKillRegState(isKill)) 182 .addImm(4).addFrameIndex(FI); 183 } 184 } else 185 llvm_unreachable("Register class not handled!"); 186} 187 188void MipsInstrInfo:: 189loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 190 unsigned DestReg, int FI, 191 const TargetRegisterClass *RC, 192 const TargetRegisterInfo *TRI) const 193{ 194 DebugLoc DL; 195 if (I != MBB.end()) DL = I->getDebugLoc(); 196 197 if (RC == Mips::CPURegsRegisterClass) 198 BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI); 199 else if (RC == Mips::FGR32RegisterClass) 200 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI); 201 else if (RC == Mips::AFGR64RegisterClass) { 202 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) { 203 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI); 204 } else { 205 const TargetRegisterInfo *TRI = 206 MBB.getParent()->getTarget().getRegisterInfo(); 207 const unsigned *SubSet = TRI->getSubRegisters(DestReg); 208 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0]) 209 .addImm(0).addFrameIndex(FI); 210 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1]) 211 .addImm(4).addFrameIndex(FI); 212 } 213 } else 214 llvm_unreachable("Register class not handled!"); 215} 216 217//===----------------------------------------------------------------------===// 218// Branch Analysis 219//===----------------------------------------------------------------------===// 220 221static unsigned GetAnalyzableBrOpc(unsigned Opc) { 222 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || 223 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || 224 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? Opc : 0; 225} 226 227/// GetOppositeBranchOpc - Return the inverse of the specified 228/// opcode, e.g. turning BEQ to BNE. 229unsigned Mips::GetOppositeBranchOpc(unsigned Opc) 230{ 231 switch (Opc) { 232 default: llvm_unreachable("Illegal opcode!"); 233 case Mips::BEQ : return Mips::BNE; 234 case Mips::BNE : return Mips::BEQ; 235 case Mips::BGTZ : return Mips::BLEZ; 236 case Mips::BGEZ : return Mips::BLTZ; 237 case Mips::BLTZ : return Mips::BGEZ; 238 case Mips::BLEZ : return Mips::BGTZ; 239 case Mips::BC1T : return Mips::BC1F; 240 case Mips::BC1F : return Mips::BC1T; 241 } 242} 243 244static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc, 245 MachineBasicBlock *&BB, 246 SmallVectorImpl<MachineOperand>& Cond) { 247 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch"); 248 int NumOp = Inst->getNumExplicitOperands(); 249 250 // for both int and fp branches, the last explicit operand is the 251 // MBB. 252 BB = Inst->getOperand(NumOp-1).getMBB(); 253 Cond.push_back(MachineOperand::CreateImm(Opc)); 254 255 for (int i=0; i<NumOp-1; i++) 256 Cond.push_back(Inst->getOperand(i)); 257} 258 259bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 260 MachineBasicBlock *&TBB, 261 MachineBasicBlock *&FBB, 262 SmallVectorImpl<MachineOperand> &Cond, 263 bool AllowModify) const 264{ 265 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 266 267 // Skip all the debug instructions. 268 while (I != REnd && I->isDebugValue()) 269 ++I; 270 271 if (I == REnd || !isUnpredicatedTerminator(&*I)) { 272 // If this block ends with no branches (it just falls through to its succ) 273 // just return false, leaving TBB/FBB null. 274 TBB = FBB = NULL; 275 return false; 276 } 277 278 MachineInstr *LastInst = &*I; 279 unsigned LastOpc = LastInst->getOpcode(); 280 281 // Not an analyzable branch (must be an indirect jump). 282 if (!GetAnalyzableBrOpc(LastOpc)) 283 return true; 284 285 // Get the second to last instruction in the block. 286 unsigned SecondLastOpc = 0; 287 MachineInstr *SecondLastInst = NULL; 288 289 if (++I != REnd) { 290 SecondLastInst = &*I; 291 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode()); 292 293 // Not an analyzable branch (must be an indirect jump). 294 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc) 295 return true; 296 } 297 298 // If there is only one terminator instruction, process it. 299 if (!SecondLastOpc) { 300 // Unconditional branch 301 if (LastOpc == Mips::J) { 302 TBB = LastInst->getOperand(0).getMBB(); 303 return false; 304 } 305 306 // Conditional branch 307 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); 308 return false; 309 } 310 311 // If we reached here, there are two branches. 312 // If there are three terminators, we don't know what sort of block this is. 313 if (++I != REnd && isUnpredicatedTerminator(&*I)) 314 return true; 315 316 // If second to last instruction is an unconditional branch, 317 // analyze it and remove the last instruction. 318 if (SecondLastOpc == Mips::J) { 319 // Return if the last instruction cannot be removed. 320 if (!AllowModify) 321 return true; 322 323 TBB = SecondLastInst->getOperand(0).getMBB(); 324 LastInst->eraseFromParent(); 325 return false; 326 } 327 328 // Conditional branch followed by an unconditional branch. 329 // The last one must be unconditional. 330 if (LastOpc != Mips::J) 331 return true; 332 333 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); 334 FBB = LastInst->getOperand(0).getMBB(); 335 336 return false; 337} 338 339void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, 340 MachineBasicBlock *TBB, DebugLoc DL, 341 const SmallVectorImpl<MachineOperand>& Cond) 342 const { 343 unsigned Opc = Cond[0].getImm(); 344 const TargetInstrDesc &TID = get(Opc); 345 MachineInstrBuilder MIB = BuildMI(&MBB, DL, TID); 346 347 for (unsigned i = 1; i < Cond.size(); ++i) 348 MIB.addReg(Cond[i].getReg()); 349 350 MIB.addMBB(TBB); 351} 352 353unsigned MipsInstrInfo:: 354InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 355 MachineBasicBlock *FBB, 356 const SmallVectorImpl<MachineOperand> &Cond, 357 DebugLoc DL) const { 358 // Shouldn't be a fall through. 359 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 360 361 // # of condition operands: 362 // Unconditional branches: 0 363 // Floating point branches: 1 (opc) 364 // Int BranchZero: 2 (opc, reg) 365 // Int Branch: 3 (opc, reg0, reg1) 366 assert((Cond.size() <= 3) && 367 "# of Mips branch conditions must be <= 3!"); 368 369 // Two-way Conditional branch. 370 if (FBB) { 371 BuildCondBr(MBB, TBB, DL, Cond); 372 BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB); 373 return 2; 374 } 375 376 // One way branch. 377 // Unconditional branch. 378 if (Cond.empty()) 379 BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB); 380 else // Conditional branch. 381 BuildCondBr(MBB, TBB, DL, Cond); 382 return 1; 383} 384 385unsigned MipsInstrInfo:: 386RemoveBranch(MachineBasicBlock &MBB) const 387{ 388 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 389 MachineBasicBlock::reverse_iterator FirstBr; 390 unsigned removed; 391 392 // Skip all the debug instructions. 393 while (I != REnd && I->isDebugValue()) 394 ++I; 395 396 FirstBr = I; 397 398 // Up to 2 branches are removed. 399 // Note that indirect branches are not removed. 400 for(removed = 0; I != REnd && removed < 2; ++I, ++removed) 401 if (!GetAnalyzableBrOpc(I->getOpcode())) 402 break; 403 404 MBB.erase(I.base(), FirstBr.base()); 405 406 return removed; 407} 408 409/// ReverseBranchCondition - Return the inverse opcode of the 410/// specified Branch instruction. 411bool MipsInstrInfo:: 412ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 413{ 414 assert( (Cond.size() && Cond.size() <= 3) && 415 "Invalid Mips branch condition!"); 416 Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm())); 417 return false; 418} 419 420/// getGlobalBaseReg - Return a virtual register initialized with the 421/// the global base register value. Output instructions required to 422/// initialize the register in the function entry block, if necessary. 423/// 424unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 425 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>(); 426 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg(); 427 if (GlobalBaseReg != 0) 428 return GlobalBaseReg; 429 430 // Insert the set of GlobalBaseReg into the first MBB of the function 431 MachineBasicBlock &FirstMBB = MF->front(); 432 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 433 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 434 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 435 436 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass); 437 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), 438 GlobalBaseReg).addReg(Mips::GP); 439 RegInfo.addLiveIn(Mips::GP); 440 441 MipsFI->setGlobalBaseReg(GlobalBaseReg); 442 return GlobalBaseReg; 443} 444