MipsInstrInfo.cpp revision dc54d317e7a381ef8e4aca80d54ad1466bb85dda 
1//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsInstrInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "MipsGenInstrInfo.inc"
19
20using namespace llvm;
21
22MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
23  : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
24    TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
25
26static bool isZeroImm(const MachineOperand &op) {
27  return op.isImm() && op.getImm() == 0;
28}
29
30/// Return true if the instruction is a register to register move and
31/// leave the source and dest operands in the passed parameters.
32bool MipsInstrInfo::
33isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
34            unsigned &SrcSubIdx, unsigned &DstSubIdx) const
35{
36  SrcSubIdx = DstSubIdx = 0; // No sub-registers.
37
38  //  addu  $dst, $src, $zero || addu  $dst, $zero, $src
39  //  or    $dst, $src, $zero || or    $dst, $zero, $src
40  if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
41    if (MI.getOperand(1).getReg() == Mips::ZERO) {
42      DstReg = MI.getOperand(0).getReg();
43      SrcReg = MI.getOperand(2).getReg();
44      return true;
45    } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
46      DstReg = MI.getOperand(0).getReg();
47      SrcReg = MI.getOperand(1).getReg();
48      return true;
49    }
50  }
51
52  // mov $fpDst, $fpSrc
53  // mfc $gpDst, $fpSrc
54  // mtc $fpDst, $gpSrc
55  if (MI.getOpcode() == Mips::FMOV_SO32 || MI.getOpcode() == Mips::FMOV_AS32 ||
56      MI.getOpcode() == Mips::FMOV_D32 || MI.getOpcode() == Mips::MFC1A ||
57      MI.getOpcode() == Mips::MFC1 || MI.getOpcode() == Mips::MTC1A ||
58      MI.getOpcode() == Mips::MTC1 ) {
59    DstReg = MI.getOperand(0).getReg();
60    SrcReg = MI.getOperand(1).getReg();
61    return true;
62  }
63
64  //  addiu $dst, $src, 0
65  if (MI.getOpcode() == Mips::ADDiu) {
66    if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
67      DstReg = MI.getOperand(0).getReg();
68      SrcReg = MI.getOperand(1).getReg();
69      return true;
70    }
71  }
72  return false;
73}
74
75/// isLoadFromStackSlot - If the specified machine instruction is a direct
76/// load from a stack slot, return the virtual or physical register number of
77/// the destination along with the FrameIndex of the loaded stack slot.  If
78/// not, return 0.  This predicate must return 0 if the instruction has
79/// any side effects other than loading from the stack slot.
80unsigned MipsInstrInfo::
81isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
82{
83  if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
84      (MI->getOpcode() == Mips::LWC1A) || (MI->getOpcode() == Mips::LDC1)) {
85    if ((MI->getOperand(2).isFI()) && // is a stack slot
86        (MI->getOperand(1).isImm()) &&  // the imm is zero
87        (isZeroImm(MI->getOperand(1)))) {
88      FrameIndex = MI->getOperand(2).getIndex();
89      return MI->getOperand(0).getReg();
90    }
91  }
92
93  return 0;
94}
95
96/// isStoreToStackSlot - If the specified machine instruction is a direct
97/// store to a stack slot, return the virtual or physical register number of
98/// the source reg along with the FrameIndex of the loaded stack slot.  If
99/// not, return 0.  This predicate must return 0 if the instruction has
100/// any side effects other than storing to the stack slot.
101unsigned MipsInstrInfo::
102isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
103{
104  if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
105      (MI->getOpcode() == Mips::SWC1A) || (MI->getOpcode() == Mips::SDC1)) {
106    if ((MI->getOperand(2).isFI()) && // is a stack slot
107        (MI->getOperand(1).isImm()) &&  // the imm is zero
108        (isZeroImm(MI->getOperand(1)))) {
109      FrameIndex = MI->getOperand(2).getIndex();
110      return MI->getOperand(0).getReg();
111    }
112  }
113  return 0;
114}
115
116/// insertNoop - If data hazard condition is found insert the target nop
117/// instruction.
118void MipsInstrInfo::
119insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
120{
121  BuildMI(MBB, MI, get(Mips::NOP));
122}
123
124bool MipsInstrInfo::
125copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
126             unsigned DestReg, unsigned SrcReg,
127             const TargetRegisterClass *DestRC,
128             const TargetRegisterClass *SrcRC) const {
129  if (DestRC != SrcRC) {
130    if ((DestRC == Mips::CPURegsRegisterClass) &&
131        (SrcRC == Mips::FGR32RegisterClass))
132      BuildMI(MBB, I, get(Mips::MFC1), DestReg).addReg(SrcReg);
133    else if ((DestRC == Mips::CPURegsRegisterClass) &&
134             (SrcRC == Mips::AFGR32RegisterClass))
135      BuildMI(MBB, I, get(Mips::MFC1A), DestReg).addReg(SrcReg);
136    else if ((DestRC == Mips::FGR32RegisterClass) &&
137             (SrcRC == Mips::CPURegsRegisterClass))
138      BuildMI(MBB, I, get(Mips::MTC1), DestReg).addReg(SrcReg);
139    else if ((DestRC == Mips::AFGR32RegisterClass) &&
140             (SrcRC == Mips::CPURegsRegisterClass))
141      BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
142    else if ((DestRC == Mips::AFGR32RegisterClass) &&
143             (SrcRC == Mips::CPURegsRegisterClass))
144      BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
145    else if ((SrcRC == Mips::CCRRegisterClass) &&
146             (SrcReg == Mips::FCR31))
147      return true; // This register is used implicitly, no copy needed.
148    else if ((DestRC == Mips::CCRRegisterClass) &&
149             (DestReg == Mips::FCR31))
150      return true; // This register is used implicitly, no copy needed.
151    else if ((DestRC == Mips::HILORegisterClass) &&
152             (SrcRC == Mips::CPURegsRegisterClass)) {
153      unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
154      BuildMI(MBB, I, get(Opc), DestReg);
155    } else if ((SrcRC == Mips::HILORegisterClass) &&
156               (DestRC == Mips::CPURegsRegisterClass)) {
157      unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
158      BuildMI(MBB, I, get(Opc), DestReg);
159    } else
160      // DestRC != SrcRC, Can't copy this register
161      return false;
162
163    return true;
164  }
165
166  if (DestRC == Mips::CPURegsRegisterClass)
167    BuildMI(MBB, I, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
168      .addReg(SrcReg);
169  else if (DestRC == Mips::FGR32RegisterClass)
170    BuildMI(MBB, I, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg);
171  else if (DestRC == Mips::AFGR32RegisterClass)
172    BuildMI(MBB, I, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg);
173  else if (DestRC == Mips::AFGR64RegisterClass)
174    BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
175  else
176    // Can't copy this register
177    return false;
178
179  return true;
180}
181
182void MipsInstrInfo::
183storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
184          unsigned SrcReg, bool isKill, int FI,
185          const TargetRegisterClass *RC) const
186{
187  unsigned Opc;
188  if (RC == Mips::CPURegsRegisterClass)
189    Opc = Mips::SW;
190  else if (RC == Mips::FGR32RegisterClass)
191    Opc = Mips::SWC1;
192  else if (RC == Mips::AFGR32RegisterClass)
193    Opc = Mips::SWC1A;
194  else if (RC == Mips::AFGR64RegisterClass)
195    Opc = Mips::SDC1;
196  else
197    assert(0 && "Can't store this register to stack slot");
198
199  BuildMI(MBB, I, get(Opc)).addReg(SrcReg, false, false, isKill)
200          .addImm(0).addFrameIndex(FI);
201}
202
203void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
204  bool isKill, SmallVectorImpl<MachineOperand> &Addr,
205  const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const
206{
207  unsigned Opc;
208  if (RC == Mips::CPURegsRegisterClass)
209    Opc = Mips::SW;
210  else if (RC == Mips::FGR32RegisterClass)
211    Opc = Mips::SWC1;
212  else if (RC == Mips::AFGR32RegisterClass)
213    Opc = Mips::SWC1A;
214  else if (RC == Mips::AFGR64RegisterClass)
215    Opc = Mips::SDC1;
216  else
217    assert(0 && "Can't store this register");
218
219  MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
220    .addReg(SrcReg, false, false, isKill);
221  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
222    MachineOperand &MO = Addr[i];
223    if (MO.isReg())
224      MIB.addReg(MO.getReg());
225    else if (MO.isImm())
226      MIB.addImm(MO.getImm());
227    else
228      MIB.addFrameIndex(MO.getIndex());
229  }
230  NewMIs.push_back(MIB);
231  return;
232}
233
234void MipsInstrInfo::
235loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
236                     unsigned DestReg, int FI,
237                     const TargetRegisterClass *RC) const
238{
239  unsigned Opc;
240  if (RC == Mips::CPURegsRegisterClass)
241    Opc = Mips::LW;
242  else if (RC == Mips::FGR32RegisterClass)
243    Opc = Mips::LWC1;
244  else if (RC == Mips::AFGR32RegisterClass)
245    Opc = Mips::LWC1A;
246  else if (RC == Mips::AFGR64RegisterClass)
247    Opc = Mips::LDC1;
248  else
249    assert(0 && "Can't load this register from stack slot");
250
251  BuildMI(MBB, I, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
252}
253
254void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
255                                       SmallVectorImpl<MachineOperand> &Addr,
256                                       const TargetRegisterClass *RC,
257                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
258  unsigned Opc;
259  if (RC == Mips::CPURegsRegisterClass)
260    Opc = Mips::LW;
261  else if (RC == Mips::FGR32RegisterClass)
262    Opc = Mips::LWC1;
263  else if (RC == Mips::AFGR32RegisterClass)
264    Opc = Mips::LWC1A;
265  else if (RC == Mips::AFGR64RegisterClass)
266    Opc = Mips::LDC1;
267  else
268    assert(0 && "Can't load this register");
269
270  MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
271  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
272    MachineOperand &MO = Addr[i];
273    if (MO.isReg())
274      MIB.addReg(MO.getReg());
275    else if (MO.isImm())
276      MIB.addImm(MO.getImm());
277    else
278      MIB.addFrameIndex(MO.getIndex());
279  }
280  NewMIs.push_back(MIB);
281  return;
282}
283
284MachineInstr *MipsInstrInfo::
285foldMemoryOperandImpl(MachineFunction &MF,
286                      MachineInstr* MI,
287                      const SmallVectorImpl<unsigned> &Ops, int FI) const
288{
289  if (Ops.size() != 1) return NULL;
290
291  MachineInstr *NewMI = NULL;
292
293  switch (MI->getOpcode()) {
294  case Mips::ADDu:
295    if ((MI->getOperand(0).isReg()) &&
296        (MI->getOperand(1).isReg()) &&
297        (MI->getOperand(1).getReg() == Mips::ZERO) &&
298        (MI->getOperand(2).isReg())) {
299      if (Ops[0] == 0) {    // COPY -> STORE
300        unsigned SrcReg = MI->getOperand(2).getReg();
301        bool isKill = MI->getOperand(2).isKill();
302        NewMI = BuildMI(MF, get(Mips::SW)).addReg(SrcReg, false, false, isKill)
303          .addImm(0).addFrameIndex(FI);
304      } else {              // COPY -> LOAD
305        unsigned DstReg = MI->getOperand(0).getReg();
306        bool isDead = MI->getOperand(0).isDead();
307        NewMI = BuildMI(MF, get(Mips::LW))
308          .addReg(DstReg, true, false, false, isDead)
309          .addImm(0).addFrameIndex(FI);
310      }
311    }
312    break;
313  case Mips::FMOV_SO32:
314  case Mips::FMOV_AS32:
315  case Mips::FMOV_D32:
316    if ((MI->getOperand(0).isReg()) &&
317        (MI->getOperand(1).isReg())) {
318      const TargetRegisterClass
319        *RC = RI.getRegClass(MI->getOperand(0).getReg());
320      unsigned StoreOpc, LoadOpc;
321
322      if (RC == Mips::FGR32RegisterClass) {
323        LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
324      } else if (RC == Mips::AFGR32RegisterClass) {
325        LoadOpc = Mips::LWC1A; StoreOpc = Mips::SWC1A;
326      } else if (RC == Mips::AFGR64RegisterClass) {
327        LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
328      } else
329        assert(0 && "foldMemoryOperandImpl register unknown");
330
331      if (Ops[0] == 0) {    // COPY -> STORE
332        unsigned SrcReg = MI->getOperand(1).getReg();
333        bool isKill = MI->getOperand(1).isKill();
334        NewMI = BuildMI(MF, get(StoreOpc)).addReg(SrcReg, false, false, isKill)
335          .addImm(0).addFrameIndex(FI) ;
336      } else {              // COPY -> LOAD
337        unsigned DstReg = MI->getOperand(0).getReg();
338        bool isDead = MI->getOperand(0).isDead();
339        NewMI = BuildMI(MF, get(LoadOpc))
340          .addReg(DstReg, true, false, false, isDead)
341          .addImm(0).addFrameIndex(FI);
342      }
343    }
344    break;
345  }
346
347  return NewMI;
348}
349
350//===----------------------------------------------------------------------===//
351// Branch Analysis
352//===----------------------------------------------------------------------===//
353
354/// GetCondFromBranchOpc - Return the Mips CC that matches
355/// the correspondent Branch instruction opcode.
356static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
357{
358  switch (BrOpc) {
359  default: return Mips::COND_INVALID;
360  case Mips::BEQ  : return Mips::COND_E;
361  case Mips::BNE  : return Mips::COND_NE;
362  case Mips::BGTZ : return Mips::COND_GZ;
363  case Mips::BGEZ : return Mips::COND_GEZ;
364  case Mips::BLTZ : return Mips::COND_LZ;
365  case Mips::BLEZ : return Mips::COND_LEZ;
366
367  // We dont do fp branch analysis yet!
368  case Mips::BC1T :
369  case Mips::BC1F : return Mips::COND_INVALID;
370  }
371}
372
373/// GetCondBranchFromCond - Return the Branch instruction
374/// opcode that matches the cc.
375unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
376{
377  switch (CC) {
378  default: assert(0 && "Illegal condition code!");
379  case Mips::COND_E   : return Mips::BEQ;
380  case Mips::COND_NE  : return Mips::BNE;
381  case Mips::COND_GZ  : return Mips::BGTZ;
382  case Mips::COND_GEZ : return Mips::BGEZ;
383  case Mips::COND_LZ  : return Mips::BLTZ;
384  case Mips::COND_LEZ : return Mips::BLEZ;
385
386  case Mips::FCOND_F:
387  case Mips::FCOND_UN:
388  case Mips::FCOND_EQ:
389  case Mips::FCOND_UEQ:
390  case Mips::FCOND_OLT:
391  case Mips::FCOND_ULT:
392  case Mips::FCOND_OLE:
393  case Mips::FCOND_ULE:
394  case Mips::FCOND_SF:
395  case Mips::FCOND_NGLE:
396  case Mips::FCOND_SEQ:
397  case Mips::FCOND_NGL:
398  case Mips::FCOND_LT:
399  case Mips::FCOND_NGE:
400  case Mips::FCOND_LE:
401  case Mips::FCOND_NGT: return Mips::BC1T;
402
403  case Mips::FCOND_T:
404  case Mips::FCOND_OR:
405  case Mips::FCOND_NEQ:
406  case Mips::FCOND_OGL:
407  case Mips::FCOND_UGE:
408  case Mips::FCOND_OGE:
409  case Mips::FCOND_UGT:
410  case Mips::FCOND_OGT:
411  case Mips::FCOND_ST:
412  case Mips::FCOND_GLE:
413  case Mips::FCOND_SNE:
414  case Mips::FCOND_GL:
415  case Mips::FCOND_NLT:
416  case Mips::FCOND_GE:
417  case Mips::FCOND_NLE:
418  case Mips::FCOND_GT: return Mips::BC1F;
419  }
420}
421
422/// GetOppositeBranchCondition - Return the inverse of the specified
423/// condition, e.g. turning COND_E to COND_NE.
424Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
425{
426  switch (CC) {
427  default: assert(0 && "Illegal condition code!");
428  case Mips::COND_E   : return Mips::COND_NE;
429  case Mips::COND_NE  : return Mips::COND_E;
430  case Mips::COND_GZ  : return Mips::COND_LEZ;
431  case Mips::COND_GEZ : return Mips::COND_LZ;
432  case Mips::COND_LZ  : return Mips::COND_GEZ;
433  case Mips::COND_LEZ : return Mips::COND_GZ;
434  case Mips::FCOND_F  : return Mips::FCOND_T;
435  case Mips::FCOND_UN : return Mips::FCOND_OR;
436  case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
437  case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
438  case Mips::FCOND_OLT: return Mips::FCOND_UGE;
439  case Mips::FCOND_ULT: return Mips::FCOND_OGE;
440  case Mips::FCOND_OLE: return Mips::FCOND_UGT;
441  case Mips::FCOND_ULE: return Mips::FCOND_OGT;
442  case Mips::FCOND_SF:  return Mips::FCOND_ST;
443  case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
444  case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
445  case Mips::FCOND_NGL: return Mips::FCOND_GL;
446  case Mips::FCOND_LT:  return Mips::FCOND_NLT;
447  case Mips::FCOND_NGE: return Mips::FCOND_GE;
448  case Mips::FCOND_LE:  return Mips::FCOND_NLE;
449  case Mips::FCOND_NGT: return Mips::FCOND_GT;
450  }
451}
452
453bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
454                                  MachineBasicBlock *&TBB,
455                                  MachineBasicBlock *&FBB,
456                                  SmallVectorImpl<MachineOperand> &Cond,
457                                  bool AllowModify) const
458{
459  // If the block has no terminators, it just falls into the block after it.
460  MachineBasicBlock::iterator I = MBB.end();
461  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
462    return false;
463
464  // Get the last instruction in the block.
465  MachineInstr *LastInst = I;
466
467  // If there is only one terminator instruction, process it.
468  unsigned LastOpc = LastInst->getOpcode();
469  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
470    if (!LastInst->getDesc().isBranch())
471      return true;
472
473    // Unconditional branch
474    if (LastOpc == Mips::J) {
475      TBB = LastInst->getOperand(0).getMBB();
476      return false;
477    }
478
479    Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
480    if (BranchCode == Mips::COND_INVALID)
481      return true;  // Can't handle indirect branch.
482
483    // Conditional branch
484    // Block ends with fall-through condbranch.
485    if (LastOpc != Mips::COND_INVALID) {
486      int LastNumOp = LastInst->getNumOperands();
487
488      TBB = LastInst->getOperand(LastNumOp-1).getMBB();
489      Cond.push_back(MachineOperand::CreateImm(BranchCode));
490
491      for (int i=0; i<LastNumOp-1; i++) {
492        Cond.push_back(LastInst->getOperand(i));
493      }
494
495      return false;
496    }
497  }
498
499  // Get the instruction before it if it is a terminator.
500  MachineInstr *SecondLastInst = I;
501
502  // If there are three terminators, we don't know what sort of block this is.
503  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
504    return true;
505
506  // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
507  unsigned SecondLastOpc    = SecondLastInst->getOpcode();
508  Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
509
510  if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
511    int SecondNumOp = SecondLastInst->getNumOperands();
512
513    TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
514    Cond.push_back(MachineOperand::CreateImm(BranchCode));
515
516    for (int i=0; i<SecondNumOp-1; i++) {
517      Cond.push_back(SecondLastInst->getOperand(i));
518    }
519
520    FBB = LastInst->getOperand(0).getMBB();
521    return false;
522  }
523
524  // If the block ends with two unconditional branches, handle it. The last
525  // one is not executed, so remove it.
526  if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
527    TBB = SecondLastInst->getOperand(0).getMBB();
528    I = LastInst;
529    if (AllowModify)
530      I->eraseFromParent();
531    return false;
532  }
533
534  // Otherwise, can't handle this.
535  return true;
536}
537
538unsigned MipsInstrInfo::
539InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
540             MachineBasicBlock *FBB,
541             const SmallVectorImpl<MachineOperand> &Cond) const {
542  // Shouldn't be a fall through.
543  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
544  assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
545         "Mips branch conditions can have two|three components!");
546
547  if (FBB == 0) { // One way branch.
548    if (Cond.empty()) {
549      // Unconditional branch?
550      BuildMI(&MBB, get(Mips::J)).addMBB(TBB);
551    } else {
552      // Conditional branch.
553      unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
554      const TargetInstrDesc &TID = get(Opc);
555
556      if (TID.getNumOperands() == 3)
557        BuildMI(&MBB, TID).addReg(Cond[1].getReg())
558                          .addReg(Cond[2].getReg())
559                          .addMBB(TBB);
560      else
561        BuildMI(&MBB, TID).addReg(Cond[1].getReg())
562                          .addMBB(TBB);
563
564    }
565    return 1;
566  }
567
568  // Two-way Conditional branch.
569  unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
570  const TargetInstrDesc &TID = get(Opc);
571
572  if (TID.getNumOperands() == 3)
573    BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
574                      .addMBB(TBB);
575  else
576    BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
577
578  BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
579  return 2;
580}
581
582unsigned MipsInstrInfo::
583RemoveBranch(MachineBasicBlock &MBB) const
584{
585  MachineBasicBlock::iterator I = MBB.end();
586  if (I == MBB.begin()) return 0;
587  --I;
588  if (I->getOpcode() != Mips::J &&
589      GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
590    return 0;
591
592  // Remove the branch.
593  I->eraseFromParent();
594
595  I = MBB.end();
596
597  if (I == MBB.begin()) return 1;
598  --I;
599  if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
600    return 1;
601
602  // Remove the branch.
603  I->eraseFromParent();
604  return 2;
605}
606
607/// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
608/// fall-through into its successor block.
609bool MipsInstrInfo::
610BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
611{
612  if (MBB.empty()) return false;
613
614  switch (MBB.back().getOpcode()) {
615  case Mips::RET:     // Return.
616  case Mips::JR:      // Indirect branch.
617  case Mips::J:       // Uncond branch.
618    return true;
619  default: return false;
620  }
621}
622
623/// ReverseBranchCondition - Return the inverse opcode of the
624/// specified Branch instruction.
625bool MipsInstrInfo::
626ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
627{
628  assert( (Cond.size() == 3 || Cond.size() == 2) &&
629          "Invalid Mips branch condition!");
630  Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
631  return false;
632}
633