MipsInstrInfo.cpp revision ea982789354af0d24ea55021a5fc2178d4647980
121ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===// 2edf128a7fa90f2b0b7ee24741a04a7ae1ecd6f7eMisha Brukman// 321ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner// The LLVM Compiler Infrastructure 421ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7edf128a7fa90f2b0b7ee24741a04a7ae1ecd6f7eMisha Brukman// 821ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner//===----------------------------------------------------------------------===// 921ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner// 1021ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner// This file contains the Mips implementation of the TargetInstrInfo class. 1121ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner// 1221ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner//===----------------------------------------------------------------------===// 1321ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner 1421ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner#include "MipsInstrInfo.h" 1521ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner#include "MipsTargetMachine.h" 1621ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner#include "MipsMachineFunction.h" 1721ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner#include "llvm/ADT/STLExtras.h" 1821ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner#include "llvm/CodeGen/MachineInstrBuilder.h" 19f10a56a86f8ae32d0493c7de770493d55519b073Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 20030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng#include "llvm/Support/ErrorHandling.h" 212c04dae715b05017d7d2c19ab4f8cb37c1e650aeBob Wilson#include "MipsGenInstrInfo.inc" 2221ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner 2344c3b9fdd416c79f4b67cde1aecfced5921efd81Jim Laskeyusing namespace llvm; 2421ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner 25c50ffcb7fcb7c1109fee2406e8f74d096f755f47Chris LattnerMipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm) 2669cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)), 2721ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 2821ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner 296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohmanstatic bool isZeroImm(const MachineOperand &op) { 3012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner return op.isImm() && op.getImm() == 0; 31f10a56a86f8ae32d0493c7de770493d55519b073Chris Lattner} 32c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin 333403bcd8f943cb053a7d9bbf8eb8135407699afaBill Wendling/// Return true if the instruction is a register to register move and 3480b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng/// leave the source and dest operands in the passed parameters. 352210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohmanbool MipsInstrInfo:: 3612143054aa6d120f029d268a5154bf2ecd0f707fChris LattnerisMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, 37551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer unsigned &SrcSubIdx, unsigned &DstSubIdx) const 38d41b30def3181bce4bf87e8bde664d15663165d0Jeff Cohen{ 3921ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner SrcSubIdx = DstSubIdx = 0; // No sub-registers. 4021ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner 41cd3245ac45c595da96bb768a55cddc356dff55feChris Lattner // addu $dst, $src, $zero || addu $dst, $zero, $src 42cd3245ac45c595da96bb768a55cddc356dff55feChris Lattner // or $dst, $src, $zero || or $dst, $zero, $src 43cd3245ac45c595da96bb768a55cddc356dff55feChris Lattner if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) { 447cd5d3e05ca9573dbac1a01846813037f901480cBob Wilson if (MI.getOperand(1).getReg() == Mips::ZERO) { 454e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman DstReg = MI.getOperand(0).getReg(); 4681da02b553b86868637f27b89c6e919c31ed5b51Dale Johannesen SrcReg = MI.getOperand(2).getReg(); 477cd5d3e05ca9573dbac1a01846813037f901480cBob Wilson return true; 48844731a7f1909f55935e3514c9e713a62d67662eDan Gohman } else if (MI.getOperand(2).getReg() == Mips::ZERO) { 49844731a7f1909f55935e3514c9e713a62d67662eDan Gohman DstReg = MI.getOperand(0).getReg(); 504e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman SrcReg = MI.getOperand(1).getReg(); 51844731a7f1909f55935e3514c9e713a62d67662eDan Gohman return true; 52622addbe49ffdc611adb315fb22756e23fe7b222Dale Johannesen } 531a90a5aebe3488dc3feaab60ba16bed1659ba27bDale Johannesen } 542210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman 552210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman // mov $fpDst, $fpSrc 562210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman // mfc $gpDst, $fpSrc 573cbc3120873242d93e469b4635c0bbd09fdb6438Bob Wilson // mtc $fpDst, $gpSrc 582210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman if (MI.getOpcode() == Mips::FMOV_S32 || 592210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman MI.getOpcode() == Mips::FMOV_D32 || 60794fd75c67a2cdc128d67342c6d88a504d186896Devang Patel MI.getOpcode() == Mips::MFC1 || 6172b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman MI.getOpcode() == Mips::MTC1 || 6272b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman MI.getOpcode() == Mips::MOVCCRToCCR) { 6372b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman DstReg = MI.getOperand(0).getReg(); 6472b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman SrcReg = MI.getOperand(1).getReg(); 6572b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman return true; 6672b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman } 6772b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman 6872b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman // addiu $dst, $src, 0 6972b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman if (MI.getOpcode() == Mips::ADDiu) { 7072b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) { 7172b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman DstReg = MI.getOperand(0).getReg(); 7272b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman SrcReg = MI.getOperand(1).getReg(); 7372b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman return true; 7472b2990a7495b9df89e151eb711c1e7abdd5f2e5Dan Gohman } 75030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng } 7621ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner 777cc253e3b85b27540bbc91b8331e06e7a65fbc4cDan Gohman return false; 78a597103c328e29fb763e7a4864bd7c29a588fc9dBob Wilson} 79030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng 80030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng/// isLoadFromStackSlot - If the specified machine instruction is a direct 81030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng/// load from a stack slot, return the virtual or physical register number of 82030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng/// the destination along with the FrameIndex of the loaded stack slot. If 83030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng/// not, return 0. This predicate must return 0 if the instruction has 84030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng/// any side effects other than loading from the stack slot. 85030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Chengunsigned MipsInstrInfo:: 86030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan ChengisLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const 87030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng{ 88030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) || 89a597103c328e29fb763e7a4864bd7c29a588fc9dBob Wilson (MI->getOpcode() == Mips::LDC1)) { 90030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng if ((MI->getOperand(2).isFI()) && // is a stack slot 91030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng (MI->getOperand(1).isImm()) && // the imm is zero 92030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng (isZeroImm(MI->getOperand(1)))) { 93030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng FrameIndex = MI->getOperand(2).getIndex(); 94030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng return MI->getOperand(0).getReg(); 95b3c27428969b3cc52ab8493e91b5dd1465325fedEvan Cheng } 9621ab22e47592d8a4046cfdac844d76b2cb76d711Chris Lattner } 97c50ffcb7fcb7c1109fee2406e8f74d096f755f47Chris Lattner 98c50ffcb7fcb7c1109fee2406e8f74d096f755f47Chris Lattner return 0; 99683747abb81a7b7711ad6cb5abf5a4227f7ab691Chris Lattner} 100033c9715d9bf7ce59ad2e466bf0720811b34da08Jim Laskey 101465e2b950d61c870fb3120c80191973e8282a3efDavid Greene/// isStoreToStackSlot - If the specified machine instruction is a direct 1024e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman/// store to a stack slot, return the virtual or physical register number of 103c50ffcb7fcb7c1109fee2406e8f74d096f755f47Chris Lattner/// the source reg along with the FrameIndex of the loaded stack slot. If 104c50ffcb7fcb7c1109fee2406e8f74d096f755f47Chris Lattner/// not, return 0. This predicate must return 0 if the instruction has 105c50ffcb7fcb7c1109fee2406e8f74d096f755f47Chris Lattner/// any side effects other than storing to the stack slot. 106c50ffcb7fcb7c1109fee2406e8f74d096f755f47Chris Lattnerunsigned MipsInstrInfo:: 1074e3f125e184f96ae72f2c44d16cafe0d44158283Dan GohmanisStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const 10868d4d1d49c813d10047ad116e897a17d67112c10Duncan Sands{ 10968d4d1d49c813d10047ad116e897a17d67112c10Duncan Sands if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) || 11044c3b9fdd416c79f4b67cde1aecfced5921efd81Jim Laskey (MI->getOpcode() == Mips::SDC1)) { 111683747abb81a7b7711ad6cb5abf5a4227f7ab691Chris Lattner if ((MI->getOperand(2).isFI()) && // is a stack slot 112683747abb81a7b7711ad6cb5abf5a4227f7ab691Chris Lattner (MI->getOperand(1).isImm()) && // the imm is zero 11368d4d1d49c813d10047ad116e897a17d67112c10Duncan Sands (isZeroImm(MI->getOperand(1)))) { 114683747abb81a7b7711ad6cb5abf5a4227f7ab691Chris Lattner FrameIndex = MI->getOperand(2).getIndex(); 11544c3b9fdd416c79f4b67cde1aecfced5921efd81Jim Laskey return MI->getOperand(0).getReg(); 116683747abb81a7b7711ad6cb5abf5a4227f7ab691Chris Lattner } 117683747abb81a7b7711ad6cb5abf5a4227f7ab691Chris Lattner } 1184e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman return 0; 119c50ffcb7fcb7c1109fee2406e8f74d096f755f47Chris Lattner} 1208e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman 121c50ffcb7fcb7c1109fee2406e8f74d096f755f47Chris Lattner/// insertNoop - If data hazard condition is found insert the target nop 122c50ffcb7fcb7c1109fee2406e8f74d096f755f47Chris Lattner/// instruction. 12380b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Chengvoid MipsInstrInfo:: 12480b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan ChenginsertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const 12580b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng{ 12680b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng DebugLoc DL = DebugLoc::getUnknownLoc(); 12780b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng if (MI != MBB.end()) DL = MI->getDebugLoc(); 12880b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng BuildMI(MBB, MI, DL, get(Mips::NOP)); 12980b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng} 13080b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng 13180b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Chengbool MipsInstrInfo:: 13280b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan ChengcopyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 13380b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng unsigned DestReg, unsigned SrcReg, 13480b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng const TargetRegisterClass *DestRC, 13580b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng const TargetRegisterClass *SrcRC) const { 136518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner DebugLoc DL = DebugLoc::getUnknownLoc(); 13780b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng 13880b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng if (I != MBB.end()) DL = I->getDebugLoc(); 13980b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng 140030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng if (DestRC != SrcRC) { 14180b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng 14280b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng // Copy to/from FCR31 condition register 14380b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng if ((DestRC == Mips::CPURegsRegisterClass) && 14480b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng (SrcRC == Mips::CCRRegisterClass)) 14580b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg); 14680b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng else if ((DestRC == Mips::CCRRegisterClass) && 14780b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng (SrcRC == Mips::CPURegsRegisterClass)) 14880b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg); 14980b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng 15080b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng // Moves between coprocessors and cpu 15180b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng else if ((DestRC == Mips::CPURegsRegisterClass) && 15280b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng (SrcRC == Mips::FGR32RegisterClass)) 15380b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg); 15480b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng else if ((DestRC == Mips::FGR32RegisterClass) && 155d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman (SrcRC == Mips::CPURegsRegisterClass)) 15680b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg); 15780b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng 15880b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng // Move from/to Hi/Lo registers 15980b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng else if ((DestRC == Mips::HILORegisterClass) && 16080b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng (SrcRC == Mips::CPURegsRegisterClass)) { 16180b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO; 16280b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng BuildMI(MBB, I, DL, get(Opc), DestReg); 16380b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng } else if ((SrcRC == Mips::HILORegisterClass) && 16480b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng (DestRC == Mips::CPURegsRegisterClass)) { 16580b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO; 16680b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng BuildMI(MBB, I, DL, get(Opc), DestReg); 16780b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng } else 16880b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng // Can't copy this register 16980b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng return false; 17080b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng 17180b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng return true; 17280b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng } 17380b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng 174030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng if (DestRC == Mips::CPURegsRegisterClass) 175030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) 176030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng .addReg(SrcReg); 177030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng else if (DestRC == Mips::FGR32RegisterClass) 178030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg); 179030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng else if (DestRC == Mips::AFGR64RegisterClass) 180030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg); 181030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng else if (DestRC == Mips::CCRRegisterClass) 182030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg); 183030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng else 184030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng // Can't copy this register 1857821a8afd3009c3c2760592e61de9e2c31c73e18Chris Lattner return false; 186030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng 18780b09fe8bc1d2755ef9a6b03b8862a657db42f06Evan Cheng return true; 18814ba0cc42959a3fcc9b6781aea614b01877fb55fDale Johannesen} 189030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng 19014ba0cc42959a3fcc9b6781aea614b01877fb55fDale Johannesenvoid MipsInstrInfo:: 19114ba0cc42959a3fcc9b6781aea614b01877fb55fDale JohannesenstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 19244eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson unsigned SrcReg, bool isKill, int FI, 193dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng const TargetRegisterClass *RC) const { 194030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng DebugLoc DL = DebugLoc::getUnknownLoc(); 195030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng if (I != MBB.end()) DL = I->getDebugLoc(); 19614ba0cc42959a3fcc9b6781aea614b01877fb55fDale Johannesen 19714ba0cc42959a3fcc9b6781aea614b01877fb55fDale Johannesen if (RC == Mips::CPURegsRegisterClass) 19812143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill)) 19912143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner .addImm(0).addFrameIndex(FI); 20012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner else if (RC == Mips::FGR32RegisterClass) 20112143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill)) 20212143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner .addImm(0).addFrameIndex(FI); 203030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng else if (RC == Mips::AFGR64RegisterClass) { 20412143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner if (!TM.getSubtarget<MipsSubtarget>().isMips1()) { 20512143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner BuildMI(MBB, I, DL, get(Mips::SDC1)) 2066acfe12dd6d52c801f78c240528b7cb42fa91159Chris Lattner .addReg(SrcReg, getKillRegState(isKill)) 2076acfe12dd6d52c801f78c240528b7cb42fa91159Chris Lattner .addImm(0).addFrameIndex(FI); 2086acfe12dd6d52c801f78c240528b7cb42fa91159Chris Lattner } else { 209071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner const TargetRegisterInfo *TRI = 210071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner MBB.getParent()->getTarget().getRegisterInfo(); 211071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner const unsigned *SubSet = TRI->getSubRegisters(SrcReg); 212071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner BuildMI(MBB, I, DL, get(Mips::SWC1)) 213071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner .addReg(SubSet[0], getKillRegState(isKill)) 2146acfe12dd6d52c801f78c240528b7cb42fa91159Chris Lattner .addImm(0).addFrameIndex(FI); 215071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner BuildMI(MBB, I, DL, get(Mips::SWC1)) 216071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner .addReg(SubSet[1], getKillRegState(isKill)) 217071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner .addImm(4).addFrameIndex(FI); 218071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner } 219071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner } else 220071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner llvm_unreachable("Register class not handled!"); 221071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner} 222071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner 223071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattnervoid MipsInstrInfo:: 224071c62fad0b25ad4131e7f984173a796c1e63f61Chris LattnerloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 225071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner unsigned DestReg, int FI, 226071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner const TargetRegisterClass *RC) const 227071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner{ 228071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner DebugLoc DL = DebugLoc::getUnknownLoc(); 229071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner if (I != MBB.end()) DL = I->getDebugLoc(); 2304e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman 231071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner if (RC == Mips::CPURegsRegisterClass) 232071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI); 233071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner else if (RC == Mips::FGR32RegisterClass) 234071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI); 235071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner else if (RC == Mips::AFGR64RegisterClass) { 236071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner if (!TM.getSubtarget<MipsSubtarget>().isMips1()) { 237071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI); 238071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner } else { 239071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner const TargetRegisterInfo *TRI = 240071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner MBB.getParent()->getTarget().getRegisterInfo(); 241071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner const unsigned *SubSet = TRI->getSubRegisters(DestReg); 242071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0]) 243071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner .addImm(0).addFrameIndex(FI); 244071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1]) 245071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner .addImm(4).addFrameIndex(FI); 246071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner } 2476acfe12dd6d52c801f78c240528b7cb42fa91159Chris Lattner } else 2486acfe12dd6d52c801f78c240528b7cb42fa91159Chris Lattner llvm_unreachable("Register class not handled!"); 249030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng} 250071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner 251071c62fad0b25ad4131e7f984173a796c1e63f61Chris LattnerMachineInstr *MipsInstrInfo:: 252071c62fad0b25ad4131e7f984173a796c1e63f61Chris LattnerfoldMemoryOperandImpl(MachineFunction &MF, 253071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner MachineInstr* MI, 254071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner const SmallVectorImpl<unsigned> &Ops, int FI) const 255071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner{ 256071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner if (Ops.size() != 1) return NULL; 257071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner 258071c62fad0b25ad4131e7f984173a796c1e63f61Chris Lattner MachineInstr *NewMI = NULL; 25969cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen 260030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng switch (MI->getOpcode()) { 26112143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::ADDu: 26212143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner if ((MI->getOperand(0).isReg()) && 26312143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner (MI->getOperand(1).isReg()) && 26412143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner (MI->getOperand(1).getReg() == Mips::ZERO) && 26512143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner (MI->getOperand(2).isReg())) { 26612143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner if (Ops[0] == 0) { // COPY -> STORE 26712143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner unsigned SrcReg = MI->getOperand(2).getReg(); 26812143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner bool isKill = MI->getOperand(2).isKill(); 26912143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner bool isUndef = MI->getOperand(2).isUndef(); 27012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW)) 27112143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 2724e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman .addImm(0).addFrameIndex(FI); 27312143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner } else { // COPY -> LOAD 27412143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner unsigned DstReg = MI->getOperand(0).getReg(); 27512143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner bool isDead = MI->getOperand(0).isDead(); 27612143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner bool isUndef = MI->getOperand(0).isUndef(); 27712143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW)) 27812143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner .addReg(DstReg, RegState::Define | getDeadRegState(isDead) | 2798aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner getUndefRegState(isUndef)) 28012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner .addImm(0).addFrameIndex(FI); 2818aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner } 28212143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner } 28312143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner break; 2848aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner case Mips::FMOV_S32: 28512143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FMOV_D32: 28612143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner if ((MI->getOperand(0).isReg()) && 28712143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner (MI->getOperand(1).isReg())) { 28812143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner const TargetRegisterClass 28912143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner *RC = RI.getRegClass(MI->getOperand(0).getReg()); 29012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner unsigned StoreOpc, LoadOpc; 29112143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner bool IsMips1 = TM.getSubtarget<MipsSubtarget>().isMips1(); 29212143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner 29312143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner if (RC == Mips::FGR32RegisterClass) { 2944e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1; 29512143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner } else { 29612143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner assert(RC == Mips::AFGR64RegisterClass); 29712143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner // Mips1 doesn't have ldc/sdc instructions. 29812143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner if (IsMips1) break; 29912143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1; 3007aea8320340ce867eb4328aeec52cb02c88ef0b3Dale Johannesen } 3014e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman 3024e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman if (Ops[0] == 0) { // COPY -> STORE 3037aea8320340ce867eb4328aeec52cb02c88ef0b3Dale Johannesen unsigned SrcReg = MI->getOperand(1).getReg(); 3047aea8320340ce867eb4328aeec52cb02c88ef0b3Dale Johannesen bool isKill = MI->getOperand(1).isKill(); 3057aea8320340ce867eb4328aeec52cb02c88ef0b3Dale Johannesen bool isUndef = MI->getOperand(2).isUndef(); 3067aea8320340ce867eb4328aeec52cb02c88ef0b3Dale Johannesen NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc)) 3077aea8320340ce867eb4328aeec52cb02c88ef0b3Dale Johannesen .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 30812143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner .addImm(0).addFrameIndex(FI) ; 30912143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner } else { // COPY -> LOAD 31012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner unsigned DstReg = MI->getOperand(0).getReg(); 3114e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman bool isDead = MI->getOperand(0).isDead(); 31212143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner bool isUndef = MI->getOperand(0).isUndef(); 31384839daa595968286acd25644820c644867f0c52Dale Johannesen NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc)) 31484839daa595968286acd25644820c644867f0c52Dale Johannesen .addReg(DstReg, RegState::Define | getDeadRegState(isDead) | 31584839daa595968286acd25644820c644867f0c52Dale Johannesen getUndefRegState(isUndef)) 31684839daa595968286acd25644820c644867f0c52Dale Johannesen .addImm(0).addFrameIndex(FI); 31784839daa595968286acd25644820c644867f0c52Dale Johannesen } 31884839daa595968286acd25644820c644867f0c52Dale Johannesen } 31912143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner break; 3204e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman } 3217aea8320340ce867eb4328aeec52cb02c88ef0b3Dale Johannesen 32212143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner return NewMI; 3234e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman} 32412143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner 32584839daa595968286acd25644820c644867f0c52Dale Johannesen//===----------------------------------------------------------------------===// 32684839daa595968286acd25644820c644867f0c52Dale Johannesen// Branch Analysis 32784839daa595968286acd25644820c644867f0c52Dale Johannesen//===----------------------------------------------------------------------===// 32884839daa595968286acd25644820c644867f0c52Dale Johannesen 32984839daa595968286acd25644820c644867f0c52Dale Johannesen/// GetCondFromBranchOpc - Return the Mips CC that matches 33012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner/// the correspondent Branch instruction opcode. 33112143054aa6d120f029d268a5154bf2ecd0f707fChris Lattnerstatic Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc) 33212143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner{ 33312143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner switch (BrOpc) { 33412143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner default: return Mips::COND_INVALID; 33512143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::BEQ : return Mips::COND_E; 33612143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::BNE : return Mips::COND_NE; 33712143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::BGTZ : return Mips::COND_GZ; 33812143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::BGEZ : return Mips::COND_GEZ; 33912143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::BLTZ : return Mips::COND_LZ; 34012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::BLEZ : return Mips::COND_LEZ; 34112143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner 34212143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner // We dont do fp branch analysis yet! 34312143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::BC1T : 3444e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman case Mips::BC1F : return Mips::COND_INVALID; 34512143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner } 34612143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner} 34712143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner 34884839daa595968286acd25644820c644867f0c52Dale Johannesen/// GetCondBranchFromCond - Return the Branch instruction 34984839daa595968286acd25644820c644867f0c52Dale Johannesen/// opcode that matches the cc. 350c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesenunsigned Mips::GetCondBranchFromCond(Mips::CondCode CC) 351c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen{ 352c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen switch (CC) { 353c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen default: llvm_unreachable("Illegal condition code!"); 354c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::COND_E : return Mips::BEQ; 355c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::COND_NE : return Mips::BNE; 356c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::COND_GZ : return Mips::BGTZ; 357c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::COND_GEZ : return Mips::BGEZ; 358c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::COND_LZ : return Mips::BLTZ; 35984839daa595968286acd25644820c644867f0c52Dale Johannesen case Mips::COND_LEZ : return Mips::BLEZ; 360c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen 36184839daa595968286acd25644820c644867f0c52Dale Johannesen case Mips::FCOND_F: 36284839daa595968286acd25644820c644867f0c52Dale Johannesen case Mips::FCOND_UN: 363c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_EQ: 36484839daa595968286acd25644820c644867f0c52Dale Johannesen case Mips::FCOND_UEQ: 365c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_OLT: 366c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_ULT: 367c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_OLE: 36884839daa595968286acd25644820c644867f0c52Dale Johannesen case Mips::FCOND_ULE: 369c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_SF: 37084839daa595968286acd25644820c644867f0c52Dale Johannesen case Mips::FCOND_NGLE: 37184839daa595968286acd25644820c644867f0c52Dale Johannesen case Mips::FCOND_SEQ: 372c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_NGL: 37384839daa595968286acd25644820c644867f0c52Dale Johannesen case Mips::FCOND_LT: 374da6efc5268958a0668806e989c1c5a1f788543e5Bill Wendling case Mips::FCOND_NGE: 3750713a224234b4596709c7582ebf17a1ccb95c872Bill Wendling case Mips::FCOND_LE: 3760713a224234b4596709c7582ebf17a1ccb95c872Bill Wendling case Mips::FCOND_NGT: return Mips::BC1T; 3770713a224234b4596709c7582ebf17a1ccb95c872Bill Wendling 3780713a224234b4596709c7582ebf17a1ccb95c872Bill Wendling case Mips::FCOND_T: 379518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner case Mips::FCOND_OR: 38012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_NEQ: 38112143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_OGL: 38212143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_UGE: 38312143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_OGE: 38412143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_UGT: 385c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_OGT: 386c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_ST: 387c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_GLE: 388c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_SNE: 389c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_GL: 390c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_NLT: 391c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_GE: 392c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_NLE: 393c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::FCOND_GT: return Mips::BC1F; 394c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen } 395c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen} 396c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen 397c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen/// GetOppositeBranchCondition - Return the inverse of the specified 398c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen/// condition, e.g. turning COND_E to COND_NE. 399c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale JohannesenMips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC) 400c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen{ 401c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen switch (CC) { 402c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen default: llvm_unreachable("Illegal condition code!"); 403c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::COND_E : return Mips::COND_NE; 404c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::COND_NE : return Mips::COND_E; 405c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::COND_GZ : return Mips::COND_LEZ; 406c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::COND_GEZ : return Mips::COND_LZ; 407c5cf227f3dac755508928b9dee8ac6a45dcb4e4fDale Johannesen case Mips::COND_LZ : return Mips::COND_GEZ; 40812143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::COND_LEZ : return Mips::COND_GZ; 40912143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_F : return Mips::FCOND_T; 41012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_UN : return Mips::FCOND_OR; 41112143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_EQ : return Mips::FCOND_NEQ; 412386e29065db5b05b57440f6b2a6dfa1e7f29a00dChris Lattner case Mips::FCOND_UEQ: return Mips::FCOND_OGL; 413386e29065db5b05b57440f6b2a6dfa1e7f29a00dChris Lattner case Mips::FCOND_OLT: return Mips::FCOND_UGE; 41412143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_ULT: return Mips::FCOND_OGE; 41512143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_OLE: return Mips::FCOND_UGT; 41612143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_ULE: return Mips::FCOND_OGT; 4174e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman case Mips::FCOND_SF: return Mips::FCOND_ST; 41812143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_NGLE:return Mips::FCOND_GLE; 41912143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_SEQ: return Mips::FCOND_SNE; 42012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_NGL: return Mips::FCOND_GL; 4214e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman case Mips::FCOND_LT: return Mips::FCOND_NLT; 42212143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_NGE: return Mips::FCOND_GE; 42312143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_LE: return Mips::FCOND_NLE; 42412143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner case Mips::FCOND_NGT: return Mips::FCOND_GT; 425386e29065db5b05b57440f6b2a6dfa1e7f29a00dChris Lattner } 426386e29065db5b05b57440f6b2a6dfa1e7f29a00dChris Lattner} 4271501cdbf63cff3afd92df6cd249096770334b268Dan Gohman 42812143054aa6d120f029d268a5154bf2ecd0f707fChris Lattnerbool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 42912143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner MachineBasicBlock *&TBB, 43012143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner MachineBasicBlock *&FBB, 43112143054aa6d120f029d268a5154bf2ecd0f707fChris Lattner SmallVectorImpl<MachineOperand> &Cond, 4321d08d83230338ca5969ff6ae6737a978336538bfChris Lattner bool AllowModify) const 4331d08d83230338ca5969ff6ae6737a978336538bfChris Lattner{ 4341d08d83230338ca5969ff6ae6737a978336538bfChris Lattner // If the block has no terminators, it just falls into the block after it. 4351d08d83230338ca5969ff6ae6737a978336538bfChris Lattner MachineBasicBlock::iterator I = MBB.end(); 4361d08d83230338ca5969ff6ae6737a978336538bfChris Lattner if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) 4378e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman return false; 4388e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman 4391d08d83230338ca5969ff6ae6737a978336538bfChris Lattner // Get the last instruction in the block. 4401d08d83230338ca5969ff6ae6737a978336538bfChris Lattner MachineInstr *LastInst = I; 4418e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman 4428e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman // If there is only one terminator instruction, process it. 4431d08d83230338ca5969ff6ae6737a978336538bfChris Lattner unsigned LastOpc = LastInst->getOpcode(); 4441d08d83230338ca5969ff6ae6737a978336538bfChris Lattner if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 44504478e56f736325d3567e7c0efe2bb5c2766c63bDan Gohman if (!LastInst->getDesc().isBranch()) 4464e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman return true; 4471d08d83230338ca5969ff6ae6737a978336538bfChris Lattner 4481d08d83230338ca5969ff6ae6737a978336538bfChris Lattner // Unconditional branch 4494e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman if (LastOpc == Mips::J) { 4501d08d83230338ca5969ff6ae6737a978336538bfChris Lattner TBB = LastInst->getOperand(0).getMBB(); 4511d08d83230338ca5969ff6ae6737a978336538bfChris Lattner return false; 45269cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen } 45369cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen 45469cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 45569cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen if (BranchCode == Mips::COND_INVALID) 45669cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen return true; // Can't handle indirect branch. 45769cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen 458030a0a0cdb38924e55773a8e0b5fe7347aa664aaEvan Cheng // Conditional branch 45969cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen // Block ends with fall-through condbranch. 4608520149db158427339a235a74dd2cc19553a7328Dan Gohman if (LastOpc != Mips::COND_INVALID) { 46169cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen int LastNumOp = LastInst->getNumOperands(); 46269cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen 46369cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen TBB = LastInst->getOperand(LastNumOp-1).getMBB(); 46469cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen Cond.push_back(MachineOperand::CreateImm(BranchCode)); 4651d08d83230338ca5969ff6ae6737a978336538bfChris Lattner 4661d08d83230338ca5969ff6ae6737a978336538bfChris Lattner for (int i=0; i<LastNumOp-1; i++) { 4671d08d83230338ca5969ff6ae6737a978336538bfChris Lattner Cond.push_back(LastInst->getOperand(i)); 468d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner } 469d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner 470d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner return false; 47169244300b8a0112efb44b6273ecea4ca6264b8cfChris Lattner } 472d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner } 473d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner 474b0812f114b83a32c4b90a4b553c7177c557558b5Dale Johannesen // Get the instruction before it if it is a terminator. 475b0812f114b83a32c4b90a4b553c7177c557558b5Dale Johannesen MachineInstr *SecondLastInst = I; 476749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner 477749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner // If there are three terminators, we don't know what sort of block this is. 478d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 47941474baac839da410302950305722cb0e026a094Dan Gohman return true; 480d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner 481d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it. 482d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner unsigned SecondLastOpc = SecondLastInst->getOpcode(); 483d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); 484d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner 485d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) { 486d4bf3c2fd60975b30cd067b59f743a3ea45e45b5Chris Lattner int SecondNumOp = SecondLastInst->getNumOperands(); 48776b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen 48876b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB(); 48976b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen Cond.push_back(MachineOperand::CreateImm(BranchCode)); 49076b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen 491d34f5d91bc6fdc55085d3c4d509c778d6bcc5f0aBob Wilson for (int i=0; i<SecondNumOp-1; i++) { 49276b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen Cond.push_back(SecondLastInst->getOperand(i)); 49376b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen } 4947896c9f436a4eda5ec15e882a7505ba482a2fcd0Chris Lattner 49576b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen FBB = LastInst->getOperand(0).getMBB(); 49644eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson return false; 49776b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen } 498dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng 49976b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen // If the block ends with two unconditional branches, handle it. The last 5006b8583cbf1f8a3df5ae859d3da2ca690ff57f91cDale Johannesen // one is not executed, so remove it. 50176b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) { 50276b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen TBB = SecondLastInst->getOperand(0).getMBB(); 50376b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen I = LastInst; 50476b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen if (AllowModify) 50576b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen I->eraseFromParent(); 50676b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen return false; 50776b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen } 5081501cdbf63cff3afd92df6cd249096770334b268Dan Gohman 50976b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen // Otherwise, can't handle this. 51076b38fcabeba725e166a2ff72c56fe31d784b229Dale Johannesen return true; 511ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman} 512ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman 513ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohmanunsigned MipsInstrInfo:: 514ffe644ebf4dcc50b314261ddd2d08c841f629349Dan GohmanInsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 515ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman MachineBasicBlock *FBB, 516ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman const SmallVectorImpl<MachineOperand> &Cond) const { 517ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman // FIXME this should probably have a DebugLoc argument 518ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman DebugLoc dl = DebugLoc::getUnknownLoc(); 519ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman // Shouldn't be a fall through. 520ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 521ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) && 522ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman "Mips branch conditions can have two|three components!"); 523ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman 52497b4ac8c844e08ce1c4f4a73b85ba56775a2a6c5Duncan Sands if (FBB == 0) { // One way branch. 525ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman if (Cond.empty()) { 52667fcdf7f6579fcc070f019096cedf80d5a834554David Greene // Unconditional branch? 527ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB); 528ffe644ebf4dcc50b314261ddd2d08c841f629349Dan Gohman } else { 52995ef406e0f2da0197f8b46849319c07e9bea1e55Dale Johannesen // Conditional branch. 53095ef406e0f2da0197f8b46849319c07e9bea1e55Dale Johannesen unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm()); 5312210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman const TargetInstrDesc &TID = get(Opc); 5322210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman 5332210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman if (TID.getNumOperands() == 3) 5342210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()) 5352210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman .addReg(Cond[2].getReg()) 5362210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman .addMBB(TBB); 5372210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman else 5382210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()) 5392210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman .addMBB(TBB); 5402210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman 5412210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman } 5422210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman return 1; 5432210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman } 5442210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman 5452210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman // Two-way Conditional branch. 5462210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm()); 5472210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman const TargetInstrDesc &TID = get(Opc); 5482210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman 5492210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman if (TID.getNumOperands() == 3) 5507b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg()) 5517b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson .addMBB(TBB); 5527b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson else 5537b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB); 5547b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson 5557b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB); 5567b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson return 2; 5577b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson} 5587b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson 5592210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohmanunsigned MipsInstrInfo:: 5602210c0bea83aa8a8585d793a1f63e8c01b65be38Dan GohmanRemoveBranch(MachineBasicBlock &MBB) const 5612210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman{ 5627b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson MachineBasicBlock::iterator I = MBB.end(); 5637b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson if (I == MBB.begin()) return 0; 5647b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson --I; 5657b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson if (I->getOpcode() != Mips::J && 5667b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID) 5677b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson return 0; 5682210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman 5692210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman // Remove the branch. 5702210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman I->eraseFromParent(); 5712210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman 5722210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman I = MBB.end(); 5732210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman 5742210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman if (I == MBB.begin()) return 1; 5752210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman --I; 5762210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID) 577ad6af45dc172fe23801771200eabb6a7f764e2cbDan Gohman return 1; 578ad6af45dc172fe23801771200eabb6a7f764e2cbDan Gohman 579ad6af45dc172fe23801771200eabb6a7f764e2cbDan Gohman // Remove the branch. 580ad6af45dc172fe23801771200eabb6a7f764e2cbDan Gohman I->eraseFromParent(); 581ad6af45dc172fe23801771200eabb6a7f764e2cbDan Gohman return 2; 582ad6af45dc172fe23801771200eabb6a7f764e2cbDan Gohman} 583ad6af45dc172fe23801771200eabb6a7f764e2cbDan Gohman 584ad6af45dc172fe23801771200eabb6a7f764e2cbDan Gohman/// ReverseBranchCondition - Return the inverse opcode of the 585ad6af45dc172fe23801771200eabb6a7f764e2cbDan Gohman/// specified Branch instruction. 5862210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohmanbool MipsInstrInfo:: 587c4c550c7584b3240bda71d4339ec49c1cf731d55Dan GohmanReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 588c4c550c7584b3240bda71d4339ec49c1cf731d55Dan Gohman{ 589c4c550c7584b3240bda71d4339ec49c1cf731d55Dan Gohman assert( (Cond.size() == 3 || Cond.size() == 2) && 5903cbc3120873242d93e469b4635c0bbd09fdb6438Bob Wilson "Invalid Mips branch condition!"); 5912210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm())); 5922210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman return false; 593c4c550c7584b3240bda71d4339ec49c1cf731d55Dan Gohman} 5942210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman 5952210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman/// getGlobalBaseReg - Return a virtual register initialized with the 596c4c550c7584b3240bda71d4339ec49c1cf731d55Dan Gohman/// the global base register value. Output instructions required to 5972210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman/// initialize the register in the function entry block, if necessary. 5982210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman/// 599c4c550c7584b3240bda71d4339ec49c1cf731d55Dan Gohmanunsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 600c4c550c7584b3240bda71d4339ec49c1cf731d55Dan Gohman MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>(); 601c4c550c7584b3240bda71d4339ec49c1cf731d55Dan Gohman unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg(); 602c4c550c7584b3240bda71d4339ec49c1cf731d55Dan Gohman if (GlobalBaseReg != 0) 603c4c550c7584b3240bda71d4339ec49c1cf731d55Dan Gohman return GlobalBaseReg; 604c4c550c7584b3240bda71d4339ec49c1cf731d55Dan Gohman 6057b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson // Insert the set of GlobalBaseReg into the first MBB of the function 6067b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson MachineBasicBlock &FirstMBB = MF->front(); 6077b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 6087b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson MachineRegisterInfo &RegInfo = MF->getRegInfo(); 6097b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 6107b888b8ad07cccec099634bc838eed5da3f336b1Bob Wilson 6116b8583cbf1f8a3df5ae859d3da2ca690ff57f91cDale Johannesen GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass); 6124e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP, 6136b8583cbf1f8a3df5ae859d3da2ca690ff57f91cDale Johannesen Mips::CPURegsRegisterClass, 6146b8583cbf1f8a3df5ae859d3da2ca690ff57f91cDale Johannesen Mips::CPURegsRegisterClass); 6154e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman assert(Ok && "Couldn't assign to global base register!"); 6164e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman Ok = Ok; // Silence warning when assertions are turned off. 6176b8583cbf1f8a3df5ae859d3da2ca690ff57f91cDale Johannesen RegInfo.addLiveIn(Mips::GP); 6186b8583cbf1f8a3df5ae859d3da2ca690ff57f91cDale Johannesen 6196b8583cbf1f8a3df5ae859d3da2ca690ff57f91cDale Johannesen MipsFI->setGlobalBaseReg(GlobalBaseReg); 6206b8583cbf1f8a3df5ae859d3da2ca690ff57f91cDale Johannesen return GlobalBaseReg; 6214e3f125e184f96ae72f2c44d16cafe0d44158283Dan Gohman} 6222210c0bea83aa8a8585d793a1f63e8c01b65be38Dan Gohman