MipsInstrInfo.h revision 564f69072c4569e2d603c335a6ddc61adf94ebb2 
1//===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSINSTRUCTIONINFO_H
15#define MIPSINSTRUCTIONINFO_H
16
17#include "Mips.h"
18#include "MipsRegisterInfo.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22#define GET_INSTRINFO_HEADER
23#include "MipsGenInstrInfo.inc"
24
25namespace llvm {
26
27namespace Mips {
28  /// GetOppositeBranchOpc - Return the inverse of the specified
29  /// opcode, e.g. turning BEQ to BNE.
30  unsigned GetOppositeBranchOpc(unsigned Opc);
31}
32
33class MipsInstrInfo : public MipsGenInstrInfo {
34  MipsTargetMachine &TM;
35  bool IsN64;
36  const MipsRegisterInfo RI;
37  unsigned UncondBrOpc;
38public:
39  explicit MipsInstrInfo(MipsTargetMachine &TM);
40
41  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
42  /// such, whenever a client has an instance of instruction info, it should
43  /// always be able to get register info as well (through this method).
44  ///
45  virtual const MipsRegisterInfo &getRegisterInfo() const;
46
47  /// isLoadFromStackSlot - If the specified machine instruction is a direct
48  /// load from a stack slot, return the virtual or physical register number of
49  /// the destination along with the FrameIndex of the loaded stack slot.  If
50  /// not, return 0.  This predicate must return 0 if the instruction has
51  /// any side effects other than loading from the stack slot.
52  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
53                                       int &FrameIndex) const;
54
55  /// isStoreToStackSlot - If the specified machine instruction is a direct
56  /// store to a stack slot, return the virtual or physical register number of
57  /// the source reg along with the FrameIndex of the loaded stack slot.  If
58  /// not, return 0.  This predicate must return 0 if the instruction has
59  /// any side effects other than storing to the stack slot.
60  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
61                                      int &FrameIndex) const;
62
63  /// Branch Analysis
64  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
65                             MachineBasicBlock *&FBB,
66                             SmallVectorImpl<MachineOperand> &Cond,
67                             bool AllowModify) const;
68  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
69
70private:
71  void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
72                   const SmallVectorImpl<MachineOperand>& Cond) const;
73  void ExpandExtractElementF64(MachineBasicBlock &MBB,
74                               MachineBasicBlock::iterator I) const;
75  void ExpandBuildPairF64(MachineBasicBlock &MBB,
76                          MachineBasicBlock::iterator I) const;
77
78public:
79  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
80                                MachineBasicBlock *FBB,
81                                const SmallVectorImpl<MachineOperand> &Cond,
82                                DebugLoc DL) const;
83  virtual void copyPhysReg(MachineBasicBlock &MBB,
84                           MachineBasicBlock::iterator MI, DebugLoc DL,
85                           unsigned DestReg, unsigned SrcReg,
86                           bool KillSrc) const;
87  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
88                                   MachineBasicBlock::iterator MBBI,
89                                   unsigned SrcReg, bool isKill, int FrameIndex,
90                                   const TargetRegisterClass *RC,
91                                   const TargetRegisterInfo *TRI) const;
92
93  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
94                                    MachineBasicBlock::iterator MBBI,
95                                    unsigned DestReg, int FrameIndex,
96                                    const TargetRegisterClass *RC,
97                                    const TargetRegisterInfo *TRI) const;
98
99  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
100
101  virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
102                                                 int FrameIx, uint64_t Offset,
103                                                 const MDNode *MDPtr,
104                                                 DebugLoc DL) const;
105
106  virtual
107  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
108
109  /// Insert nop instruction when hazard condition is found
110  virtual void insertNoop(MachineBasicBlock &MBB,
111                          MachineBasicBlock::iterator MI) const;
112};
113
114}
115
116#endif
117