MipsInstrInfo.h revision 8e8b8a223c2b0e69f44c0639f846260c8011668f 
1//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSINSTRUCTIONINFO_H
15#define MIPSINSTRUCTIONINFO_H
16
17#include "Mips.h"
18#include "llvm/Target/TargetInstrInfo.h"
19#include "MipsRegisterInfo.h"
20
21namespace llvm {
22
23namespace Mips {
24
25  // Mips Branch Codes
26  enum FPBranchCode {
27    BRANCH_F,
28    BRANCH_T,
29    BRANCH_FL,
30    BRANCH_TL,
31    BRANCH_INVALID
32  };
33
34  // Mips Condition Codes
35  enum CondCode {
36    // To be used with float branch True
37    FCOND_F,
38    FCOND_UN,
39    FCOND_EQ,
40    FCOND_UEQ,
41    FCOND_OLT,
42    FCOND_ULT,
43    FCOND_OLE,
44    FCOND_ULE,
45    FCOND_SF,
46    FCOND_NGLE,
47    FCOND_SEQ,
48    FCOND_NGL,
49    FCOND_LT,
50    FCOND_NGE,
51    FCOND_LE,
52    FCOND_NGT,
53
54    // To be used with float branch False
55    // This conditions have the same mnemonic as the
56    // above ones, but are used with a branch False;
57    FCOND_T,
58    FCOND_OR,
59    FCOND_NEQ,
60    FCOND_OGL,
61    FCOND_UGE,
62    FCOND_OGE,
63    FCOND_UGT,
64    FCOND_OGT,
65    FCOND_ST,
66    FCOND_GLE,
67    FCOND_SNE,
68    FCOND_GL,
69    FCOND_NLT,
70    FCOND_GE,
71    FCOND_NLE,
72    FCOND_GT,
73
74    // Only integer conditions
75    COND_E,
76    COND_GZ,
77    COND_GEZ,
78    COND_LZ,
79    COND_LEZ,
80    COND_NE,
81    COND_INVALID
82  };
83
84  // Turn condition code into conditional branch opcode.
85  unsigned GetCondBranchFromCond(CondCode CC);
86
87  /// GetOppositeBranchCondition - Return the inverse of the specified cond,
88  /// e.g. turning COND_E to COND_NE.
89  CondCode GetOppositeBranchCondition(Mips::CondCode CC);
90
91  /// MipsCCToString - Map each FP condition code to its string
92  inline static const char *MipsFCCToString(Mips::CondCode CC)
93  {
94    switch (CC) {
95      default: assert(0 && "Unknown condition code");
96      case FCOND_F:
97      case FCOND_T:   return "f";
98      case FCOND_UN:
99      case FCOND_OR:  return "un";
100      case FCOND_EQ:
101      case FCOND_NEQ: return "eq";
102      case FCOND_UEQ:
103      case FCOND_OGL: return "ueq";
104      case FCOND_OLT:
105      case FCOND_UGE: return "olt";
106      case FCOND_ULT:
107      case FCOND_OGE: return "ult";
108      case FCOND_OLE:
109      case FCOND_UGT: return "ole";
110      case FCOND_ULE:
111      case FCOND_OGT: return "ule";
112      case FCOND_SF:
113      case FCOND_ST:  return "sf";
114      case FCOND_NGLE:
115      case FCOND_GLE: return "ngle";
116      case FCOND_SEQ:
117      case FCOND_SNE: return "seq";
118      case FCOND_NGL:
119      case FCOND_GL:  return "ngl";
120      case FCOND_LT:
121      case FCOND_NLT: return "lt";
122      case FCOND_NGE:
123      case FCOND_GE:  return "ge";
124      case FCOND_LE:
125      case FCOND_NLE: return "nle";
126      case FCOND_NGT:
127      case FCOND_GT:  return "gt";
128    }
129  }
130}
131
132class MipsInstrInfo : public TargetInstrInfoImpl {
133  MipsTargetMachine &TM;
134  const MipsRegisterInfo RI;
135public:
136  explicit MipsInstrInfo(MipsTargetMachine &TM);
137
138  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
139  /// such, whenever a client has an instance of instruction info, it should
140  /// always be able to get register info as well (through this method).
141  ///
142  virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
143
144  /// Return true if the instruction is a register to register move and
145  /// leave the source and dest operands in the passed parameters.
146  ///
147  virtual bool isMoveInstr(const MachineInstr &MI,
148                           unsigned &SrcReg, unsigned &DstReg) const;
149
150  /// isLoadFromStackSlot - If the specified machine instruction is a direct
151  /// load from a stack slot, return the virtual or physical register number of
152  /// the destination along with the FrameIndex of the loaded stack slot.  If
153  /// not, return 0.  This predicate must return 0 if the instruction has
154  /// any side effects other than loading from the stack slot.
155  virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
156
157  /// isStoreToStackSlot - If the specified machine instruction is a direct
158  /// store to a stack slot, return the virtual or physical register number of
159  /// the source reg along with the FrameIndex of the loaded stack slot.  If
160  /// not, return 0.  This predicate must return 0 if the instruction has
161  /// any side effects other than storing to the stack slot.
162  virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
163
164  /// Branch Analysis
165  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
166                             MachineBasicBlock *&FBB,
167                             SmallVectorImpl<MachineOperand> &Cond) const;
168  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
169  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
170                                MachineBasicBlock *FBB,
171                            const SmallVectorImpl<MachineOperand> &Cond) const;
172  virtual bool copyRegToReg(MachineBasicBlock &MBB,
173                            MachineBasicBlock::iterator I,
174                            unsigned DestReg, unsigned SrcReg,
175                            const TargetRegisterClass *DestRC,
176                            const TargetRegisterClass *SrcRC) const;
177  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
178                                   MachineBasicBlock::iterator MBBI,
179                                   unsigned SrcReg, bool isKill, int FrameIndex,
180                                   const TargetRegisterClass *RC) const;
181
182  virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
183                              SmallVectorImpl<MachineOperand> &Addr,
184                              const TargetRegisterClass *RC,
185                              SmallVectorImpl<MachineInstr*> &NewMIs) const;
186
187  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
188                                    MachineBasicBlock::iterator MBBI,
189                                    unsigned DestReg, int FrameIndex,
190                                    const TargetRegisterClass *RC) const;
191
192  virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
193                               SmallVectorImpl<MachineOperand> &Addr,
194                               const TargetRegisterClass *RC,
195                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
196
197  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
198                                          MachineInstr* MI,
199                                          const SmallVectorImpl<unsigned> &Ops,
200                                          int FrameIndex) const;
201
202  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
203                                          MachineInstr* MI,
204                                          const SmallVectorImpl<unsigned> &Ops,
205                                          MachineInstr* LoadMI) const {
206    return 0;
207  }
208
209  virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
210  virtual
211  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
212
213  /// Insert nop instruction when hazard condition is found
214  virtual void insertNoop(MachineBasicBlock &MBB,
215                          MachineBasicBlock::iterator MI) const;
216};
217
218}
219
220#endif
221