PPCISelLowering.h revision 43c6e7cd9b0d9a3b0006650ddfac256848f10d51
1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that PPC uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "PPC.h" 21#include "PPCSubtarget.h" 22 23namespace llvm { 24 namespace PPCISD { 25 enum NodeType { 26 // Start the numbering where the builtin ops and target ops leave off. 27 FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END, 28 29 /// FSEL - Traditional three-operand fsel node. 30 /// 31 FSEL, 32 33 /// FCFID - The FCFID instruction, taking an f64 operand and producing 34 /// and f64 value containing the FP representation of the integer that 35 /// was temporarily in the f64 operand. 36 FCFID, 37 38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 39 /// operand, producing an f64 value containing the integer representation 40 /// of that FP value. 41 FCTIDZ, FCTIWZ, 42 43 /// STFIWX - The STFIWX instruction. The first operand is an input token 44 /// chain, then an f64 value to store, then an address to store it to, 45 /// then a SRCVALUE for the address. 46 STFIWX, 47 48 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 49 // three v4f32 operands and producing a v4f32 result. 50 VMADDFP, VNMSUBFP, 51 52 /// VPERM - The PPC VPERM Instruction. 53 /// 54 VPERM, 55 56 /// Hi/Lo - These represent the high and low 16-bit parts of a global 57 /// address respectively. These nodes have two operands, the first of 58 /// which must be a TargetGlobalAddress, and the second of which must be a 59 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 60 /// though these are usually folded into other nodes. 61 Hi, Lo, 62 63 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 64 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 65 /// compute an allocation on the stack. 66 DYNALLOC, 67 68 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 69 /// at function entry, used for PIC code. 70 GlobalBaseReg, 71 72 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 73 /// shift amounts. These nodes are generated by the multi-precision shift 74 /// code. 75 SRL, SRA, SHL, 76 77 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" 78 /// registers. 79 EXTSW_32, 80 81 /// STD_32 - This is the STD instruction for use with "32-bit" registers. 82 STD_32, 83 84 /// CALL - A direct function call. 85 CALL_Macho, CALL_ELF, 86 87 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 88 /// MTCTR instruction. 89 MTCTR, 90 91 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 92 /// BCTRL instruction. 93 BCTRL_Macho, BCTRL_ELF, 94 95 /// Return with a flag operand, matched by 'blr' 96 RET_FLAG, 97 98 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions. 99 /// This copies the bits corresponding to the specified CRREG into the 100 /// resultant GPR. Bits corresponding to other CR regs are undefined. 101 MFCR, 102 103 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 104 /// instructions. For lack of better number, we use the opcode number 105 /// encoding for the OPC field to identify the compare. For example, 838 106 /// is VCMPGTSH. 107 VCMP, 108 109 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 110 /// altivec VCMP*o instructions. For lack of better number, we use the 111 /// opcode number encoding for the OPC field to identify the compare. For 112 /// example, 838 is VCMPGTSH. 113 VCMPo, 114 115 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 116 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 117 /// condition register to branch on, OPC is the branch opcode to use (e.g. 118 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 119 /// an optional input flag argument. 120 COND_BRANCH, 121 122 /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a 123 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 124 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 125 /// i32. 126 STBRX, 127 128 /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a 129 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 130 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 131 /// or i32. 132 LBRX 133 }; 134 } 135 136 /// Define some predicates that are used for node matching. 137 namespace PPC { 138 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 139 /// VPKUHUM instruction. 140 bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary); 141 142 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 143 /// VPKUWUM instruction. 144 bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary); 145 146 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 147 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 148 bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 149 150 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 151 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 152 bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 153 154 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 155 /// amount, otherwise return -1. 156 int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 157 158 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 159 /// specifies a splat of a single element that is suitable for input to 160 /// VSPLTB/VSPLTH/VSPLTW. 161 bool isSplatShuffleMask(SDNode *N, unsigned EltSize); 162 163 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 164 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 165 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 166 167 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 168 /// formed by using a vspltis[bhw] instruction of the specified element 169 /// size, return the constant being splatted. The ByteSize field indicates 170 /// the number of bytes of each element [124] -> [bhw]. 171 SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 172 } 173 174 class PPCTargetLowering : public TargetLowering { 175 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 176 int ReturnAddrIndex; // FrameIndex for return slot. 177 const PPCSubtarget &PPCSubTarget; 178 public: 179 PPCTargetLowering(PPCTargetMachine &TM); 180 181 /// getTargetNodeName() - This method returns the name of a target specific 182 /// DAG node. 183 virtual const char *getTargetNodeName(unsigned Opcode) const; 184 185 /// getPreIndexedAddressParts - returns true by value, base pointer and 186 /// offset pointer and addressing mode by reference if the node's address 187 /// can be legally represented as pre-indexed load / store address. 188 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 189 SDOperand &Offset, 190 ISD::MemIndexedMode &AM, 191 SelectionDAG &DAG); 192 193 /// SelectAddressRegReg - Given the specified addressed, check to see if it 194 /// can be represented as an indexed [r+r] operation. Returns false if it 195 /// can be more efficiently represented with [r+imm]. 196 bool SelectAddressRegReg(SDOperand N, SDOperand &Base, SDOperand &Index, 197 SelectionDAG &DAG); 198 199 /// SelectAddressRegImm - Returns true if the address N can be represented 200 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 201 /// is not better represented as reg+reg. 202 bool SelectAddressRegImm(SDOperand N, SDOperand &Disp, SDOperand &Base, 203 SelectionDAG &DAG); 204 205 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 206 /// represented as an indexed [r+r] operation. 207 bool SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, SDOperand &Index, 208 SelectionDAG &DAG); 209 210 /// SelectAddressRegImmShift - Returns true if the address N can be 211 /// represented by a base register plus a signed 14-bit displacement 212 /// [r+imm*4]. Suitable for use by STD and friends. 213 bool SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base, 214 SelectionDAG &DAG); 215 216 217 /// LowerOperation - Provide custom lowering hooks for some operations. 218 /// 219 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 220 221 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 222 223 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 224 uint64_t Mask, 225 uint64_t &KnownZero, 226 uint64_t &KnownOne, 227 unsigned Depth = 0) const; 228 229 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 230 MachineBasicBlock *MBB); 231 232 ConstraintType getConstraintType(char ConstraintLetter) const; 233 std::pair<unsigned, const TargetRegisterClass*> 234 getRegForInlineAsmConstraint(const std::string &Constraint, 235 MVT::ValueType VT) const; 236 SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter, 237 SelectionDAG &DAG); 238 239 /// isLegalAddressImmediate - Return true if the integer value can be used 240 /// as the offset of the target addressing mode. 241 virtual bool isLegalAddressImmediate(int64_t V) const; 242 virtual bool isLegalAddressImmediate(llvm::GlobalValue*) const; 243 244 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG); 245 }; 246} 247 248#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 249