PPCISelLowering.h revision ef819f8fbb68793cc21396fcc1563ec481dacb2f 
1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that PPC uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
17
18#include "llvm/Target/TargetLowering.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "PPC.h"
21
22namespace llvm {
23  namespace PPCISD {
24    enum NodeType {
25      // Start the numbering where the builting ops and target ops leave off.
26      FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
27
28      /// FSEL - Traditional three-operand fsel node.
29      ///
30      FSEL,
31
32      /// FCFID - The FCFID instruction, taking an f64 operand and producing
33      /// and f64 value containing the FP representation of the integer that
34      /// was temporarily in the f64 operand.
35      FCFID,
36
37      /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
38      /// operand, producing an f64 value containing the integer representation
39      /// of that FP value.
40      FCTIDZ, FCTIWZ,
41
42      /// STFIWX - The STFIWX instruction.  The first operand is an input token
43      /// chain, then an f64 value to store, then an address to store it to,
44      /// then a SRCVALUE for the address.
45      STFIWX,
46
47      // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48      // three v4f32 operands and producing a v4f32 result.
49      VMADDFP, VNMSUBFP,
50
51      /// LVE_X - The PPC LVE*X instructions.  The size of the element loaded is
52      /// the size of the element type of the vector result.  The element loaded
53      /// depends on the alignment of the input pointer.
54      ///
55      /// The first operand is a token chain, the second is the address to load
56      /// the third is the SRCVALUE node.
57      LVE_X,
58
59      /// VPERM - The PPC VPERM Instruction.
60      ///
61      VPERM,
62
63      /// Hi/Lo - These represent the high and low 16-bit parts of a global
64      /// address respectively.  These nodes have two operands, the first of
65      /// which must be a TargetGlobalAddress, and the second of which must be a
66      /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
67      /// though these are usually folded into other nodes.
68      Hi, Lo,
69
70      /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
71      /// at function entry, used for PIC code.
72      GlobalBaseReg,
73
74      /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
75      /// shift amounts.  These nodes are generated by the multi-precision shift
76      /// code.
77      SRL, SRA, SHL,
78
79      /// CALL - A function call.
80      CALL,
81
82      /// Return with a flag operand, matched by 'blr'
83      RET_FLAG,
84    };
85  }
86
87  /// Define some predicates that are used for node matching.
88  namespace PPC {
89    /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
90    /// specifies a splat of a single element that is suitable for input to
91    /// VSPLTB/VSPLTH/VSPLTW.
92    bool isSplatShuffleMask(SDNode *N);
93
94    /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
95    /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
96    unsigned getVSPLTImmediate(SDNode *N);
97  }
98
99  class PPCTargetLowering : public TargetLowering {
100    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
101    int ReturnAddrIndex;              // FrameIndex for return slot.
102  public:
103    PPCTargetLowering(TargetMachine &TM);
104
105    /// getTargetNodeName() - This method returns the name of a target specific
106    /// DAG node.
107    virtual const char *getTargetNodeName(unsigned Opcode) const;
108
109    /// LowerOperation - Provide custom lowering hooks for some operations.
110    ///
111    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
112
113    virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
114
115    /// LowerArguments - This hook must be implemented to indicate how we should
116    /// lower the arguments for the specified function, into the specified DAG.
117    virtual std::vector<SDOperand>
118      LowerArguments(Function &F, SelectionDAG &DAG);
119
120    /// LowerCallTo - This hook lowers an abstract call to a function into an
121    /// actual call.
122    virtual std::pair<SDOperand, SDOperand>
123      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
124                  unsigned CC,
125                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
126                  SelectionDAG &DAG);
127
128    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
129                                                       MachineBasicBlock *MBB);
130
131    ConstraintType getConstraintType(char ConstraintLetter) const;
132    std::vector<unsigned>
133      getRegClassForInlineAsmConstraint(const std::string &Constraint,
134                                        MVT::ValueType VT) const;
135    bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
136
137    /// isLegalAddressImmediate - Return true if the integer value can be used
138    /// as the offset of the target addressing mode.
139    virtual bool isLegalAddressImmediate(int64_t V) const;
140  };
141}
142
143#endif   // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
144