PPCISelLowering.h revision f28f8bc40eedc6304ab25dd8bed486fa08f51f70
1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that PPC uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "PPC.h" 21#include "PPCSubtarget.h" 22 23namespace llvm { 24 namespace PPCISD { 25 enum NodeType { 26 // Start the numbering where the builtin ops and target ops leave off. 27 FIRST_NUMBER = ISD::BUILTIN_OP_END, 28 29 /// FSEL - Traditional three-operand fsel node. 30 /// 31 FSEL, 32 33 /// FCFID - The FCFID instruction, taking an f64 operand and producing 34 /// and f64 value containing the FP representation of the integer that 35 /// was temporarily in the f64 operand. 36 FCFID, 37 38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 39 /// operand, producing an f64 value containing the integer representation 40 /// of that FP value. 41 FCTIDZ, FCTIWZ, 42 43 /// STFIWX - The STFIWX instruction. The first operand is an input token 44 /// chain, then an f64 value to store, then an address to store it to. 45 STFIWX, 46 47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 48 // three v4f32 operands and producing a v4f32 result. 49 VMADDFP, VNMSUBFP, 50 51 /// VPERM - The PPC VPERM Instruction. 52 /// 53 VPERM, 54 55 /// Hi/Lo - These represent the high and low 16-bit parts of a global 56 /// address respectively. These nodes have two operands, the first of 57 /// which must be a TargetGlobalAddress, and the second of which must be a 58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 59 /// though these are usually folded into other nodes. 60 Hi, Lo, 61 62 TOC_ENTRY, 63 64 /// The following three target-specific nodes are used for calls through 65 /// function pointers in the 64-bit SVR4 ABI. 66 67 /// Restore the TOC from the TOC save area of the current stack frame. 68 /// This is basically a hard coded load instruction which additionally 69 /// takes/produces a flag. 70 TOC_RESTORE, 71 72 /// Like a regular LOAD but additionally taking/producing a flag. 73 LOAD, 74 75 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is 76 /// a hard coded load instruction. 77 LOAD_TOC, 78 79 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 80 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 81 /// compute an allocation on the stack. 82 DYNALLOC, 83 84 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 85 /// at function entry, used for PIC code. 86 GlobalBaseReg, 87 88 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 89 /// shift amounts. These nodes are generated by the multi-precision shift 90 /// code. 91 SRL, SRA, SHL, 92 93 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" 94 /// registers. 95 EXTSW_32, 96 97 /// CALL - A direct function call. 98 CALL_Darwin, CALL_SVR4, 99 100 /// NOP - Special NOP which follows 64-bit SVR4 calls. 101 NOP, 102 103 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 104 /// MTCTR instruction. 105 MTCTR, 106 107 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 108 /// BCTRL instruction. 109 BCTRL_Darwin, BCTRL_SVR4, 110 111 /// Return with a flag operand, matched by 'blr' 112 RET_FLAG, 113 114 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions. 115 /// This copies the bits corresponding to the specified CRREG into the 116 /// resultant GPR. Bits corresponding to other CR regs are undefined. 117 MFCR, 118 119 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 120 /// instructions. For lack of better number, we use the opcode number 121 /// encoding for the OPC field to identify the compare. For example, 838 122 /// is VCMPGTSH. 123 VCMP, 124 125 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 126 /// altivec VCMP*o instructions. For lack of better number, we use the 127 /// opcode number encoding for the OPC field to identify the compare. For 128 /// example, 838 is VCMPGTSH. 129 VCMPo, 130 131 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 132 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 133 /// condition register to branch on, OPC is the branch opcode to use (e.g. 134 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 135 /// an optional input flag argument. 136 COND_BRANCH, 137 138 // The following 5 instructions are used only as part of the 139 // long double-to-int conversion sequence. 140 141 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the 142 /// register. 143 MFFS, 144 145 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR. 146 MTFSB0, 147 148 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR. 149 MTFSB1, 150 151 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with 152 /// rounding towards zero. It has flags added so it won't move past the 153 /// FPSCR-setting instructions. 154 FADDRTZ, 155 156 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR. 157 MTFSF, 158 159 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 160 /// reserve indexed. This is used to implement atomic operations. 161 LARX, 162 163 /// STCX = This corresponds to PPC stcx. instrcution: store conditional 164 /// indexed. This is used to implement atomic operations. 165 STCX, 166 167 /// TC_RETURN - A tail call return. 168 /// operand #0 chain 169 /// operand #1 callee (register or absolute) 170 /// operand #2 stack adjustment 171 /// operand #3 optional in flag 172 TC_RETURN, 173 174 /// STD_32 - This is the STD instruction for use with "32-bit" registers. 175 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE, 176 177 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 178 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 179 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 180 /// i32. 181 STBRX, 182 183 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 184 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 185 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 186 /// or i32. 187 LBRX 188 }; 189 } 190 191 /// Define some predicates that are used for node matching. 192 namespace PPC { 193 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 194 /// VPKUHUM instruction. 195 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 196 197 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 198 /// VPKUWUM instruction. 199 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 200 201 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 202 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 203 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 204 bool isUnary); 205 206 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 207 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 208 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 209 bool isUnary); 210 211 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 212 /// amount, otherwise return -1. 213 int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 214 215 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 216 /// specifies a splat of a single element that is suitable for input to 217 /// VSPLTB/VSPLTH/VSPLTW. 218 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 219 220 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 221 /// are -0.0. 222 bool isAllNegativeZeroVector(SDNode *N); 223 224 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 225 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 226 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 227 228 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 229 /// formed by using a vspltis[bhw] instruction of the specified element 230 /// size, return the constant being splatted. The ByteSize field indicates 231 /// the number of bytes of each element [124] -> [bhw]. 232 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 233 } 234 235 class PPCTargetLowering : public TargetLowering { 236 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 237 int VarArgsStackOffset; // StackOffset for start of stack 238 // arguments. 239 unsigned VarArgsNumGPR; // Index of the first unused integer 240 // register for parameter passing. 241 unsigned VarArgsNumFPR; // Index of the first unused double 242 // register for parameter passing. 243 const PPCSubtarget &PPCSubTarget; 244 public: 245 explicit PPCTargetLowering(PPCTargetMachine &TM); 246 247 /// getTargetNodeName() - This method returns the name of a target specific 248 /// DAG node. 249 virtual const char *getTargetNodeName(unsigned Opcode) const; 250 251 /// getSetCCResultType - Return the ISD::SETCC ValueType 252 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 253 254 /// getPreIndexedAddressParts - returns true by value, base pointer and 255 /// offset pointer and addressing mode by reference if the node's address 256 /// can be legally represented as pre-indexed load / store address. 257 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 258 SDValue &Offset, 259 ISD::MemIndexedMode &AM, 260 SelectionDAG &DAG) const; 261 262 /// SelectAddressRegReg - Given the specified addressed, check to see if it 263 /// can be represented as an indexed [r+r] operation. Returns false if it 264 /// can be more efficiently represented with [r+imm]. 265 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 266 SelectionDAG &DAG) const; 267 268 /// SelectAddressRegImm - Returns true if the address N can be represented 269 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 270 /// is not better represented as reg+reg. 271 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 272 SelectionDAG &DAG) const; 273 274 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 275 /// represented as an indexed [r+r] operation. 276 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 277 SelectionDAG &DAG) const; 278 279 /// SelectAddressRegImmShift - Returns true if the address N can be 280 /// represented by a base register plus a signed 14-bit displacement 281 /// [r+imm*4]. Suitable for use by STD and friends. 282 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base, 283 SelectionDAG &DAG) const; 284 285 286 /// LowerOperation - Provide custom lowering hooks for some operations. 287 /// 288 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 289 290 /// ReplaceNodeResults - Replace the results of node with an illegal result 291 /// type with new values built out of custom code. 292 /// 293 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 294 SelectionDAG &DAG); 295 296 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 297 298 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 299 const APInt &Mask, 300 APInt &KnownZero, 301 APInt &KnownOne, 302 const SelectionDAG &DAG, 303 unsigned Depth = 0) const; 304 305 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 306 MachineBasicBlock *MBB, 307 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 308 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 309 MachineBasicBlock *MBB, bool is64Bit, 310 unsigned BinOpcode) const; 311 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 312 MachineBasicBlock *MBB, 313 bool is8bit, unsigned Opcode) const; 314 315 ConstraintType getConstraintType(const std::string &Constraint) const; 316 std::pair<unsigned, const TargetRegisterClass*> 317 getRegForInlineAsmConstraint(const std::string &Constraint, 318 EVT VT) const; 319 320 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 321 /// function arguments in the caller parameter area. This is the actual 322 /// alignment, not its logarithm. 323 unsigned getByValTypeAlignment(const Type *Ty) const; 324 325 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 326 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 327 /// true it means one of the asm constraint of the inline asm instruction 328 /// being processed is 'm'. 329 virtual void LowerAsmOperandForConstraint(SDValue Op, 330 char ConstraintLetter, 331 bool hasMemory, 332 std::vector<SDValue> &Ops, 333 SelectionDAG &DAG) const; 334 335 /// isLegalAddressingMode - Return true if the addressing mode represented 336 /// by AM is legal for this target, for a load/store of the specified type. 337 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 338 339 /// isLegalAddressImmediate - Return true if the integer value can be used 340 /// as the offset of the target addressing mode for load / store of the 341 /// given type. 342 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const; 343 344 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as 345 /// the offset of the target addressing mode. 346 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 347 348 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 349 350 /// getOptimalMemOpType - Returns the target specific optimal type for load 351 /// and store operations as a result of memset, memcpy, and memmove 352 /// lowering. If DstAlign is zero that means it's safe to destination 353 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 354 /// means there isn't a need to check it against alignment requirement, 355 /// probably because the source does not need to be loaded. If 356 /// 'NonScalarIntSafe' is true, that means it's safe to return a 357 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 358 /// from memory. It returns EVT::Other if SelectionDAG should be responsible 359 /// for determining it. 360 virtual EVT 361 getOptimalMemOpType(uint64_t Size, 362 unsigned DstAlign, unsigned SrcAlign, 363 bool NonScalarIntSafe, SelectionDAG &DAG) const; 364 365 /// getFunctionAlignment - Return the Log2 alignment of this function. 366 virtual unsigned getFunctionAlignment(const Function *F) const; 367 368 private: 369 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 370 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 371 372 bool 373 IsEligibleForTailCallOptimization(SDValue Callee, 374 CallingConv::ID CalleeCC, 375 bool isVarArg, 376 const SmallVectorImpl<ISD::InputArg> &Ins, 377 SelectionDAG& DAG) const; 378 379 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 380 int SPDiff, 381 SDValue Chain, 382 SDValue &LROpOut, 383 SDValue &FPOpOut, 384 bool isDarwinABI, 385 DebugLoc dl); 386 387 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); 388 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 389 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); 390 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); 391 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); 392 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 393 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); 394 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); 395 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); 396 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 397 int VarArgsFrameIndex, int VarArgsStackOffset, 398 unsigned VarArgsNumGPR, unsigned VarArgsNumFPR, 399 const PPCSubtarget &Subtarget); 400 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex, 401 int VarArgsStackOffset, unsigned VarArgsNumGPR, 402 unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget); 403 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 404 const PPCSubtarget &Subtarget); 405 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 406 const PPCSubtarget &Subtarget); 407 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); 408 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl); 409 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); 410 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); 411 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG); 412 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG); 413 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG); 414 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); 415 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); 416 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 417 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); 418 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG); 419 420 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 421 CallingConv::ID CallConv, bool isVarArg, 422 const SmallVectorImpl<ISD::InputArg> &Ins, 423 DebugLoc dl, SelectionDAG &DAG, 424 SmallVectorImpl<SDValue> &InVals); 425 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall, 426 bool isVarArg, 427 SelectionDAG &DAG, 428 SmallVector<std::pair<unsigned, SDValue>, 8> 429 &RegsToPass, 430 SDValue InFlag, SDValue Chain, 431 SDValue &Callee, 432 int SPDiff, unsigned NumBytes, 433 const SmallVectorImpl<ISD::InputArg> &Ins, 434 SmallVectorImpl<SDValue> &InVals); 435 436 virtual SDValue 437 LowerFormalArguments(SDValue Chain, 438 CallingConv::ID CallConv, bool isVarArg, 439 const SmallVectorImpl<ISD::InputArg> &Ins, 440 DebugLoc dl, SelectionDAG &DAG, 441 SmallVectorImpl<SDValue> &InVals); 442 443 virtual SDValue 444 LowerCall(SDValue Chain, SDValue Callee, 445 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 446 const SmallVectorImpl<ISD::OutputArg> &Outs, 447 const SmallVectorImpl<ISD::InputArg> &Ins, 448 DebugLoc dl, SelectionDAG &DAG, 449 SmallVectorImpl<SDValue> &InVals); 450 451 virtual SDValue 452 LowerReturn(SDValue Chain, 453 CallingConv::ID CallConv, bool isVarArg, 454 const SmallVectorImpl<ISD::OutputArg> &Outs, 455 DebugLoc dl, SelectionDAG &DAG); 456 457 SDValue 458 LowerFormalArguments_Darwin(SDValue Chain, 459 CallingConv::ID CallConv, bool isVarArg, 460 const SmallVectorImpl<ISD::InputArg> &Ins, 461 DebugLoc dl, SelectionDAG &DAG, 462 SmallVectorImpl<SDValue> &InVals); 463 SDValue 464 LowerFormalArguments_SVR4(SDValue Chain, 465 CallingConv::ID CallConv, bool isVarArg, 466 const SmallVectorImpl<ISD::InputArg> &Ins, 467 DebugLoc dl, SelectionDAG &DAG, 468 SmallVectorImpl<SDValue> &InVals); 469 470 SDValue 471 LowerCall_Darwin(SDValue Chain, SDValue Callee, 472 CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 473 const SmallVectorImpl<ISD::OutputArg> &Outs, 474 const SmallVectorImpl<ISD::InputArg> &Ins, 475 DebugLoc dl, SelectionDAG &DAG, 476 SmallVectorImpl<SDValue> &InVals); 477 SDValue 478 LowerCall_SVR4(SDValue Chain, SDValue Callee, 479 CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 480 const SmallVectorImpl<ISD::OutputArg> &Outs, 481 const SmallVectorImpl<ISD::InputArg> &Ins, 482 DebugLoc dl, SelectionDAG &DAG, 483 SmallVectorImpl<SDValue> &InVals); 484 }; 485} 486 487#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 488