PPCInstrInfo.h revision 2da8bc8a5f7705ac131184cd247f48500da0d74e
1c16257f05391b8aeccef62d6b543f1cb5a8185feChris Lattner//===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// The LLVM Compiler Infrastructure 4f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 9f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 10f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// This file contains the PowerPC implementation of the TargetInstrInfo class. 11f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 12f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 13f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 14f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#ifndef POWERPC32_INSTRUCTIONINFO_H 15f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#define POWERPC32_INSTRUCTIONINFO_H 16f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 172668959b8879097db368aec7d76c455260abc75bChris Lattner#include "PPC.h" 18617742b1b8b7fbb07b4ab5db7c292bff78d709f6Chris Lattner#include "llvm/Target/TargetInstrInfo.h" 1916e71f2f70811c69c56052dd146324fe20e31db5Chris Lattner#include "PPCRegisterInfo.h" 20f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 21f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukmannamespace llvm { 2288d211f82304e53694ece666d4a2507b170e4582Chris Lattner 2388d211f82304e53694ece666d4a2507b170e4582Chris Lattner/// PPCII - This namespace holds all of the PowerPC target-specific 2488d211f82304e53694ece666d4a2507b170e4582Chris Lattner/// per-instruction flags. These must match the corresponding definitions in 2588d211f82304e53694ece666d4a2507b170e4582Chris Lattner/// PPC.td and PPCInstrFormats.td. 2688d211f82304e53694ece666d4a2507b170e4582Chris Lattnernamespace PPCII { 2788d211f82304e53694ece666d4a2507b170e4582Chris Lattnerenum { 2888d211f82304e53694ece666d4a2507b170e4582Chris Lattner // PPC970 Instruction Flags. These flags describe the characteristics of the 2988d211f82304e53694ece666d4a2507b170e4582Chris Lattner // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 3088d211f82304e53694ece666d4a2507b170e4582Chris Lattner // raw machine instructions. 3188d211f82304e53694ece666d4a2507b170e4582Chris Lattner 3288d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// PPC970_First - This instruction starts a new dispatch group, so it will 3388d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// always be the first one in the group. 3488d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_First = 0x1, 356e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 3688d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// PPC970_Single - This instruction starts a new dispatch group and 3788d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// terminates it, so it will be the sole instruction in the group. 3888d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_Single = 0x2, 3988d211f82304e53694ece666d4a2507b170e4582Chris Lattner 40fd97734f3636f54a86890918096d3d692df0b939Chris Lattner /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 41fd97734f3636f54a86890918096d3d692df0b939Chris Lattner /// two dispatch pipes to be available to issue. 42fd97734f3636f54a86890918096d3d692df0b939Chris Lattner PPC970_Cracked = 0x4, 436e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 4488d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 4588d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// an instruction is issued to. 46fd97734f3636f54a86890918096d3d692df0b939Chris Lattner PPC970_Shift = 3, 47d74ea2bbd8bb630331f35ead42d385249bd42af8Chris Lattner PPC970_Mask = 0x07 << PPC970_Shift 4888d211f82304e53694ece666d4a2507b170e4582Chris Lattner}; 4988d211f82304e53694ece666d4a2507b170e4582Chris Lattnerenum PPC970_Unit { 5088d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// These are the various PPC970 execution unit pipelines. Each instruction 5188d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// is one of these. 5288d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 5388d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 5488d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 5588d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 5688d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 5788d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 5888d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 59d74ea2bbd8bb630331f35ead42d385249bd42af8Chris Lattner PPC970_BRU = 7 << PPC970_Shift // Branch Unit 6088d211f82304e53694ece666d4a2507b170e4582Chris Lattner}; 61b908258d59745ab9f150c66f94541951cf9c9211Chris Lattner} // end namespace PPCII 626e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 636e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 64641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerclass PPCInstrInfo : public TargetInstrInfoImpl { 65b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner PPCTargetMachine &TM; 6621e463b2bf864671a87ebe386cb100ef9349a540Nate Begeman const PPCRegisterInfo RI; 674a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling 688e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman bool StoreRegToStackSlot(MachineFunction &MF, 698e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman unsigned SrcReg, bool isKill, int FrameIdx, 704a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling const TargetRegisterClass *RC, 714a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling SmallVectorImpl<MachineInstr*> &NewMIs) const; 726e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick void LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 738e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman unsigned DestReg, int FrameIdx, 744a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling const TargetRegisterClass *RC, 754a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling SmallVectorImpl<MachineInstr*> &NewMIs) const; 76f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukmanpublic: 77950a4c40b823cd4f09dc71be635229246dfd6cacDan Gohman explicit PPCInstrInfo(PPCTargetMachine &TM); 78f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 79f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 80f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman /// such, whenever a client has an instance of instruction info, it should 81f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman /// always be able to get register info as well (through this method). 82f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman /// 83c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6Dan Gohman virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; } 84f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 852da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick ScheduleHazardRecognizer * 862da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick CreateTargetHazardRecognizer(const TargetMachine *TM, 872da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const; 882da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 89cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman unsigned isLoadFromStackSlot(const MachineInstr *MI, 90cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const; 91cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman unsigned isStoreToStackSlot(const MachineInstr *MI, 92cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const; 93408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 94043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // commuteInstruction - We can commute rlwimi instructions, but only if the 95043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // rotate amt is zero. We also have to munge the immediates a bit. 9658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 976e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 986e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick virtual void insertNoop(MachineBasicBlock &MBB, 99bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner MachineBasicBlock::iterator MI) const; 100bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner 101c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 102c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Branch analysis. 103c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 104c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock *&FBB, 105dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 106dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify) const; 107b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 108b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 109b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng MachineBasicBlock *FBB, 1103bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 1113bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const; 11227689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen virtual void copyPhysReg(MachineBasicBlock &MBB, 11327689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 11427689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 11527689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen bool KillSrc) const; 1166e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 117f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 118f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MBBI, 119f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIndex, 120746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 121746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const; 122f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 123f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 124f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MBBI, 125f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIndex, 126746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 127746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const; 1286e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 1290965217e74fe07f1451350a80114ab566ced5de0Evan Cheng virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 1308601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, 1310965217e74fe07f1451350a80114ab566ced5de0Evan Cheng uint64_t Offset, 1320965217e74fe07f1451350a80114ab566ced5de0Evan Cheng const MDNode *MDPtr, 1330965217e74fe07f1451350a80114ab566ced5de0Evan Cheng DebugLoc DL) const; 1340965217e74fe07f1451350a80114ab566ced5de0Evan Cheng 13544eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson virtual 13644eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 1376e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 13852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// GetInstSize - Return the number of bytes of code the specified 13952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// instruction may be. This returns the maximum number of bytes. 14052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// 14152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 142f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman}; 143f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 144f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman} 145f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 146f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#endif 147