PPCInstrInfo.h revision 4a66e9a57e679b4f3243bf2061daf53c70102030 
1//===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef POWERPC32_INSTRUCTIONINFO_H
15#define POWERPC32_INSTRUCTIONINFO_H
16
17#include "PPC.h"
18#include "llvm/Target/TargetInstrInfo.h"
19#include "PPCRegisterInfo.h"
20
21namespace llvm {
22
23/// PPCII - This namespace holds all of the PowerPC target-specific
24/// per-instruction flags.  These must match the corresponding definitions in
25/// PPC.td and PPCInstrFormats.td.
26namespace PPCII {
27enum {
28  // PPC970 Instruction Flags.  These flags describe the characteristics of the
29  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
30  // raw machine instructions.
31
32  /// PPC970_First - This instruction starts a new dispatch group, so it will
33  /// always be the first one in the group.
34  PPC970_First = 0x1,
35
36  /// PPC970_Single - This instruction starts a new dispatch group and
37  /// terminates it, so it will be the sole instruction in the group.
38  PPC970_Single = 0x2,
39
40  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
41  /// two dispatch pipes to be available to issue.
42  PPC970_Cracked = 0x4,
43
44  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
45  /// an instruction is issued to.
46  PPC970_Shift = 3,
47  PPC970_Mask = 0x07 << PPC970_Shift
48};
49enum PPC970_Unit {
50  /// These are the various PPC970 execution unit pipelines.  Each instruction
51  /// is one of these.
52  PPC970_Pseudo = 0 << PPC970_Shift,   // Pseudo instruction
53  PPC970_FXU    = 1 << PPC970_Shift,   // Fixed Point (aka Integer/ALU) Unit
54  PPC970_LSU    = 2 << PPC970_Shift,   // Load Store Unit
55  PPC970_FPU    = 3 << PPC970_Shift,   // Floating Point Unit
56  PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
57  PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
58  PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
59  PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
60};
61}
62
63
64class PPCInstrInfo : public TargetInstrInfoImpl {
65  PPCTargetMachine &TM;
66  const PPCRegisterInfo RI;
67
68  bool StoreRegToStackSlot(unsigned SrcReg, bool isKill, int FrameIdx,
69                           const TargetRegisterClass *RC,
70                           SmallVectorImpl<MachineInstr*> &NewMIs) const;
71  void LoadRegFromStackSlot(unsigned DestReg, int FrameIdx,
72                            const TargetRegisterClass *RC,
73                            SmallVectorImpl<MachineInstr*> &NewMIs) const;
74public:
75  PPCInstrInfo(PPCTargetMachine &TM);
76
77  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
78  /// such, whenever a client has an instance of instruction info, it should
79  /// always be able to get register info as well (through this method).
80  ///
81  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
82
83  /// getPointerRegClass - Return the register class to use to hold pointers.
84  /// This is used for addressing modes.
85  virtual const TargetRegisterClass *getPointerRegClass() const;
86
87  // Return true if the instruction is a register to register move and
88  // leave the source and dest operands in the passed parameters.
89  //
90  virtual bool isMoveInstr(const MachineInstr& MI,
91                           unsigned& sourceReg,
92                           unsigned& destReg) const;
93
94  unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
95  unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
96
97  // commuteInstruction - We can commute rlwimi instructions, but only if the
98  // rotate amt is zero.  We also have to munge the immediates a bit.
99  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
100
101  virtual void insertNoop(MachineBasicBlock &MBB,
102                          MachineBasicBlock::iterator MI) const;
103
104
105  // Branch analysis.
106  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
107                             MachineBasicBlock *&FBB,
108                             std::vector<MachineOperand> &Cond) const;
109  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
110  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
111                                MachineBasicBlock *FBB,
112                                const std::vector<MachineOperand> &Cond) const;
113  virtual void copyRegToReg(MachineBasicBlock &MBB,
114                            MachineBasicBlock::iterator MI,
115                            unsigned DestReg, unsigned SrcReg,
116                            const TargetRegisterClass *DestRC,
117                            const TargetRegisterClass *SrcRC) const;
118
119  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
120                                   MachineBasicBlock::iterator MBBI,
121                                   unsigned SrcReg, bool isKill, int FrameIndex,
122                                   const TargetRegisterClass *RC) const;
123
124  virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
125                              SmallVectorImpl<MachineOperand> &Addr,
126                              const TargetRegisterClass *RC,
127                              SmallVectorImpl<MachineInstr*> &NewMIs) const;
128
129  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
130                                    MachineBasicBlock::iterator MBBI,
131                                    unsigned DestReg, int FrameIndex,
132                                    const TargetRegisterClass *RC) const;
133
134  virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
135                               SmallVectorImpl<MachineOperand> &Addr,
136                               const TargetRegisterClass *RC,
137                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
138
139  /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
140  /// copy instructions, turning them into load/store instructions.
141  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
142                                          MachineInstr* MI,
143                                          SmallVectorImpl<unsigned> &Ops,
144                                          int FrameIndex) const;
145
146  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
147                                          MachineInstr* MI,
148                                          SmallVectorImpl<unsigned> &Ops,
149                                          MachineInstr* LoadMI) const {
150    return 0;
151  }
152
153  virtual bool canFoldMemoryOperand(MachineInstr *MI,
154                                    SmallVectorImpl<unsigned> &Ops) const;
155
156  virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
157  virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
158};
159
160}
161
162#endif
163