PPCInstrInfo.h revision d1c321a89ab999b9bb602b0f398ecd4c2022262c
1c16257f05391b8aeccef62d6b543f1cb5a8185feChris Lattner//===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// The LLVM Compiler Infrastructure 4f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 9f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 10f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// This file contains the PowerPC implementation of the TargetInstrInfo class. 11f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 12f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 13f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 14f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#ifndef POWERPC32_INSTRUCTIONINFO_H 15f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#define POWERPC32_INSTRUCTIONINFO_H 16f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 172668959b8879097db368aec7d76c455260abc75bChris Lattner#include "PPC.h" 18617742b1b8b7fbb07b4ab5db7c292bff78d709f6Chris Lattner#include "llvm/Target/TargetInstrInfo.h" 1916e71f2f70811c69c56052dd146324fe20e31db5Chris Lattner#include "PPCRegisterInfo.h" 20f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 21f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukmannamespace llvm { 2288d211f82304e53694ece666d4a2507b170e4582Chris Lattner 2388d211f82304e53694ece666d4a2507b170e4582Chris Lattner/// PPCII - This namespace holds all of the PowerPC target-specific 2488d211f82304e53694ece666d4a2507b170e4582Chris Lattner/// per-instruction flags. These must match the corresponding definitions in 2588d211f82304e53694ece666d4a2507b170e4582Chris Lattner/// PPC.td and PPCInstrFormats.td. 2688d211f82304e53694ece666d4a2507b170e4582Chris Lattnernamespace PPCII { 2788d211f82304e53694ece666d4a2507b170e4582Chris Lattnerenum { 2888d211f82304e53694ece666d4a2507b170e4582Chris Lattner // PPC970 Instruction Flags. These flags describe the characteristics of the 2988d211f82304e53694ece666d4a2507b170e4582Chris Lattner // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 3088d211f82304e53694ece666d4a2507b170e4582Chris Lattner // raw machine instructions. 3188d211f82304e53694ece666d4a2507b170e4582Chris Lattner 3288d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// PPC970_First - This instruction starts a new dispatch group, so it will 3388d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// always be the first one in the group. 3488d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_First = 0x1, 3588d211f82304e53694ece666d4a2507b170e4582Chris Lattner 3688d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// PPC970_Single - This instruction starts a new dispatch group and 3788d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// terminates it, so it will be the sole instruction in the group. 3888d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_Single = 0x2, 3988d211f82304e53694ece666d4a2507b170e4582Chris Lattner 40fd97734f3636f54a86890918096d3d692df0b939Chris Lattner /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 41fd97734f3636f54a86890918096d3d692df0b939Chris Lattner /// two dispatch pipes to be available to issue. 42fd97734f3636f54a86890918096d3d692df0b939Chris Lattner PPC970_Cracked = 0x4, 43fd97734f3636f54a86890918096d3d692df0b939Chris Lattner 4488d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 4588d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// an instruction is issued to. 46fd97734f3636f54a86890918096d3d692df0b939Chris Lattner PPC970_Shift = 3, 47d74ea2bbd8bb630331f35ead42d385249bd42af8Chris Lattner PPC970_Mask = 0x07 << PPC970_Shift 4888d211f82304e53694ece666d4a2507b170e4582Chris Lattner}; 4988d211f82304e53694ece666d4a2507b170e4582Chris Lattnerenum PPC970_Unit { 5088d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// These are the various PPC970 execution unit pipelines. Each instruction 5188d211f82304e53694ece666d4a2507b170e4582Chris Lattner /// is one of these. 5288d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 5388d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 5488d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 5588d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 5688d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 5788d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 5888d211f82304e53694ece666d4a2507b170e4582Chris Lattner PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 59d74ea2bbd8bb630331f35ead42d385249bd42af8Chris Lattner PPC970_BRU = 7 << PPC970_Shift // Branch Unit 6088d211f82304e53694ece666d4a2507b170e4582Chris Lattner}; 6188d211f82304e53694ece666d4a2507b170e4582Chris Lattner} 6288d211f82304e53694ece666d4a2507b170e4582Chris Lattner 63617742b1b8b7fbb07b4ab5db7c292bff78d709f6Chris Lattner 64641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerclass PPCInstrInfo : public TargetInstrInfoImpl { 65b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner PPCTargetMachine &TM; 6621e463b2bf864671a87ebe386cb100ef9349a540Nate Begeman const PPCRegisterInfo RI; 674a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling 688e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman bool StoreRegToStackSlot(MachineFunction &MF, 698e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman unsigned SrcReg, bool isKill, int FrameIdx, 704a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling const TargetRegisterClass *RC, 714a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling SmallVectorImpl<MachineInstr*> &NewMIs) const; 72d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling void LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 738e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman unsigned DestReg, int FrameIdx, 744a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling const TargetRegisterClass *RC, 754a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling SmallVectorImpl<MachineInstr*> &NewMIs) const; 76f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukmanpublic: 77950a4c40b823cd4f09dc71be635229246dfd6cacDan Gohman explicit PPCInstrInfo(PPCTargetMachine &TM); 78f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 79f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 80f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman /// such, whenever a client has an instance of instruction info, it should 81f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman /// always be able to get register info as well (through this method). 82f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman /// 83c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6Dan Gohman virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; } 84f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 8504ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng /// Return true if the instruction is a register to register move and return 8604ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng /// the source and dest operands and their sub-register indices by reference. 8704ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng virtual bool isMoveInstr(const MachineInstr &MI, 8804ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned &SrcReg, unsigned &DstReg, 8904ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 90f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 91cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman unsigned isLoadFromStackSlot(const MachineInstr *MI, 92cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const; 93cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman unsigned isStoreToStackSlot(const MachineInstr *MI, 94cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const; 95408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 96043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // commuteInstruction - We can commute rlwimi instructions, but only if the 97043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // rotate amt is zero. We also have to munge the immediates a bit. 9858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 99043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 100bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner virtual void insertNoop(MachineBasicBlock &MBB, 101bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner MachineBasicBlock::iterator MI) const; 102bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner 103c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 104c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Branch analysis. 105c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 106c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock *&FBB, 107dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 108dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify) const; 109b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 110b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 111b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng MachineBasicBlock *FBB, 11244eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Cond) const; 113940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson virtual bool copyRegToReg(MachineBasicBlock &MBB, 114f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 115f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, unsigned SrcReg, 116f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *DestRC, 117f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *SrcRC) const; 118f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 119f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 120f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MBBI, 121f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIndex, 122f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const; 123f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 124f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 125f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 126f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 127f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const; 128f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 129f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 130f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MBBI, 131f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIndex, 132f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const; 133f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 134f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 135f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 136f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 137f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const; 138f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 13943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 14043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// copy instructions, turning them into load/store instructions. 141c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 142c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 143c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 144c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const; 145c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 146c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 147c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 148c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 149c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const { 15043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 15143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 15243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 1538e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman virtual bool canFoldMemoryOperand(const MachineInstr *MI, 1548e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops) const; 15543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 1568e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; 15744eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson virtual 15844eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 15952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 16052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// GetInstSize - Return the number of bytes of code the specified 16152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// instruction may be. This returns the maximum number of bytes. 16252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// 16352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 164f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman}; 165f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 166f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman} 167f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 168f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#endif 169