SparcISelDAGToDAG.cpp revision 61273d55e9ce068fef5dfcddb65e5ad9c1f4772e
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SPARC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcTargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/CodeGen/SelectionDAGISel.h" 25#include "llvm/Target/TargetLowering.h" 26#include "llvm/Support/Compiler.h" 27#include "llvm/Support/Debug.h" 28#include <queue> 29#include <set> 30using namespace llvm; 31 32//===----------------------------------------------------------------------===// 33// TargetLowering Implementation 34//===----------------------------------------------------------------------===// 35 36namespace SPISD { 37 enum { 38 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 39 CMPICC, // Compare two GPR operands, set icc. 40 CMPFCC, // Compare two FP operands, set fcc. 41 BRICC, // Branch to dest on icc condition 42 BRFCC, // Branch to dest on fcc condition 43 SELECT_ICC, // Select between two values using the current ICC flags. 44 SELECT_FCC, // Select between two values using the current FCC flags. 45 46 Hi, Lo, // Hi/Lo operations, typically on a global address. 47 48 FTOI, // FP to Int within a FP register. 49 ITOF, // Int to FP within a FP register. 50 51 CALL, // A call instruction. 52 RET_FLAG // Return with a flag operand. 53 }; 54} 55 56/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 57/// condition. 58static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 59 switch (CC) { 60 default: assert(0 && "Unknown integer condition code!"); 61 case ISD::SETEQ: return SPCC::ICC_E; 62 case ISD::SETNE: return SPCC::ICC_NE; 63 case ISD::SETLT: return SPCC::ICC_L; 64 case ISD::SETGT: return SPCC::ICC_G; 65 case ISD::SETLE: return SPCC::ICC_LE; 66 case ISD::SETGE: return SPCC::ICC_GE; 67 case ISD::SETULT: return SPCC::ICC_CS; 68 case ISD::SETULE: return SPCC::ICC_LEU; 69 case ISD::SETUGT: return SPCC::ICC_GU; 70 case ISD::SETUGE: return SPCC::ICC_CC; 71 } 72} 73 74/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 75/// FCC condition. 76static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 77 switch (CC) { 78 default: assert(0 && "Unknown fp condition code!"); 79 case ISD::SETEQ: 80 case ISD::SETOEQ: return SPCC::FCC_E; 81 case ISD::SETNE: 82 case ISD::SETUNE: return SPCC::FCC_NE; 83 case ISD::SETLT: 84 case ISD::SETOLT: return SPCC::FCC_L; 85 case ISD::SETGT: 86 case ISD::SETOGT: return SPCC::FCC_G; 87 case ISD::SETLE: 88 case ISD::SETOLE: return SPCC::FCC_LE; 89 case ISD::SETGE: 90 case ISD::SETOGE: return SPCC::FCC_GE; 91 case ISD::SETULT: return SPCC::FCC_UL; 92 case ISD::SETULE: return SPCC::FCC_ULE; 93 case ISD::SETUGT: return SPCC::FCC_UG; 94 case ISD::SETUGE: return SPCC::FCC_UGE; 95 case ISD::SETUO: return SPCC::FCC_U; 96 case ISD::SETO: return SPCC::FCC_O; 97 case ISD::SETONE: return SPCC::FCC_LG; 98 case ISD::SETUEQ: return SPCC::FCC_UE; 99 } 100} 101 102namespace { 103 class SparcTargetLowering : public TargetLowering { 104 int VarArgsFrameOffset; // Frame offset to start of varargs area. 105 public: 106 SparcTargetLowering(TargetMachine &TM); 107 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 108 109 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 110 /// in Mask are known to be either zero or one and return them in the 111 /// KnownZero/KnownOne bitsets. 112 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 113 const APInt &Mask, 114 APInt &KnownZero, 115 APInt &KnownOne, 116 const SelectionDAG &DAG, 117 unsigned Depth = 0) const; 118 119 virtual std::vector<SDOperand> 120 LowerArguments(Function &F, SelectionDAG &DAG); 121 virtual std::pair<SDOperand, SDOperand> 122 LowerCallTo(SDOperand Chain, const Type *RetTy, 123 bool RetSExt, bool RetZExt, bool isVarArg, 124 unsigned CC, bool isTailCall, SDOperand Callee, 125 ArgListTy &Args, SelectionDAG &DAG); 126 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 127 MachineBasicBlock *MBB); 128 129 virtual const char *getTargetNodeName(unsigned Opcode) const; 130 }; 131} 132 133SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 134 : TargetLowering(TM) { 135 136 // Set up the register classes. 137 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 138 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 139 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 140 141 // Turn FP extload into load/fextend 142 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 143 144 // Sparc doesn't have i1 sign extending load 145 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 146 147 // Custom legalize GlobalAddress nodes into LO/HI parts. 148 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 149 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 150 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 151 152 // Sparc doesn't have sext_inreg, replace them with shl/sra 153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 156 157 // Sparc has no REM or DIVREM operations. 158 setOperationAction(ISD::UREM, MVT::i32, Expand); 159 setOperationAction(ISD::SREM, MVT::i32, Expand); 160 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 161 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 162 163 // Custom expand fp<->sint 164 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 165 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 166 167 // Expand fp<->uint 168 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 169 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 170 171 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 172 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 173 174 // Sparc has no select or setcc: expand to SELECT_CC. 175 setOperationAction(ISD::SELECT, MVT::i32, Expand); 176 setOperationAction(ISD::SELECT, MVT::f32, Expand); 177 setOperationAction(ISD::SELECT, MVT::f64, Expand); 178 setOperationAction(ISD::SETCC, MVT::i32, Expand); 179 setOperationAction(ISD::SETCC, MVT::f32, Expand); 180 setOperationAction(ISD::SETCC, MVT::f64, Expand); 181 182 // Sparc doesn't have BRCOND either, it has BR_CC. 183 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 184 setOperationAction(ISD::BRIND, MVT::Other, Expand); 185 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 186 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 187 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 188 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 189 190 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 191 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 192 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 193 194 // SPARC has no intrinsics for these particular operations. 195 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 196 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 197 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 198 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 199 200 setOperationAction(ISD::FSIN , MVT::f64, Expand); 201 setOperationAction(ISD::FCOS , MVT::f64, Expand); 202 setOperationAction(ISD::FREM , MVT::f64, Expand); 203 setOperationAction(ISD::FSIN , MVT::f32, Expand); 204 setOperationAction(ISD::FCOS , MVT::f32, Expand); 205 setOperationAction(ISD::FREM , MVT::f32, Expand); 206 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 207 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 208 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 209 setOperationAction(ISD::ROTL , MVT::i32, Expand); 210 setOperationAction(ISD::ROTR , MVT::i32, Expand); 211 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 212 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 213 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 214 setOperationAction(ISD::FPOW , MVT::f64, Expand); 215 setOperationAction(ISD::FPOW , MVT::f32, Expand); 216 217 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 218 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 219 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 220 221 // FIXME: Sparc provides these multiplies, but we don't have them yet. 222 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 223 224 // We don't have line number support yet. 225 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 226 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 227 setOperationAction(ISD::LABEL, MVT::Other, Expand); 228 229 // RET must be custom lowered, to meet ABI requirements 230 setOperationAction(ISD::RET , MVT::Other, Custom); 231 232 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 233 setOperationAction(ISD::VASTART , MVT::Other, Custom); 234 // VAARG needs to be lowered to not do unaligned accesses for doubles. 235 setOperationAction(ISD::VAARG , MVT::Other, Custom); 236 237 // Use the default implementation. 238 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 239 setOperationAction(ISD::VAEND , MVT::Other, Expand); 240 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 241 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 242 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 243 244 setStackPointerRegisterToSaveRestore(SP::O6); 245 246 if (TM.getSubtarget<SparcSubtarget>().isV9()) { 247 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 248 } 249 250 computeRegisterProperties(); 251} 252 253const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 254 switch (Opcode) { 255 default: return 0; 256 case SPISD::CMPICC: return "SPISD::CMPICC"; 257 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 258 case SPISD::BRICC: return "SPISD::BRICC"; 259 case SPISD::BRFCC: return "SPISD::BRFCC"; 260 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 261 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 262 case SPISD::Hi: return "SPISD::Hi"; 263 case SPISD::Lo: return "SPISD::Lo"; 264 case SPISD::FTOI: return "SPISD::FTOI"; 265 case SPISD::ITOF: return "SPISD::ITOF"; 266 case SPISD::CALL: return "SPISD::CALL"; 267 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 268 } 269} 270 271/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 272/// be zero. Op is expected to be a target specific node. Used by DAG 273/// combiner. 274void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 275 const APInt &Mask, 276 APInt &KnownZero, 277 APInt &KnownOne, 278 const SelectionDAG &DAG, 279 unsigned Depth) const { 280 APInt KnownZero2, KnownOne2; 281 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 282 283 switch (Op.getOpcode()) { 284 default: break; 285 case SPISD::SELECT_ICC: 286 case SPISD::SELECT_FCC: 287 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 288 Depth+1); 289 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 290 Depth+1); 291 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 292 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 293 294 // Only known if known in both the LHS and RHS. 295 KnownOne &= KnownOne2; 296 KnownZero &= KnownZero2; 297 break; 298 } 299} 300 301/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 302/// either one or two GPRs, including FP values. TODO: we should pass FP values 303/// in FP registers for fastcc functions. 304std::vector<SDOperand> 305SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 306 MachineFunction &MF = DAG.getMachineFunction(); 307 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 308 std::vector<SDOperand> ArgValues; 309 310 static const unsigned ArgRegs[] = { 311 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 312 }; 313 314 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 315 unsigned ArgOffset = 68; 316 317 SDOperand Root = DAG.getRoot(); 318 std::vector<SDOperand> OutChains; 319 320 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 321 MVT::ValueType ObjectVT = getValueType(I->getType()); 322 323 switch (ObjectVT) { 324 default: assert(0 && "Unhandled argument type!"); 325 case MVT::i1: 326 case MVT::i8: 327 case MVT::i16: 328 case MVT::i32: 329 if (I->use_empty()) { // Argument is dead. 330 if (CurArgReg < ArgRegEnd) ++CurArgReg; 331 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 332 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 333 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 334 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 335 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 336 if (ObjectVT != MVT::i32) { 337 unsigned AssertOp = ISD::AssertSext; 338 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 339 DAG.getValueType(ObjectVT)); 340 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 341 } 342 ArgValues.push_back(Arg); 343 } else { 344 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 345 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 346 SDOperand Load; 347 if (ObjectVT == MVT::i32) { 348 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 349 } else { 350 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 351 352 // Sparc is big endian, so add an offset based on the ObjectVT. 353 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 354 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 355 DAG.getConstant(Offset, MVT::i32)); 356 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 357 NULL, 0, ObjectVT); 358 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 359 } 360 ArgValues.push_back(Load); 361 } 362 363 ArgOffset += 4; 364 break; 365 case MVT::f32: 366 if (I->use_empty()) { // Argument is dead. 367 if (CurArgReg < ArgRegEnd) ++CurArgReg; 368 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 369 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 370 // FP value is passed in an integer register. 371 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 372 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 373 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 374 375 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 376 ArgValues.push_back(Arg); 377 } else { 378 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 379 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 380 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); 381 ArgValues.push_back(Load); 382 } 383 ArgOffset += 4; 384 break; 385 386 case MVT::i64: 387 case MVT::f64: 388 if (I->use_empty()) { // Argument is dead. 389 if (CurArgReg < ArgRegEnd) ++CurArgReg; 390 if (CurArgReg < ArgRegEnd) ++CurArgReg; 391 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 392 } else if (/* FIXME: Apparently this isn't safe?? */ 393 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 394 ((CurArgReg-ArgRegs) & 1) == 0) { 395 // If this is a double argument and the whole thing lives on the stack, 396 // and the argument is aligned, load the double straight from the stack. 397 // We can't do a load in cases like void foo([6ints], int,double), 398 // because the double wouldn't be aligned! 399 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 400 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 401 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); 402 } else { 403 SDOperand HiVal; 404 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 405 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 406 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); 407 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 408 } else { 409 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 410 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 411 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 412 } 413 414 SDOperand LoVal; 415 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 416 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 417 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); 418 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 419 } else { 420 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 421 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 422 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 423 } 424 425 // Compose the two halves together into an i64 unit. 426 SDOperand WholeValue = 427 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 428 429 // If we want a double, do a bit convert. 430 if (ObjectVT == MVT::f64) 431 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 432 433 ArgValues.push_back(WholeValue); 434 } 435 ArgOffset += 8; 436 break; 437 } 438 } 439 440 // Store remaining ArgRegs to the stack if this is a varargs function. 441 if (F.getFunctionType()->isVarArg()) { 442 // Remember the vararg offset for the va_start implementation. 443 VarArgsFrameOffset = ArgOffset; 444 445 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 446 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 447 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 448 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 449 450 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 451 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 452 453 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); 454 ArgOffset += 4; 455 } 456 } 457 458 if (!OutChains.empty()) 459 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 460 &OutChains[0], OutChains.size())); 461 462 // Finally, inform the code generator which regs we return values in. 463 switch (getValueType(F.getReturnType())) { 464 default: assert(0 && "Unknown type!"); 465 case MVT::isVoid: break; 466 case MVT::i1: 467 case MVT::i8: 468 case MVT::i16: 469 case MVT::i32: 470 MF.getRegInfo().addLiveOut(SP::I0); 471 break; 472 case MVT::i64: 473 MF.getRegInfo().addLiveOut(SP::I0); 474 MF.getRegInfo().addLiveOut(SP::I1); 475 break; 476 case MVT::f32: 477 MF.getRegInfo().addLiveOut(SP::F0); 478 break; 479 case MVT::f64: 480 MF.getRegInfo().addLiveOut(SP::D0); 481 break; 482 } 483 484 return ArgValues; 485} 486 487std::pair<SDOperand, SDOperand> 488SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 489 bool RetSExt, bool RetZExt, bool isVarArg, 490 unsigned CC, bool isTailCall, SDOperand Callee, 491 ArgListTy &Args, SelectionDAG &DAG) { 492 // Count the size of the outgoing arguments. 493 unsigned ArgsSize = 0; 494 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 495 switch (getValueType(Args[i].Ty)) { 496 default: assert(0 && "Unknown value type!"); 497 case MVT::i1: 498 case MVT::i8: 499 case MVT::i16: 500 case MVT::i32: 501 case MVT::f32: 502 ArgsSize += 4; 503 break; 504 case MVT::i64: 505 case MVT::f64: 506 ArgsSize += 8; 507 break; 508 } 509 } 510 if (ArgsSize > 4*6) 511 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 512 else 513 ArgsSize = 0; 514 515 // Keep stack frames 8-byte aligned. 516 ArgsSize = (ArgsSize+7) & ~7; 517 518 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 519 520 SDOperand StackPtr; 521 std::vector<SDOperand> Stores; 522 std::vector<SDOperand> RegValuesToPass; 523 unsigned ArgOffset = 68; 524 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 525 SDOperand Val = Args[i].Node; 526 MVT::ValueType ObjectVT = Val.getValueType(); 527 SDOperand ValToStore(0, 0); 528 unsigned ObjSize; 529 switch (ObjectVT) { 530 default: assert(0 && "Unhandled argument type!"); 531 case MVT::i1: 532 case MVT::i8: 533 case MVT::i16: { 534 // Promote the integer to 32-bits. If the input type is signed, use a 535 // sign extend, otherwise use a zero extend. 536 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 537 if (Args[i].isSExt) 538 ExtendKind = ISD::SIGN_EXTEND; 539 else if (Args[i].isZExt) 540 ExtendKind = ISD::ZERO_EXTEND; 541 Val = DAG.getNode(ExtendKind, MVT::i32, Val); 542 // FALL THROUGH 543 } 544 case MVT::i32: 545 ObjSize = 4; 546 547 if (RegValuesToPass.size() >= 6) { 548 ValToStore = Val; 549 } else { 550 RegValuesToPass.push_back(Val); 551 } 552 break; 553 case MVT::f32: 554 ObjSize = 4; 555 if (RegValuesToPass.size() >= 6) { 556 ValToStore = Val; 557 } else { 558 // Convert this to a FP value in an int reg. 559 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 560 RegValuesToPass.push_back(Val); 561 } 562 break; 563 case MVT::f64: 564 ObjSize = 8; 565 // If we can store this directly into the outgoing slot, do so. We can 566 // do this when all ArgRegs are used and if the outgoing slot is aligned. 567 // FIXME: McGill/misr fails with this. 568 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 569 ValToStore = Val; 570 break; 571 } 572 573 // Otherwise, convert this to a FP value in int regs. 574 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 575 // FALL THROUGH 576 case MVT::i64: 577 ObjSize = 8; 578 if (RegValuesToPass.size() >= 6) { 579 ValToStore = Val; // Whole thing is passed in memory. 580 break; 581 } 582 583 // Split the value into top and bottom part. Top part goes in a reg. 584 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 585 DAG.getConstant(1, MVT::i32)); 586 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 587 DAG.getConstant(0, MVT::i32)); 588 RegValuesToPass.push_back(Hi); 589 590 if (RegValuesToPass.size() >= 6) { 591 ValToStore = Lo; 592 ArgOffset += 4; 593 ObjSize = 4; 594 } else { 595 RegValuesToPass.push_back(Lo); 596 } 597 break; 598 } 599 600 if (ValToStore.Val) { 601 if (!StackPtr.Val) { 602 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 603 } 604 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 605 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 606 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); 607 } 608 ArgOffset += ObjSize; 609 } 610 611 // Emit all stores, make sure the occur before any copies into physregs. 612 if (!Stores.empty()) 613 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); 614 615 static const unsigned ArgRegs[] = { 616 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 617 }; 618 619 // Build a sequence of copy-to-reg nodes chained together with token chain 620 // and flag operands which copy the outgoing args into O[0-5]. 621 SDOperand InFlag; 622 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 623 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 624 InFlag = Chain.getValue(1); 625 } 626 627 // If the callee is a GlobalAddress node (quite common, every direct call is) 628 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 629 // Likewise ExternalSymbol -> TargetExternalSymbol. 630 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 631 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 632 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 633 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 634 635 std::vector<MVT::ValueType> NodeTys; 636 NodeTys.push_back(MVT::Other); // Returns a chain 637 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 638 SDOperand Ops[] = { Chain, Callee, InFlag }; 639 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); 640 InFlag = Chain.getValue(1); 641 642 MVT::ValueType RetTyVT = getValueType(RetTy); 643 SDOperand RetVal; 644 if (RetTyVT != MVT::isVoid) { 645 switch (RetTyVT) { 646 default: assert(0 && "Unknown value type to return!"); 647 case MVT::i1: 648 case MVT::i8: 649 case MVT::i16: { 650 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 651 Chain = RetVal.getValue(1); 652 653 // Add a note to keep track of whether it is sign or zero extended. 654 ISD::NodeType AssertKind = ISD::DELETED_NODE; 655 if (RetSExt) 656 AssertKind = ISD::AssertSext; 657 else if (RetZExt) 658 AssertKind = ISD::AssertZext; 659 660 if (AssertKind != ISD::DELETED_NODE) 661 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal, 662 DAG.getValueType(RetTyVT)); 663 664 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 665 break; 666 } 667 case MVT::i32: 668 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 669 Chain = RetVal.getValue(1); 670 break; 671 case MVT::f32: 672 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 673 Chain = RetVal.getValue(1); 674 break; 675 case MVT::f64: 676 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 677 Chain = RetVal.getValue(1); 678 break; 679 case MVT::i64: 680 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 681 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 682 Lo.getValue(2)); 683 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 684 Chain = Hi.getValue(1); 685 break; 686 } 687 } 688 689 Chain = DAG.getCALLSEQ_END(Chain, 690 DAG.getConstant(ArgsSize, getPointerTy()), 691 DAG.getConstant(0, getPointerTy()), 692 SDOperand()); 693 return std::make_pair(RetVal, Chain); 694} 695 696// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 697// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 698static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 699 ISD::CondCode CC, unsigned &SPCC) { 700 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 701 CC == ISD::SETNE && 702 ((LHS.getOpcode() == SPISD::SELECT_ICC && 703 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 704 (LHS.getOpcode() == SPISD::SELECT_FCC && 705 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 706 isa<ConstantSDNode>(LHS.getOperand(0)) && 707 isa<ConstantSDNode>(LHS.getOperand(1)) && 708 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 709 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 710 SDOperand CMPCC = LHS.getOperand(3); 711 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 712 LHS = CMPCC.getOperand(0); 713 RHS = CMPCC.getOperand(1); 714 } 715} 716 717 718SDOperand SparcTargetLowering:: 719LowerOperation(SDOperand Op, SelectionDAG &DAG) { 720 switch (Op.getOpcode()) { 721 default: assert(0 && "Should not custom lower this!"); 722 case ISD::GlobalTLSAddress: 723 assert(0 && "TLS not implemented for Sparc."); 724 case ISD::GlobalAddress: { 725 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 726 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 727 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 728 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 729 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 730 } 731 case ISD::ConstantPool: { 732 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal(); 733 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 734 cast<ConstantPoolSDNode>(Op)->getAlignment()); 735 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 736 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 737 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 738 } 739 case ISD::FP_TO_SINT: 740 // Convert the fp value to integer in an FP register. 741 assert(Op.getValueType() == MVT::i32); 742 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 743 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 744 case ISD::SINT_TO_FP: { 745 assert(Op.getOperand(0).getValueType() == MVT::i32); 746 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 747 // Convert the int value to FP in an FP register. 748 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 749 } 750 case ISD::BR_CC: { 751 SDOperand Chain = Op.getOperand(0); 752 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 753 SDOperand LHS = Op.getOperand(2); 754 SDOperand RHS = Op.getOperand(3); 755 SDOperand Dest = Op.getOperand(4); 756 unsigned Opc, SPCC = ~0U; 757 758 // If this is a br_cc of a "setcc", and if the setcc got lowered into 759 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 760 LookThroughSetCC(LHS, RHS, CC, SPCC); 761 762 // Get the condition flag. 763 SDOperand CompareFlag; 764 if (LHS.getValueType() == MVT::i32) { 765 std::vector<MVT::ValueType> VTs; 766 VTs.push_back(MVT::i32); 767 VTs.push_back(MVT::Flag); 768 SDOperand Ops[2] = { LHS, RHS }; 769 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 770 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 771 Opc = SPISD::BRICC; 772 } else { 773 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 774 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 775 Opc = SPISD::BRFCC; 776 } 777 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 778 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 779 } 780 case ISD::SELECT_CC: { 781 SDOperand LHS = Op.getOperand(0); 782 SDOperand RHS = Op.getOperand(1); 783 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 784 SDOperand TrueVal = Op.getOperand(2); 785 SDOperand FalseVal = Op.getOperand(3); 786 unsigned Opc, SPCC = ~0U; 787 788 // If this is a select_cc of a "setcc", and if the setcc got lowered into 789 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 790 LookThroughSetCC(LHS, RHS, CC, SPCC); 791 792 SDOperand CompareFlag; 793 if (LHS.getValueType() == MVT::i32) { 794 std::vector<MVT::ValueType> VTs; 795 VTs.push_back(LHS.getValueType()); // subcc returns a value 796 VTs.push_back(MVT::Flag); 797 SDOperand Ops[2] = { LHS, RHS }; 798 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 799 Opc = SPISD::SELECT_ICC; 800 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 801 } else { 802 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 803 Opc = SPISD::SELECT_FCC; 804 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 805 } 806 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 807 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 808 } 809 case ISD::VASTART: { 810 // vastart just stores the address of the VarArgsFrameIndex slot into the 811 // memory location argument. 812 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 813 DAG.getRegister(SP::I6, MVT::i32), 814 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 815 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 816 return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0); 817 } 818 case ISD::VAARG: { 819 SDNode *Node = Op.Val; 820 MVT::ValueType VT = Node->getValueType(0); 821 SDOperand InChain = Node->getOperand(0); 822 SDOperand VAListPtr = Node->getOperand(1); 823 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 824 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, SV, 0); 825 // Increment the pointer, VAList, to the next vaarg 826 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 827 DAG.getConstant(MVT::getSizeInBits(VT)/8, 828 getPointerTy())); 829 // Store the incremented VAList to the legalized pointer 830 InChain = DAG.getStore(VAList.getValue(1), NextPtr, 831 VAListPtr, SV, 0); 832 // Load the actual argument out of the pointer VAList, unless this is an 833 // f64 load. 834 if (VT != MVT::f64) { 835 return DAG.getLoad(VT, InChain, VAList, NULL, 0); 836 } else { 837 // Otherwise, load it as i64, then do a bitconvert. 838 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); 839 std::vector<MVT::ValueType> Tys; 840 Tys.push_back(MVT::f64); 841 Tys.push_back(MVT::Other); 842 // Bit-Convert the value to f64. 843 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 844 V.getValue(1) }; 845 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 846 } 847 } 848 case ISD::DYNAMIC_STACKALLOC: { 849 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 850 SDOperand Size = Op.getOperand(1); // Legalize the size. 851 852 unsigned SPReg = SP::O6; 853 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 854 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 855 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 856 857 // The resultant pointer is actually 16 words from the bottom of the stack, 858 // to provide a register spill area. 859 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 860 DAG.getConstant(96, MVT::i32)); 861 std::vector<MVT::ValueType> Tys; 862 Tys.push_back(MVT::i32); 863 Tys.push_back(MVT::Other); 864 SDOperand Ops[2] = { NewVal, Chain }; 865 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 866 } 867 case ISD::RET: { 868 SDOperand Copy; 869 870 switch(Op.getNumOperands()) { 871 default: 872 assert(0 && "Do not know how to return this many arguments!"); 873 abort(); 874 case 1: 875 return SDOperand(); // ret void is legal 876 case 3: { 877 unsigned ArgReg; 878 switch(Op.getOperand(1).getValueType()) { 879 default: assert(0 && "Unknown type to return!"); 880 case MVT::i32: ArgReg = SP::I0; break; 881 case MVT::f32: ArgReg = SP::F0; break; 882 case MVT::f64: ArgReg = SP::D0; break; 883 } 884 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 885 SDOperand()); 886 break; 887 } 888 case 5: 889 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 890 SDOperand()); 891 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 892 break; 893 } 894 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 895 } 896 // Frame & Return address. Currently unimplemented 897 case ISD::RETURNADDR: break; 898 case ISD::FRAMEADDR: break; 899 } 900 return SDOperand(); 901} 902 903MachineBasicBlock * 904SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 905 MachineBasicBlock *BB) { 906 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 907 unsigned BROpcode; 908 unsigned CC; 909 // Figure out the conditional branch opcode to use for this select_cc. 910 switch (MI->getOpcode()) { 911 default: assert(0 && "Unknown SELECT_CC!"); 912 case SP::SELECT_CC_Int_ICC: 913 case SP::SELECT_CC_FP_ICC: 914 case SP::SELECT_CC_DFP_ICC: 915 BROpcode = SP::BCOND; 916 break; 917 case SP::SELECT_CC_Int_FCC: 918 case SP::SELECT_CC_FP_FCC: 919 case SP::SELECT_CC_DFP_FCC: 920 BROpcode = SP::FBCOND; 921 break; 922 } 923 924 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 925 926 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 927 // control-flow pattern. The incoming instruction knows the destination vreg 928 // to set, the condition code register to branch on, the true/false values to 929 // select between, and a branch opcode to use. 930 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 931 ilist<MachineBasicBlock>::iterator It = BB; 932 ++It; 933 934 // thisMBB: 935 // ... 936 // TrueVal = ... 937 // [f]bCC copy1MBB 938 // fallthrough --> copy0MBB 939 MachineBasicBlock *thisMBB = BB; 940 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 941 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 942 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 943 MachineFunction *F = BB->getParent(); 944 F->getBasicBlockList().insert(It, copy0MBB); 945 F->getBasicBlockList().insert(It, sinkMBB); 946 // Update machine-CFG edges by first adding all successors of the current 947 // block to the new block which will contain the Phi node for the select. 948 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 949 e = BB->succ_end(); i != e; ++i) 950 sinkMBB->addSuccessor(*i); 951 // Next, remove all successors of the current block, and add the true 952 // and fallthrough blocks as its successors. 953 while(!BB->succ_empty()) 954 BB->removeSuccessor(BB->succ_begin()); 955 BB->addSuccessor(copy0MBB); 956 BB->addSuccessor(sinkMBB); 957 958 // copy0MBB: 959 // %FalseValue = ... 960 // # fallthrough to sinkMBB 961 BB = copy0MBB; 962 963 // Update machine-CFG edges 964 BB->addSuccessor(sinkMBB); 965 966 // sinkMBB: 967 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 968 // ... 969 BB = sinkMBB; 970 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) 971 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 972 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 973 974 delete MI; // The pseudo instruction is gone now. 975 return BB; 976} 977 978//===----------------------------------------------------------------------===// 979// Instruction Selector Implementation 980//===----------------------------------------------------------------------===// 981 982//===--------------------------------------------------------------------===// 983/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 984/// instructions for SelectionDAG operations. 985/// 986namespace { 987class SparcDAGToDAGISel : public SelectionDAGISel { 988 SparcTargetLowering Lowering; 989 990 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 991 /// make the right decision when generating code for different targets. 992 const SparcSubtarget &Subtarget; 993public: 994 SparcDAGToDAGISel(TargetMachine &TM) 995 : SelectionDAGISel(Lowering), Lowering(TM), 996 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 997 } 998 999 SDNode *Select(SDOperand Op); 1000 1001 // Complex Pattern Selectors. 1002 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2); 1003 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base, 1004 SDOperand &Offset); 1005 1006 /// InstructionSelectBasicBlock - This callback is invoked by 1007 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 1008 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 1009 1010 virtual const char *getPassName() const { 1011 return "SPARC DAG->DAG Pattern Instruction Selection"; 1012 } 1013 1014 // Include the pieces autogenerated from the target description. 1015#include "SparcGenDAGISel.inc" 1016}; 1017} // end anonymous namespace 1018 1019/// InstructionSelectBasicBlock - This callback is invoked by 1020/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 1021void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 1022 DEBUG(BB->dump()); 1023 1024 // Select target instructions for the DAG. 1025 DAG.setRoot(SelectRoot(DAG.getRoot())); 1026 DAG.RemoveDeadNodes(); 1027 1028 // Emit machine code to BB. 1029 ScheduleAndEmitDAG(DAG); 1030} 1031 1032bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr, 1033 SDOperand &Base, SDOperand &Offset) { 1034 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 1035 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1036 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1037 return true; 1038 } 1039 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1040 Addr.getOpcode() == ISD::TargetGlobalAddress) 1041 return false; // direct calls. 1042 1043 if (Addr.getOpcode() == ISD::ADD) { 1044 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 1045 if (Predicate_simm13(CN)) { 1046 if (FrameIndexSDNode *FIN = 1047 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 1048 // Constant offset from frame ref. 1049 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1050 } else { 1051 Base = Addr.getOperand(0); 1052 } 1053 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 1054 return true; 1055 } 1056 } 1057 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 1058 Base = Addr.getOperand(1); 1059 Offset = Addr.getOperand(0).getOperand(0); 1060 return true; 1061 } 1062 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 1063 Base = Addr.getOperand(0); 1064 Offset = Addr.getOperand(1).getOperand(0); 1065 return true; 1066 } 1067 } 1068 Base = Addr; 1069 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1070 return true; 1071} 1072 1073bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr, 1074 SDOperand &R1, SDOperand &R2) { 1075 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1076 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1077 Addr.getOpcode() == ISD::TargetGlobalAddress) 1078 return false; // direct calls. 1079 1080 if (Addr.getOpcode() == ISD::ADD) { 1081 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1082 Predicate_simm13(Addr.getOperand(1).Val)) 1083 return false; // Let the reg+imm pattern catch this! 1084 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1085 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1086 return false; // Let the reg+imm pattern catch this! 1087 R1 = Addr.getOperand(0); 1088 R2 = Addr.getOperand(1); 1089 return true; 1090 } 1091 1092 R1 = Addr; 1093 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1094 return true; 1095} 1096 1097SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { 1098 SDNode *N = Op.Val; 1099 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1100 N->getOpcode() < SPISD::FIRST_NUMBER) 1101 return NULL; // Already selected. 1102 1103 switch (N->getOpcode()) { 1104 default: break; 1105 case ISD::SDIV: 1106 case ISD::UDIV: { 1107 // FIXME: should use a custom expander to expose the SRA to the dag. 1108 SDOperand DivLHS = N->getOperand(0); 1109 SDOperand DivRHS = N->getOperand(1); 1110 AddToISelQueue(DivLHS); 1111 AddToISelQueue(DivRHS); 1112 1113 // Set the Y register to the high-part. 1114 SDOperand TopPart; 1115 if (N->getOpcode() == ISD::SDIV) { 1116 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1117 CurDAG->getTargetConstant(31, MVT::i32)), 0); 1118 } else { 1119 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1120 } 1121 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1122 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 1123 1124 // FIXME: Handle div by immediate. 1125 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1126 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 1127 TopPart); 1128 } 1129 case ISD::MULHU: 1130 case ISD::MULHS: { 1131 // FIXME: Handle mul by immediate. 1132 SDOperand MulLHS = N->getOperand(0); 1133 SDOperand MulRHS = N->getOperand(1); 1134 AddToISelQueue(MulLHS); 1135 AddToISelQueue(MulRHS); 1136 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1137 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1138 MulLHS, MulRHS); 1139 // The high part is in the Y register. 1140 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); 1141 return NULL; 1142 } 1143 } 1144 1145 return SelectCode(Op); 1146} 1147 1148 1149/// createSparcISelDag - This pass converts a legalized DAG into a 1150/// SPARC-specific DAG, ready for instruction scheduling. 1151/// 1152FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1153 return new SparcDAGToDAGISel(TM); 1154} 1155