SparcISelDAGToDAG.cpp revision 76acc872b3c63c26a83c2832ece6fa9b04786f24 
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the V8 target
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8TargetMachine.h"
16#include "llvm/Function.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/SelectionDAG.h"
19#include "llvm/CodeGen/SelectionDAGISel.h"
20#include "llvm/CodeGen/SSARegMap.h"
21#include "llvm/Target/TargetLowering.h"
22#include "llvm/Support/Debug.h"
23#include <iostream>
24using namespace llvm;
25
26//===----------------------------------------------------------------------===//
27// TargetLowering Implementation
28//===----------------------------------------------------------------------===//
29
30namespace V8ISD {
31  enum {
32    FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
33    CMPICC,   // Compare two GPR operands, set icc.
34    CMPFCC,   // Compare two FP operands, set fcc.
35    BRICC,    // Branch to dest on icc condition
36    BRFCC,    // Branch to dest on fcc condition
37
38    Hi, Lo,   // Hi/Lo operations, typically on a global address.
39  };
40}
41
42namespace {
43  class SparcV8TargetLowering : public TargetLowering {
44  public:
45    SparcV8TargetLowering(TargetMachine &TM);
46    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
47    virtual std::vector<SDOperand>
48      LowerArguments(Function &F, SelectionDAG &DAG);
49    virtual std::pair<SDOperand, SDOperand>
50      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
51                  unsigned CC,
52                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
53                  SelectionDAG &DAG);
54
55    virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
56                                    SelectionDAG &DAG);
57    virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
58                                   Value *VAListV, SelectionDAG &DAG);
59    virtual std::pair<SDOperand,SDOperand>
60      LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
61                 const Type *ArgTy, SelectionDAG &DAG);
62    virtual std::pair<SDOperand, SDOperand>
63      LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
64                              SelectionDAG &DAG);
65  };
66}
67
68SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
69  : TargetLowering(TM) {
70
71  // Set up the register classes.
72  addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
73  addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
74  addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
75
76  // Custom legalize GlobalAddress nodes into LO/HI parts.
77  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
78  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
79
80  // Sparc doesn't have sext_inreg, replace them with shl/sra
81  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16  , Expand);
82  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8   , Expand);
83  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1   , Expand);
84
85  // Sparc has no REM operation.
86  setOperationAction(ISD::UREM, MVT::i32, Expand);
87  setOperationAction(ISD::SREM, MVT::i32, Expand);
88
89  // Sparc has no select or setcc: expand to SELECT_CC.
90  setOperationAction(ISD::SELECT, MVT::i32, Expand);
91  setOperationAction(ISD::SELECT, MVT::f32, Expand);
92  setOperationAction(ISD::SELECT, MVT::f64, Expand);
93  setOperationAction(ISD::SETCC, MVT::i32, Expand);
94  setOperationAction(ISD::SETCC, MVT::f32, Expand);
95  setOperationAction(ISD::SETCC, MVT::f64, Expand);
96
97  // Sparc doesn't have BRCOND either, it has BR_CC.
98  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
99  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
100  setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
101  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
102  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
103  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
104
105  computeRegisterProperties();
106}
107
108std::vector<SDOperand>
109SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
110  MachineFunction &MF = DAG.getMachineFunction();
111  SSARegMap *RegMap = MF.getSSARegMap();
112  std::vector<SDOperand> ArgValues;
113
114  static const unsigned GPR[] = {
115    V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
116  };
117  unsigned ArgNo = 0;
118  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
119    MVT::ValueType ObjectVT = getValueType(I->getType());
120    assert(ArgNo < 6 && "Only args in regs for now");
121
122    switch (ObjectVT) {
123    default: assert(0 && "Unhandled argument type!");
124    // TODO: MVT::i64 & FP
125    case MVT::i1:
126    case MVT::i8:
127    case MVT::i16:
128    case MVT::i32: {
129      unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
130      MF.addLiveIn(GPR[ArgNo++], VReg);
131      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
132      DAG.setRoot(Arg.getValue(1));
133      if (ObjectVT != MVT::i32) {
134        unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
135                                                     : ISD::AssertZext;
136        Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
137                          DAG.getValueType(ObjectVT));
138        Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
139      }
140      ArgValues.push_back(Arg);
141      break;
142    }
143    case MVT::i64: {
144      unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
145      MF.addLiveIn(GPR[ArgNo++], VRegHi);
146      unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
147      MF.addLiveIn(GPR[ArgNo++], VRegLo);
148      SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
149      SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
150      DAG.setRoot(ArgHi.getValue(1));
151      ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
152      break;
153    }
154    }
155  }
156
157  assert(!F.isVarArg() && "Unimp");
158
159  // Finally, inform the code generator which regs we return values in.
160  switch (getValueType(F.getReturnType())) {
161  default: assert(0 && "Unknown type!");
162  case MVT::isVoid: break;
163  case MVT::i1:
164  case MVT::i8:
165  case MVT::i16:
166  case MVT::i32:
167    MF.addLiveOut(V8::I0);
168    break;
169  case MVT::i64:
170    MF.addLiveOut(V8::I0);
171    MF.addLiveOut(V8::I1);
172    break;
173  case MVT::f32:
174    MF.addLiveOut(V8::F0);
175    break;
176  case MVT::f64:
177    MF.addLiveOut(V8::D0);
178    break;
179  }
180
181  return ArgValues;
182}
183
184std::pair<SDOperand, SDOperand>
185SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
186                                   bool isVarArg, unsigned CC,
187                                   bool isTailCall, SDOperand Callee,
188                                   ArgListTy &Args, SelectionDAG &DAG) {
189  assert(0 && "Unimp");
190  abort();
191}
192
193SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
194                                               SelectionDAG &DAG) {
195  if (Op.getValueType() == MVT::i64) {
196    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
197                               DAG.getConstant(1, MVT::i32));
198    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
199                               DAG.getConstant(0, MVT::i32));
200    return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi);
201  } else {
202    return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
203  }
204}
205
206SDOperand SparcV8TargetLowering::
207LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
208             SelectionDAG &DAG) {
209
210  assert(0 && "Unimp");
211  abort();
212}
213
214std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
215LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
216           const Type *ArgTy, SelectionDAG &DAG) {
217  assert(0 && "Unimp");
218  abort();
219}
220
221std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
222LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
223                        SelectionDAG &DAG) {
224  assert(0 && "Unimp");
225  abort();
226}
227
228SDOperand SparcV8TargetLowering::
229LowerOperation(SDOperand Op, SelectionDAG &DAG) {
230  switch (Op.getOpcode()) {
231  default: assert(0 && "Should not custom lower this!");
232  case ISD::BR_CC: {
233    SDOperand Chain = Op.getOperand(0);
234    SDOperand CC = Op.getOperand(1);
235    SDOperand LHS = Op.getOperand(2);
236    SDOperand RHS = Op.getOperand(3);
237    SDOperand Dest = Op.getOperand(4);
238
239    // Get the condition flag.
240    if (LHS.getValueType() == MVT::i32) {
241      SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS);
242      return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
243    } else {
244      SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
245      return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
246    }
247  }
248  case ISD::GlobalAddress: {
249    GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
250    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
251    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
252    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
253    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
254  }
255  case ISD::ConstantPool: {
256    Constant *C = cast<ConstantPoolSDNode>(Op)->get();
257    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
258    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
259    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
260    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
261  }
262  }
263}
264
265
266//===----------------------------------------------------------------------===//
267// Instruction Selector Implementation
268//===----------------------------------------------------------------------===//
269
270//===--------------------------------------------------------------------===//
271/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
272/// instructions for SelectionDAG operations.
273///
274namespace {
275class SparcV8DAGToDAGISel : public SelectionDAGISel {
276  SparcV8TargetLowering V8Lowering;
277public:
278  SparcV8DAGToDAGISel(TargetMachine &TM)
279    : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
280
281  SDOperand Select(SDOperand Op);
282
283  // Complex Pattern Selectors.
284  bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
285  bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
286
287  /// InstructionSelectBasicBlock - This callback is invoked by
288  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
289  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
290
291  virtual const char *getPassName() const {
292    return "PowerPC DAG->DAG Pattern Instruction Selection";
293  }
294
295  // Include the pieces autogenerated from the target description.
296#include "SparcV8GenDAGISel.inc"
297};
298}  // end anonymous namespace
299
300/// InstructionSelectBasicBlock - This callback is invoked by
301/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
302void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
303  DEBUG(BB->dump());
304
305  // Select target instructions for the DAG.
306  DAG.setRoot(Select(DAG.getRoot()));
307  CodeGenMap.clear();
308  DAG.RemoveDeadNodes();
309
310  // Emit machine code to BB.
311  ScheduleAndEmitDAG(DAG);
312}
313
314bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
315                                       SDOperand &R2) {
316  if (Addr.getOpcode() == ISD::ADD) {
317    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
318        Predicate_simm13(Addr.getOperand(1).Val))
319      return false;  // Let the reg+imm pattern catch this!
320    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
321        Addr.getOperand(1).getOpcode() == V8ISD::Lo)
322      return false;  // Let the reg+imm pattern catch this!
323    R1 = Select(Addr.getOperand(0));
324    R2 = Select(Addr.getOperand(1));
325    return true;
326  }
327
328  R1 = Select(Addr);
329  R2 = CurDAG->getRegister(V8::G0, MVT::i32);
330  return true;
331}
332
333bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
334                                       SDOperand &Offset) {
335  if (Addr.getOpcode() == ISD::ADD) {
336    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
337      if (Predicate_simm13(CN)) {
338        Base = Select(Addr.getOperand(0));
339        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
340        return true;
341      }
342    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
343      Base = Select(Addr.getOperand(1));
344      Offset = Addr.getOperand(0).getOperand(0);
345      return true;
346    }
347    if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
348      Base = Select(Addr.getOperand(0));
349      Offset = Addr.getOperand(1).getOperand(0);
350      return true;
351    }
352  }
353  Base = Select(Addr);
354  Offset = CurDAG->getTargetConstant(0, MVT::i32);
355  return true;
356}
357
358
359SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
360  SDNode *N = Op.Val;
361  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
362      N->getOpcode() < V8ISD::FIRST_NUMBER)
363    return Op;   // Already selected.
364                 // If this has already been converted, use it.
365  std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
366  if (CGMI != CodeGenMap.end()) return CGMI->second;
367
368  switch (N->getOpcode()) {
369  default: break;
370  case ISD::BasicBlock:         return CodeGenMap[Op] = Op;
371  case V8ISD::CMPICC: {
372    // FIXME: Handle compare with immediate.
373    SDOperand LHS = Select(N->getOperand(0));
374    SDOperand RHS = Select(N->getOperand(1));
375    SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
376                                             LHS, RHS);
377    return CodeGenMap[Op] = Result.getValue(1);
378  }
379  case ISD::ADD_PARTS: {
380    SDOperand LHSL = Select(N->getOperand(0));
381    SDOperand LHSH = Select(N->getOperand(1));
382    SDOperand RHSL = Select(N->getOperand(2));
383    SDOperand RHSH = Select(N->getOperand(3));
384    // FIXME, handle immediate RHS.
385    SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
386                                          LHSL, RHSL);
387    SDOperand Hi  = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
388                                          Low.getValue(1));
389    CodeGenMap[SDOperand(N, 0)] = Low;
390    CodeGenMap[SDOperand(N, 1)] = Hi;
391    return Op.ResNo ? Hi : Low;
392  }
393  case ISD::SUB_PARTS: {
394    SDOperand LHSL = Select(N->getOperand(0));
395    SDOperand LHSH = Select(N->getOperand(1));
396    SDOperand RHSL = Select(N->getOperand(2));
397    SDOperand RHSH = Select(N->getOperand(3));
398    // FIXME, handle immediate RHS.
399    SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
400                                          LHSL, RHSL);
401    SDOperand Hi  = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
402                                          Low.getValue(1));
403    CodeGenMap[SDOperand(N, 0)] = Low;
404    CodeGenMap[SDOperand(N, 1)] = Hi;
405    return Op.ResNo ? Hi : Low;
406  }
407  case ISD::SDIV:
408  case ISD::UDIV: {
409    // FIXME: should use a custom expander to expose the SRA to the dag.
410    SDOperand DivLHS = Select(N->getOperand(0));
411    SDOperand DivRHS = Select(N->getOperand(1));
412
413    // Set the Y register to the high-part.
414    SDOperand TopPart;
415    if (N->getOpcode() == ISD::SDIV) {
416      TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
417                                      CurDAG->getTargetConstant(31, MVT::i32));
418    } else {
419      TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
420    }
421    TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
422                                    CurDAG->getRegister(V8::G0, MVT::i32));
423
424    // FIXME: Handle div by immediate.
425    unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
426    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
427  }
428  case ISD::MULHU:
429  case ISD::MULHS: {
430    // FIXME: Handle mul by immediate.
431    SDOperand MulLHS = Select(N->getOperand(0));
432    SDOperand MulRHS = Select(N->getOperand(1));
433    unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
434    SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
435                                          MulLHS, MulRHS);
436    // The high part is in the Y register.
437    return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
438  }
439
440  case ISD::RET: {
441    if (N->getNumOperands() == 2) {
442      SDOperand Chain = Select(N->getOperand(0));     // Token chain.
443      SDOperand Val = Select(N->getOperand(1));
444      if (N->getOperand(1).getValueType() == MVT::i32) {
445        Chain = CurDAG->getCopyToReg(Chain, V8::I0, Val);
446      } else if (N->getOperand(1).getValueType() == MVT::f32) {
447        Chain = CurDAG->getCopyToReg(Chain, V8::F0, Val);
448      } else {
449        assert(N->getOperand(1).getValueType() == MVT::f64);
450        Chain = CurDAG->getCopyToReg(Chain, V8::D0, Val);
451      }
452      return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
453    } else if (N->getNumOperands() > 1) {
454      SDOperand Chain = Select(N->getOperand(0));     // Token chain.
455      assert(N->getOperand(1).getValueType() == MVT::i32 &&
456             N->getOperand(2).getValueType() == MVT::i32 &&
457             N->getNumOperands() == 3 && "Unknown two-register ret value!");
458      Chain = CurDAG->getCopyToReg(Chain, V8::I1, Select(N->getOperand(1)));
459      Chain = CurDAG->getCopyToReg(Chain, V8::I0, Select(N->getOperand(2)));
460      return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
461    }
462    break;  // Generated code handles the void case.
463  }
464  }
465
466  return SelectCode(Op);
467}
468
469
470/// createPPCISelDag - This pass converts a legalized DAG into a
471/// PowerPC-specific DAG, ready for instruction scheduling.
472///
473FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
474  return new SparcV8DAGToDAGISel(TM);
475}
476