SparcISelDAGToDAG.cpp revision bcc5f36765e8111c13873a0c0dc874c92385d808
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SPARC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcTargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SelectionDAGISel.h" 24#include "llvm/CodeGen/SSARegMap.h" 25#include "llvm/Target/TargetLowering.h" 26#include "llvm/Support/Debug.h" 27#include <queue> 28#include <set> 29using namespace llvm; 30 31//===----------------------------------------------------------------------===// 32// TargetLowering Implementation 33//===----------------------------------------------------------------------===// 34 35namespace SPISD { 36 enum { 37 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 38 CMPICC, // Compare two GPR operands, set icc. 39 CMPFCC, // Compare two FP operands, set fcc. 40 BRICC, // Branch to dest on icc condition 41 BRFCC, // Branch to dest on fcc condition 42 SELECT_ICC, // Select between two values using the current ICC flags. 43 SELECT_FCC, // Select between two values using the current FCC flags. 44 45 Hi, Lo, // Hi/Lo operations, typically on a global address. 46 47 FTOI, // FP to Int within a FP register. 48 ITOF, // Int to FP within a FP register. 49 50 CALL, // A call instruction. 51 RET_FLAG // Return with a flag operand. 52 }; 53} 54 55/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 56/// condition. 57static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 58 switch (CC) { 59 default: assert(0 && "Unknown integer condition code!"); 60 case ISD::SETEQ: return SPCC::ICC_E; 61 case ISD::SETNE: return SPCC::ICC_NE; 62 case ISD::SETLT: return SPCC::ICC_L; 63 case ISD::SETGT: return SPCC::ICC_G; 64 case ISD::SETLE: return SPCC::ICC_LE; 65 case ISD::SETGE: return SPCC::ICC_GE; 66 case ISD::SETULT: return SPCC::ICC_CS; 67 case ISD::SETULE: return SPCC::ICC_LEU; 68 case ISD::SETUGT: return SPCC::ICC_GU; 69 case ISD::SETUGE: return SPCC::ICC_CC; 70 } 71} 72 73/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 74/// FCC condition. 75static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 76 switch (CC) { 77 default: assert(0 && "Unknown fp condition code!"); 78 case ISD::SETEQ: 79 case ISD::SETOEQ: return SPCC::FCC_E; 80 case ISD::SETNE: 81 case ISD::SETUNE: return SPCC::FCC_NE; 82 case ISD::SETLT: 83 case ISD::SETOLT: return SPCC::FCC_L; 84 case ISD::SETGT: 85 case ISD::SETOGT: return SPCC::FCC_G; 86 case ISD::SETLE: 87 case ISD::SETOLE: return SPCC::FCC_LE; 88 case ISD::SETGE: 89 case ISD::SETOGE: return SPCC::FCC_GE; 90 case ISD::SETULT: return SPCC::FCC_UL; 91 case ISD::SETULE: return SPCC::FCC_ULE; 92 case ISD::SETUGT: return SPCC::FCC_UG; 93 case ISD::SETUGE: return SPCC::FCC_UGE; 94 case ISD::SETUO: return SPCC::FCC_U; 95 case ISD::SETO: return SPCC::FCC_O; 96 case ISD::SETONE: return SPCC::FCC_LG; 97 case ISD::SETUEQ: return SPCC::FCC_UE; 98 } 99} 100 101namespace { 102 class SparcTargetLowering : public TargetLowering { 103 int VarArgsFrameOffset; // Frame offset to start of varargs area. 104 public: 105 SparcTargetLowering(TargetMachine &TM); 106 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 107 108 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 109 /// in Mask are known to be either zero or one and return them in the 110 /// KnownZero/KnownOne bitsets. 111 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 112 uint64_t Mask, 113 uint64_t &KnownZero, 114 uint64_t &KnownOne, 115 unsigned Depth = 0) const; 116 117 virtual std::vector<SDOperand> 118 LowerArguments(Function &F, SelectionDAG &DAG); 119 virtual std::pair<SDOperand, SDOperand> 120 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 121 bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, 122 ArgListTy &Args, SelectionDAG &DAG); 123 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 124 MachineBasicBlock *MBB); 125 126 virtual const char *getTargetNodeName(unsigned Opcode) const; 127 }; 128} 129 130SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 131 : TargetLowering(TM) { 132 133 // Set up the register classes. 134 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 135 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 136 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 137 138 // Turn FP extload into load/fextend 139 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 140 141 // Custom legalize GlobalAddress nodes into LO/HI parts. 142 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 143 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 144 145 // Sparc doesn't have sext_inreg, replace them with shl/sra 146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 147 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 148 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 149 150 // Sparc has no REM operation. 151 setOperationAction(ISD::UREM, MVT::i32, Expand); 152 setOperationAction(ISD::SREM, MVT::i32, Expand); 153 154 // Custom expand fp<->sint 155 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 156 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 157 158 // Expand fp<->uint 159 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 160 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 161 162 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 163 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 164 165 // Sparc has no select or setcc: expand to SELECT_CC. 166 setOperationAction(ISD::SELECT, MVT::i32, Expand); 167 setOperationAction(ISD::SELECT, MVT::f32, Expand); 168 setOperationAction(ISD::SELECT, MVT::f64, Expand); 169 setOperationAction(ISD::SETCC, MVT::i32, Expand); 170 setOperationAction(ISD::SETCC, MVT::f32, Expand); 171 setOperationAction(ISD::SETCC, MVT::f64, Expand); 172 173 // Sparc doesn't have BRCOND either, it has BR_CC. 174 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 175 setOperationAction(ISD::BRIND, MVT::Other, Expand); 176 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 177 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 178 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 179 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 180 181 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 182 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 183 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 184 185 // SPARC has no intrinsics for these particular operations. 186 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 187 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 188 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 189 190 setOperationAction(ISD::FSIN , MVT::f64, Expand); 191 setOperationAction(ISD::FCOS , MVT::f64, Expand); 192 setOperationAction(ISD::FSIN , MVT::f32, Expand); 193 setOperationAction(ISD::FCOS , MVT::f32, Expand); 194 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 195 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 196 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 197 setOperationAction(ISD::ROTL , MVT::i32, Expand); 198 setOperationAction(ISD::ROTR , MVT::i32, Expand); 199 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 200 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 201 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 202 203 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 204 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 205 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 206 207 // We don't have line number support yet. 208 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 209 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 210 setOperationAction(ISD::LABEL, MVT::Other, Expand); 211 212 // RET must be custom lowered, to meet ABI requirements 213 setOperationAction(ISD::RET , MVT::Other, Custom); 214 215 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 216 setOperationAction(ISD::VASTART , MVT::Other, Custom); 217 // VAARG needs to be lowered to not do unaligned accesses for doubles. 218 setOperationAction(ISD::VAARG , MVT::Other, Custom); 219 220 // Use the default implementation. 221 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 222 setOperationAction(ISD::VAEND , MVT::Other, Expand); 223 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 224 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 225 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 226 227 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 228 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 229 230 setStackPointerRegisterToSaveRestore(SP::O6); 231 232 if (TM.getSubtarget<SparcSubtarget>().isV9()) { 233 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 234 } 235 236 computeRegisterProperties(); 237} 238 239const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 240 switch (Opcode) { 241 default: return 0; 242 case SPISD::CMPICC: return "SPISD::CMPICC"; 243 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 244 case SPISD::BRICC: return "SPISD::BRICC"; 245 case SPISD::BRFCC: return "SPISD::BRFCC"; 246 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 247 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 248 case SPISD::Hi: return "SPISD::Hi"; 249 case SPISD::Lo: return "SPISD::Lo"; 250 case SPISD::FTOI: return "SPISD::FTOI"; 251 case SPISD::ITOF: return "SPISD::ITOF"; 252 case SPISD::CALL: return "SPISD::CALL"; 253 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 254 } 255} 256 257/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 258/// be zero. Op is expected to be a target specific node. Used by DAG 259/// combiner. 260void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 261 uint64_t Mask, 262 uint64_t &KnownZero, 263 uint64_t &KnownOne, 264 unsigned Depth) const { 265 uint64_t KnownZero2, KnownOne2; 266 KnownZero = KnownOne = 0; // Don't know anything. 267 268 switch (Op.getOpcode()) { 269 default: break; 270 case SPISD::SELECT_ICC: 271 case SPISD::SELECT_FCC: 272 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 273 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 274 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 275 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 276 277 // Only known if known in both the LHS and RHS. 278 KnownOne &= KnownOne2; 279 KnownZero &= KnownZero2; 280 break; 281 } 282} 283 284/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 285/// either one or two GPRs, including FP values. TODO: we should pass FP values 286/// in FP registers for fastcc functions. 287std::vector<SDOperand> 288SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 289 MachineFunction &MF = DAG.getMachineFunction(); 290 SSARegMap *RegMap = MF.getSSARegMap(); 291 std::vector<SDOperand> ArgValues; 292 293 static const unsigned ArgRegs[] = { 294 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 295 }; 296 297 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 298 unsigned ArgOffset = 68; 299 300 SDOperand Root = DAG.getRoot(); 301 std::vector<SDOperand> OutChains; 302 303 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 304 MVT::ValueType ObjectVT = getValueType(I->getType()); 305 306 switch (ObjectVT) { 307 default: assert(0 && "Unhandled argument type!"); 308 case MVT::i1: 309 case MVT::i8: 310 case MVT::i16: 311 case MVT::i32: 312 if (I->use_empty()) { // Argument is dead. 313 if (CurArgReg < ArgRegEnd) ++CurArgReg; 314 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 315 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 316 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 317 MF.addLiveIn(*CurArgReg++, VReg); 318 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 319 if (ObjectVT != MVT::i32) { 320 unsigned AssertOp = ISD::AssertSext; 321 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 322 DAG.getValueType(ObjectVT)); 323 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 324 } 325 ArgValues.push_back(Arg); 326 } else { 327 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 328 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 329 SDOperand Load; 330 if (ObjectVT == MVT::i32) { 331 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 332 } else { 333 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 334 335 // Sparc is big endian, so add an offset based on the ObjectVT. 336 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 337 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 338 DAG.getConstant(Offset, MVT::i32)); 339 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 340 NULL, 0, ObjectVT); 341 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 342 } 343 ArgValues.push_back(Load); 344 } 345 346 ArgOffset += 4; 347 break; 348 case MVT::f32: 349 if (I->use_empty()) { // Argument is dead. 350 if (CurArgReg < ArgRegEnd) ++CurArgReg; 351 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 352 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 353 // FP value is passed in an integer register. 354 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 355 MF.addLiveIn(*CurArgReg++, VReg); 356 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 357 358 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 359 ArgValues.push_back(Arg); 360 } else { 361 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 362 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 363 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); 364 ArgValues.push_back(Load); 365 } 366 ArgOffset += 4; 367 break; 368 369 case MVT::i64: 370 case MVT::f64: 371 if (I->use_empty()) { // Argument is dead. 372 if (CurArgReg < ArgRegEnd) ++CurArgReg; 373 if (CurArgReg < ArgRegEnd) ++CurArgReg; 374 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 375 } else if (/* FIXME: Apparently this isn't safe?? */ 376 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 377 ((CurArgReg-ArgRegs) & 1) == 0) { 378 // If this is a double argument and the whole thing lives on the stack, 379 // and the argument is aligned, load the double straight from the stack. 380 // We can't do a load in cases like void foo([6ints], int,double), 381 // because the double wouldn't be aligned! 382 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 383 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 384 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); 385 } else { 386 SDOperand HiVal; 387 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 388 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 389 MF.addLiveIn(*CurArgReg++, VRegHi); 390 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 391 } else { 392 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 393 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 394 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 395 } 396 397 SDOperand LoVal; 398 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 399 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 400 MF.addLiveIn(*CurArgReg++, VRegLo); 401 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 402 } else { 403 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 404 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 405 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 406 } 407 408 // Compose the two halves together into an i64 unit. 409 SDOperand WholeValue = 410 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 411 412 // If we want a double, do a bit convert. 413 if (ObjectVT == MVT::f64) 414 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 415 416 ArgValues.push_back(WholeValue); 417 } 418 ArgOffset += 8; 419 break; 420 } 421 } 422 423 // Store remaining ArgRegs to the stack if this is a varargs function. 424 if (F.getFunctionType()->isVarArg()) { 425 // Remember the vararg offset for the va_start implementation. 426 VarArgsFrameOffset = ArgOffset; 427 428 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 429 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 430 MF.addLiveIn(*CurArgReg, VReg); 431 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 432 433 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 434 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 435 436 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); 437 ArgOffset += 4; 438 } 439 } 440 441 if (!OutChains.empty()) 442 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 443 &OutChains[0], OutChains.size())); 444 445 // Finally, inform the code generator which regs we return values in. 446 switch (getValueType(F.getReturnType())) { 447 default: assert(0 && "Unknown type!"); 448 case MVT::isVoid: break; 449 case MVT::i1: 450 case MVT::i8: 451 case MVT::i16: 452 case MVT::i32: 453 MF.addLiveOut(SP::I0); 454 break; 455 case MVT::i64: 456 MF.addLiveOut(SP::I0); 457 MF.addLiveOut(SP::I1); 458 break; 459 case MVT::f32: 460 MF.addLiveOut(SP::F0); 461 break; 462 case MVT::f64: 463 MF.addLiveOut(SP::D0); 464 break; 465 } 466 467 return ArgValues; 468} 469 470std::pair<SDOperand, SDOperand> 471SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 472 bool RetTyIsSigned, bool isVarArg, unsigned CC, 473 bool isTailCall, SDOperand Callee, 474 ArgListTy &Args, SelectionDAG &DAG) { 475 // Count the size of the outgoing arguments. 476 unsigned ArgsSize = 0; 477 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 478 switch (getValueType(Args[i].Ty)) { 479 default: assert(0 && "Unknown value type!"); 480 case MVT::i1: 481 case MVT::i8: 482 case MVT::i16: 483 case MVT::i32: 484 case MVT::f32: 485 ArgsSize += 4; 486 break; 487 case MVT::i64: 488 case MVT::f64: 489 ArgsSize += 8; 490 break; 491 } 492 } 493 if (ArgsSize > 4*6) 494 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 495 else 496 ArgsSize = 0; 497 498 // Keep stack frames 8-byte aligned. 499 ArgsSize = (ArgsSize+7) & ~7; 500 501 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 502 503 SDOperand StackPtr; 504 std::vector<SDOperand> Stores; 505 std::vector<SDOperand> RegValuesToPass; 506 unsigned ArgOffset = 68; 507 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 508 SDOperand Val = Args[i].Node; 509 MVT::ValueType ObjectVT = Val.getValueType(); 510 SDOperand ValToStore(0, 0); 511 unsigned ObjSize; 512 switch (ObjectVT) { 513 default: assert(0 && "Unhandled argument type!"); 514 case MVT::i1: 515 case MVT::i8: 516 case MVT::i16: { 517 // Promote the integer to 32-bits. If the input type is signed, use a 518 // sign extend, otherwise use a zero extend. 519 ISD::NodeType ExtendKind = ISD::ZERO_EXTEND; 520 if (Args[i].isSigned) 521 ExtendKind = ISD::SIGN_EXTEND; 522 Val = DAG.getNode(ExtendKind, MVT::i32, Val); 523 // FALL THROUGH 524 } 525 case MVT::i32: 526 ObjSize = 4; 527 528 if (RegValuesToPass.size() >= 6) { 529 ValToStore = Val; 530 } else { 531 RegValuesToPass.push_back(Val); 532 } 533 break; 534 case MVT::f32: 535 ObjSize = 4; 536 if (RegValuesToPass.size() >= 6) { 537 ValToStore = Val; 538 } else { 539 // Convert this to a FP value in an int reg. 540 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 541 RegValuesToPass.push_back(Val); 542 } 543 break; 544 case MVT::f64: 545 ObjSize = 8; 546 // If we can store this directly into the outgoing slot, do so. We can 547 // do this when all ArgRegs are used and if the outgoing slot is aligned. 548 // FIXME: McGill/misr fails with this. 549 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 550 ValToStore = Val; 551 break; 552 } 553 554 // Otherwise, convert this to a FP value in int regs. 555 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 556 // FALL THROUGH 557 case MVT::i64: 558 ObjSize = 8; 559 if (RegValuesToPass.size() >= 6) { 560 ValToStore = Val; // Whole thing is passed in memory. 561 break; 562 } 563 564 // Split the value into top and bottom part. Top part goes in a reg. 565 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 566 DAG.getConstant(1, MVT::i32)); 567 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 568 DAG.getConstant(0, MVT::i32)); 569 RegValuesToPass.push_back(Hi); 570 571 if (RegValuesToPass.size() >= 6) { 572 ValToStore = Lo; 573 ArgOffset += 4; 574 ObjSize = 4; 575 } else { 576 RegValuesToPass.push_back(Lo); 577 } 578 break; 579 } 580 581 if (ValToStore.Val) { 582 if (!StackPtr.Val) { 583 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 584 } 585 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 586 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 587 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); 588 } 589 ArgOffset += ObjSize; 590 } 591 592 // Emit all stores, make sure the occur before any copies into physregs. 593 if (!Stores.empty()) 594 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); 595 596 static const unsigned ArgRegs[] = { 597 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 598 }; 599 600 // Build a sequence of copy-to-reg nodes chained together with token chain 601 // and flag operands which copy the outgoing args into O[0-5]. 602 SDOperand InFlag; 603 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 604 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 605 InFlag = Chain.getValue(1); 606 } 607 608 // If the callee is a GlobalAddress node (quite common, every direct call is) 609 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 610 // Likewise ExternalSymbol -> TargetExternalSymbol. 611 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 612 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 613 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 614 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 615 616 std::vector<MVT::ValueType> NodeTys; 617 NodeTys.push_back(MVT::Other); // Returns a chain 618 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 619 SDOperand Ops[] = { Chain, Callee, InFlag }; 620 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); 621 InFlag = Chain.getValue(1); 622 623 MVT::ValueType RetTyVT = getValueType(RetTy); 624 SDOperand RetVal; 625 if (RetTyVT != MVT::isVoid) { 626 switch (RetTyVT) { 627 default: assert(0 && "Unknown value type to return!"); 628 case MVT::i1: 629 case MVT::i8: 630 case MVT::i16: { 631 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 632 Chain = RetVal.getValue(1); 633 634 // Add a note to keep track of whether it is sign or zero extended. 635 ISD::NodeType AssertKind = ISD::AssertZext; 636 if (RetTyIsSigned) 637 AssertKind = ISD::AssertSext; 638 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal, 639 DAG.getValueType(RetTyVT)); 640 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 641 break; 642 } 643 case MVT::i32: 644 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 645 Chain = RetVal.getValue(1); 646 break; 647 case MVT::f32: 648 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 649 Chain = RetVal.getValue(1); 650 break; 651 case MVT::f64: 652 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 653 Chain = RetVal.getValue(1); 654 break; 655 case MVT::i64: 656 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 657 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 658 Lo.getValue(2)); 659 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 660 Chain = Hi.getValue(1); 661 break; 662 } 663 } 664 665 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 666 DAG.getConstant(ArgsSize, getPointerTy())); 667 668 return std::make_pair(RetVal, Chain); 669} 670 671// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 672// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 673static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 674 ISD::CondCode CC, unsigned &SPCC) { 675 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 676 CC == ISD::SETNE && 677 ((LHS.getOpcode() == SPISD::SELECT_ICC && 678 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 679 (LHS.getOpcode() == SPISD::SELECT_FCC && 680 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 681 isa<ConstantSDNode>(LHS.getOperand(0)) && 682 isa<ConstantSDNode>(LHS.getOperand(1)) && 683 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 684 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 685 SDOperand CMPCC = LHS.getOperand(3); 686 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 687 LHS = CMPCC.getOperand(0); 688 RHS = CMPCC.getOperand(1); 689 } 690} 691 692 693SDOperand SparcTargetLowering:: 694LowerOperation(SDOperand Op, SelectionDAG &DAG) { 695 switch (Op.getOpcode()) { 696 default: assert(0 && "Should not custom lower this!"); 697 case ISD::GlobalAddress: { 698 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 699 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 700 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 701 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 702 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 703 } 704 case ISD::ConstantPool: { 705 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal(); 706 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 707 cast<ConstantPoolSDNode>(Op)->getAlignment()); 708 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 709 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 710 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 711 } 712 case ISD::FP_TO_SINT: 713 // Convert the fp value to integer in an FP register. 714 assert(Op.getValueType() == MVT::i32); 715 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 716 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 717 case ISD::SINT_TO_FP: { 718 assert(Op.getOperand(0).getValueType() == MVT::i32); 719 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 720 // Convert the int value to FP in an FP register. 721 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 722 } 723 case ISD::BR_CC: { 724 SDOperand Chain = Op.getOperand(0); 725 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 726 SDOperand LHS = Op.getOperand(2); 727 SDOperand RHS = Op.getOperand(3); 728 SDOperand Dest = Op.getOperand(4); 729 unsigned Opc, SPCC = ~0U; 730 731 // If this is a br_cc of a "setcc", and if the setcc got lowered into 732 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 733 LookThroughSetCC(LHS, RHS, CC, SPCC); 734 735 // Get the condition flag. 736 SDOperand CompareFlag; 737 if (LHS.getValueType() == MVT::i32) { 738 std::vector<MVT::ValueType> VTs; 739 VTs.push_back(MVT::i32); 740 VTs.push_back(MVT::Flag); 741 SDOperand Ops[2] = { LHS, RHS }; 742 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 743 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 744 Opc = SPISD::BRICC; 745 } else { 746 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 747 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 748 Opc = SPISD::BRFCC; 749 } 750 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 751 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 752 } 753 case ISD::SELECT_CC: { 754 SDOperand LHS = Op.getOperand(0); 755 SDOperand RHS = Op.getOperand(1); 756 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 757 SDOperand TrueVal = Op.getOperand(2); 758 SDOperand FalseVal = Op.getOperand(3); 759 unsigned Opc, SPCC = ~0U; 760 761 // If this is a select_cc of a "setcc", and if the setcc got lowered into 762 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 763 LookThroughSetCC(LHS, RHS, CC, SPCC); 764 765 SDOperand CompareFlag; 766 if (LHS.getValueType() == MVT::i32) { 767 std::vector<MVT::ValueType> VTs; 768 VTs.push_back(LHS.getValueType()); // subcc returns a value 769 VTs.push_back(MVT::Flag); 770 SDOperand Ops[2] = { LHS, RHS }; 771 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 772 Opc = SPISD::SELECT_ICC; 773 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 774 } else { 775 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 776 Opc = SPISD::SELECT_FCC; 777 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 778 } 779 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 780 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 781 } 782 case ISD::VASTART: { 783 // vastart just stores the address of the VarArgsFrameIndex slot into the 784 // memory location argument. 785 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 786 DAG.getRegister(SP::I6, MVT::i32), 787 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 788 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 789 return DAG.getStore(Op.getOperand(0), Offset, 790 Op.getOperand(1), SV->getValue(), SV->getOffset()); 791 } 792 case ISD::VAARG: { 793 SDNode *Node = Op.Val; 794 MVT::ValueType VT = Node->getValueType(0); 795 SDOperand InChain = Node->getOperand(0); 796 SDOperand VAListPtr = Node->getOperand(1); 797 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 798 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, 799 SV->getValue(), SV->getOffset()); 800 // Increment the pointer, VAList, to the next vaarg 801 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 802 DAG.getConstant(MVT::getSizeInBits(VT)/8, 803 getPointerTy())); 804 // Store the incremented VAList to the legalized pointer 805 InChain = DAG.getStore(VAList.getValue(1), NextPtr, 806 VAListPtr, SV->getValue(), SV->getOffset()); 807 // Load the actual argument out of the pointer VAList, unless this is an 808 // f64 load. 809 if (VT != MVT::f64) { 810 return DAG.getLoad(VT, InChain, VAList, NULL, 0); 811 } else { 812 // Otherwise, load it as i64, then do a bitconvert. 813 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); 814 std::vector<MVT::ValueType> Tys; 815 Tys.push_back(MVT::f64); 816 Tys.push_back(MVT::Other); 817 // Bit-Convert the value to f64. 818 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 819 V.getValue(1) }; 820 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 821 } 822 } 823 case ISD::DYNAMIC_STACKALLOC: { 824 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 825 SDOperand Size = Op.getOperand(1); // Legalize the size. 826 827 unsigned SPReg = SP::O6; 828 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 829 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 830 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 831 832 // The resultant pointer is actually 16 words from the bottom of the stack, 833 // to provide a register spill area. 834 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 835 DAG.getConstant(96, MVT::i32)); 836 std::vector<MVT::ValueType> Tys; 837 Tys.push_back(MVT::i32); 838 Tys.push_back(MVT::Other); 839 SDOperand Ops[2] = { NewVal, Chain }; 840 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 841 } 842 case ISD::RET: { 843 SDOperand Copy; 844 845 switch(Op.getNumOperands()) { 846 default: 847 assert(0 && "Do not know how to return this many arguments!"); 848 abort(); 849 case 1: 850 return SDOperand(); // ret void is legal 851 case 3: { 852 unsigned ArgReg; 853 switch(Op.getOperand(1).getValueType()) { 854 default: assert(0 && "Unknown type to return!"); 855 case MVT::i32: ArgReg = SP::I0; break; 856 case MVT::f32: ArgReg = SP::F0; break; 857 case MVT::f64: ArgReg = SP::D0; break; 858 } 859 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 860 SDOperand()); 861 break; 862 } 863 case 5: 864 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 865 SDOperand()); 866 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 867 break; 868 } 869 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 870 } 871 // Frame & Return address. Currently unimplemented 872 case ISD::RETURNADDR: break; 873 case ISD::FRAMEADDR: break; 874 } 875 return SDOperand(); 876} 877 878MachineBasicBlock * 879SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 880 MachineBasicBlock *BB) { 881 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 882 unsigned BROpcode; 883 unsigned CC; 884 // Figure out the conditional branch opcode to use for this select_cc. 885 switch (MI->getOpcode()) { 886 default: assert(0 && "Unknown SELECT_CC!"); 887 case SP::SELECT_CC_Int_ICC: 888 case SP::SELECT_CC_FP_ICC: 889 case SP::SELECT_CC_DFP_ICC: 890 BROpcode = SP::BCOND; 891 break; 892 case SP::SELECT_CC_Int_FCC: 893 case SP::SELECT_CC_FP_FCC: 894 case SP::SELECT_CC_DFP_FCC: 895 BROpcode = SP::FBCOND; 896 break; 897 } 898 899 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue(); 900 901 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 902 // control-flow pattern. The incoming instruction knows the destination vreg 903 // to set, the condition code register to branch on, the true/false values to 904 // select between, and a branch opcode to use. 905 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 906 ilist<MachineBasicBlock>::iterator It = BB; 907 ++It; 908 909 // thisMBB: 910 // ... 911 // TrueVal = ... 912 // [f]bCC copy1MBB 913 // fallthrough --> copy0MBB 914 MachineBasicBlock *thisMBB = BB; 915 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 916 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 917 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 918 MachineFunction *F = BB->getParent(); 919 F->getBasicBlockList().insert(It, copy0MBB); 920 F->getBasicBlockList().insert(It, sinkMBB); 921 // Update machine-CFG edges by first adding all successors of the current 922 // block to the new block which will contain the Phi node for the select. 923 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 924 e = BB->succ_end(); i != e; ++i) 925 sinkMBB->addSuccessor(*i); 926 // Next, remove all successors of the current block, and add the true 927 // and fallthrough blocks as its successors. 928 while(!BB->succ_empty()) 929 BB->removeSuccessor(BB->succ_begin()); 930 BB->addSuccessor(copy0MBB); 931 BB->addSuccessor(sinkMBB); 932 933 // copy0MBB: 934 // %FalseValue = ... 935 // # fallthrough to sinkMBB 936 BB = copy0MBB; 937 938 // Update machine-CFG edges 939 BB->addSuccessor(sinkMBB); 940 941 // sinkMBB: 942 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 943 // ... 944 BB = sinkMBB; 945 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) 946 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 947 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 948 949 delete MI; // The pseudo instruction is gone now. 950 return BB; 951} 952 953//===----------------------------------------------------------------------===// 954// Instruction Selector Implementation 955//===----------------------------------------------------------------------===// 956 957//===--------------------------------------------------------------------===// 958/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 959/// instructions for SelectionDAG operations. 960/// 961namespace { 962class SparcDAGToDAGISel : public SelectionDAGISel { 963 SparcTargetLowering Lowering; 964 965 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 966 /// make the right decision when generating code for different targets. 967 const SparcSubtarget &Subtarget; 968public: 969 SparcDAGToDAGISel(TargetMachine &TM) 970 : SelectionDAGISel(Lowering), Lowering(TM), 971 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 972 } 973 974 SDNode *Select(SDOperand Op); 975 976 // Complex Pattern Selectors. 977 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2); 978 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base, 979 SDOperand &Offset); 980 981 /// InstructionSelectBasicBlock - This callback is invoked by 982 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 983 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 984 985 virtual const char *getPassName() const { 986 return "SPARC DAG->DAG Pattern Instruction Selection"; 987 } 988 989 // Include the pieces autogenerated from the target description. 990#include "SparcGenDAGISel.inc" 991}; 992} // end anonymous namespace 993 994/// InstructionSelectBasicBlock - This callback is invoked by 995/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 996void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 997 DEBUG(BB->dump()); 998 999 // Select target instructions for the DAG. 1000 DAG.setRoot(SelectRoot(DAG.getRoot())); 1001 DAG.RemoveDeadNodes(); 1002 1003 // Emit machine code to BB. 1004 ScheduleAndEmitDAG(DAG); 1005} 1006 1007bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr, 1008 SDOperand &Base, SDOperand &Offset) { 1009 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 1010 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1011 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1012 return true; 1013 } 1014 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1015 Addr.getOpcode() == ISD::TargetGlobalAddress) 1016 return false; // direct calls. 1017 1018 if (Addr.getOpcode() == ISD::ADD) { 1019 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 1020 if (Predicate_simm13(CN)) { 1021 if (FrameIndexSDNode *FIN = 1022 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 1023 // Constant offset from frame ref. 1024 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1025 } else { 1026 Base = Addr.getOperand(0); 1027 } 1028 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 1029 return true; 1030 } 1031 } 1032 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 1033 Base = Addr.getOperand(1); 1034 Offset = Addr.getOperand(0).getOperand(0); 1035 return true; 1036 } 1037 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 1038 Base = Addr.getOperand(0); 1039 Offset = Addr.getOperand(1).getOperand(0); 1040 return true; 1041 } 1042 } 1043 Base = Addr; 1044 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1045 return true; 1046} 1047 1048bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr, 1049 SDOperand &R1, SDOperand &R2) { 1050 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1051 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1052 Addr.getOpcode() == ISD::TargetGlobalAddress) 1053 return false; // direct calls. 1054 1055 if (Addr.getOpcode() == ISD::ADD) { 1056 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1057 Predicate_simm13(Addr.getOperand(1).Val)) 1058 return false; // Let the reg+imm pattern catch this! 1059 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1060 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1061 return false; // Let the reg+imm pattern catch this! 1062 R1 = Addr.getOperand(0); 1063 R2 = Addr.getOperand(1); 1064 return true; 1065 } 1066 1067 R1 = Addr; 1068 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1069 return true; 1070} 1071 1072SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { 1073 SDNode *N = Op.Val; 1074 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1075 N->getOpcode() < SPISD::FIRST_NUMBER) 1076 return NULL; // Already selected. 1077 1078 switch (N->getOpcode()) { 1079 default: break; 1080 case ISD::SDIV: 1081 case ISD::UDIV: { 1082 // FIXME: should use a custom expander to expose the SRA to the dag. 1083 SDOperand DivLHS = N->getOperand(0); 1084 SDOperand DivRHS = N->getOperand(1); 1085 AddToISelQueue(DivLHS); 1086 AddToISelQueue(DivRHS); 1087 1088 // Set the Y register to the high-part. 1089 SDOperand TopPart; 1090 if (N->getOpcode() == ISD::SDIV) { 1091 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1092 CurDAG->getTargetConstant(31, MVT::i32)), 0); 1093 } else { 1094 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1095 } 1096 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1097 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 1098 1099 // FIXME: Handle div by immediate. 1100 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1101 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 1102 TopPart); 1103 } 1104 case ISD::MULHU: 1105 case ISD::MULHS: { 1106 // FIXME: Handle mul by immediate. 1107 SDOperand MulLHS = N->getOperand(0); 1108 SDOperand MulRHS = N->getOperand(1); 1109 AddToISelQueue(MulLHS); 1110 AddToISelQueue(MulRHS); 1111 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1112 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1113 MulLHS, MulRHS); 1114 // The high part is in the Y register. 1115 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); 1116 return NULL; 1117 } 1118 } 1119 1120 return SelectCode(Op); 1121} 1122 1123 1124/// createSparcISelDag - This pass converts a legalized DAG into a 1125/// SPARC-specific DAG, ready for instruction scheduling. 1126/// 1127FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1128 return new SparcDAGToDAGISel(TM); 1129} 1130