SparcISelDAGToDAG.cpp revision bce8887ceef02a51b34814519f6c49492648eb00
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 RET_FLAG, // Return with a flag operand. 50 }; 51} 52 53namespace { 54 class SparcV8TargetLowering : public TargetLowering { 55 int VarArgsFrameOffset; // Frame offset to start of varargs area. 56 public: 57 SparcV8TargetLowering(TargetMachine &TM); 58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 59 virtual std::vector<SDOperand> 60 LowerArguments(Function &F, SelectionDAG &DAG); 61 virtual std::pair<SDOperand, SDOperand> 62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 63 unsigned CC, 64 bool isTailCall, SDOperand Callee, ArgListTy &Args, 65 SelectionDAG &DAG); 66 67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, 68 SelectionDAG &DAG); 69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, 70 Value *VAListV, SelectionDAG &DAG); 71 virtual std::pair<SDOperand,SDOperand> 72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 73 const Type *ArgTy, SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 80 virtual const char *getTargetNodeName(unsigned Opcode) const; 81 }; 82} 83 84SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 85 : TargetLowering(TM) { 86 87 // Set up the register classes. 88 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 89 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 90 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 91 92 // Custom legalize GlobalAddress nodes into LO/HI parts. 93 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 94 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 95 96 // Sparc doesn't have sext_inreg, replace them with shl/sra 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 100 101 // Sparc has no REM operation. 102 setOperationAction(ISD::UREM, MVT::i32, Expand); 103 setOperationAction(ISD::SREM, MVT::i32, Expand); 104 105 // Custom expand fp<->sint 106 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 107 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 108 109 // Expand fp<->uint 110 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 111 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 112 113 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 114 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 115 116 // Turn FP extload into load/fextend 117 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 118 119 // Sparc has no select or setcc: expand to SELECT_CC. 120 setOperationAction(ISD::SELECT, MVT::i32, Expand); 121 setOperationAction(ISD::SELECT, MVT::f32, Expand); 122 setOperationAction(ISD::SELECT, MVT::f64, Expand); 123 setOperationAction(ISD::SETCC, MVT::i32, Expand); 124 setOperationAction(ISD::SETCC, MVT::f32, Expand); 125 setOperationAction(ISD::SETCC, MVT::f64, Expand); 126 127 // Sparc doesn't have BRCOND either, it has BR_CC. 128 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 129 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 130 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 131 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 132 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 133 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 134 135 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 136 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 137 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 138 139 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 140 141 // V8 has no intrinsics for these particular operations. 142 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 143 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 144 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 145 146 setOperationAction(ISD::FSIN , MVT::f64, Expand); 147 setOperationAction(ISD::FCOS , MVT::f64, Expand); 148 setOperationAction(ISD::FSIN , MVT::f32, Expand); 149 setOperationAction(ISD::FCOS , MVT::f32, Expand); 150 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 151 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 152 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 153 setOperationAction(ISD::ROTL , MVT::i32, Expand); 154 setOperationAction(ISD::ROTR , MVT::i32, Expand); 155 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 156 157 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 158 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 159 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 160 161 // We don't have line number support yet. 162 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 163 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 164 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 165 166 // Not implemented yet. 167 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 168 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 169 170 computeRegisterProperties(); 171} 172 173const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const { 174 switch (Opcode) { 175 default: return 0; 176 case V8ISD::CMPICC: return "V8ISD::CMPICC"; 177 case V8ISD::CMPFCC: return "V8ISD::CMPFCC"; 178 case V8ISD::BRICC: return "V8ISD::BRICC"; 179 case V8ISD::BRFCC: return "V8ISD::BRFCC"; 180 case V8ISD::Hi: return "V8ISD::Hi"; 181 case V8ISD::Lo: return "V8ISD::Lo"; 182 case V8ISD::FTOI: return "V8ISD::FTOI"; 183 case V8ISD::ITOF: return "V8ISD::ITOF"; 184 case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC"; 185 case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC"; 186 case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG"; 187 } 188} 189 190/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 191/// either one or two GPRs, including FP values. TODO: we should pass FP values 192/// in FP registers for fastcc functions. 193std::vector<SDOperand> 194SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 195 MachineFunction &MF = DAG.getMachineFunction(); 196 SSARegMap *RegMap = MF.getSSARegMap(); 197 std::vector<SDOperand> ArgValues; 198 199 static const unsigned ArgRegs[] = { 200 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 201 }; 202 203 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 204 unsigned ArgOffset = 68; 205 206 SDOperand Root = DAG.getRoot(); 207 std::vector<SDOperand> OutChains; 208 209 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 210 MVT::ValueType ObjectVT = getValueType(I->getType()); 211 212 switch (ObjectVT) { 213 default: assert(0 && "Unhandled argument type!"); 214 case MVT::i1: 215 case MVT::i8: 216 case MVT::i16: 217 case MVT::i32: 218 if (I->use_empty()) { // Argument is dead. 219 if (CurArgReg < ArgRegEnd) ++CurArgReg; 220 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 221 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 222 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 223 MF.addLiveIn(*CurArgReg++, VReg); 224 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 225 if (ObjectVT != MVT::i32) { 226 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 227 : ISD::AssertZext; 228 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 229 DAG.getValueType(ObjectVT)); 230 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 231 } 232 ArgValues.push_back(Arg); 233 } else { 234 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 235 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 236 SDOperand Load; 237 if (ObjectVT == MVT::i32) { 238 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 239 } else { 240 unsigned LoadOp = 241 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 242 243 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 244 DAG.getSrcValue(0), ObjectVT); 245 } 246 ArgValues.push_back(Load); 247 } 248 249 ArgOffset += 4; 250 break; 251 case MVT::f32: 252 if (I->use_empty()) { // Argument is dead. 253 if (CurArgReg < ArgRegEnd) ++CurArgReg; 254 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 255 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 256 // FP value is passed in an integer register. 257 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 258 MF.addLiveIn(*CurArgReg++, VReg); 259 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 260 261 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 262 ArgValues.push_back(Arg); 263 } 264 ArgOffset += 4; 265 break; 266 267 case MVT::i64: 268 case MVT::f64: 269 if (I->use_empty()) { // Argument is dead. 270 if (CurArgReg < ArgRegEnd) ++CurArgReg; 271 if (CurArgReg < ArgRegEnd) ++CurArgReg; 272 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 273 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 274 ((CurArgReg-ArgRegs) & 1) == 0) { 275 // If this is a double argument and the whole thing lives on the stack, 276 // and the argument is aligned, load the double straight from the stack. 277 // We can't do a load in cases like void foo([6ints], int,double), 278 // because the double wouldn't be aligned! 279 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 280 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 281 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 282 DAG.getSrcValue(0))); 283 } else { 284 SDOperand HiVal; 285 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 286 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 287 MF.addLiveIn(*CurArgReg++, VRegHi); 288 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 289 } else { 290 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 291 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 292 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 293 } 294 295 SDOperand LoVal; 296 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 297 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 298 MF.addLiveIn(*CurArgReg++, VRegLo); 299 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 300 } else { 301 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 302 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 303 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 304 } 305 306 // Compose the two halves together into an i64 unit. 307 SDOperand WholeValue = 308 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 309 310 // If we want a double, do a bit convert. 311 if (ObjectVT == MVT::f64) 312 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 313 314 ArgValues.push_back(WholeValue); 315 } 316 ArgOffset += 8; 317 break; 318 } 319 } 320 321 // Store remaining ArgRegs to the stack if this is a varargs function. 322 if (F.getFunctionType()->isVarArg()) { 323 // Remember the vararg offset for the va_start implementation. 324 VarArgsFrameOffset = ArgOffset; 325 326 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 327 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 328 MF.addLiveIn(*CurArgReg, VReg); 329 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 330 331 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 332 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 333 334 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 335 Arg, FIPtr, DAG.getSrcValue(0))); 336 ArgOffset += 4; 337 } 338 } 339 340 if (!OutChains.empty()) 341 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 342 343 // Finally, inform the code generator which regs we return values in. 344 switch (getValueType(F.getReturnType())) { 345 default: assert(0 && "Unknown type!"); 346 case MVT::isVoid: break; 347 case MVT::i1: 348 case MVT::i8: 349 case MVT::i16: 350 case MVT::i32: 351 MF.addLiveOut(V8::I0); 352 break; 353 case MVT::i64: 354 MF.addLiveOut(V8::I0); 355 MF.addLiveOut(V8::I1); 356 break; 357 case MVT::f32: 358 MF.addLiveOut(V8::F0); 359 break; 360 case MVT::f64: 361 MF.addLiveOut(V8::D0); 362 break; 363 } 364 365 return ArgValues; 366} 367 368std::pair<SDOperand, SDOperand> 369SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 370 bool isVarArg, unsigned CC, 371 bool isTailCall, SDOperand Callee, 372 ArgListTy &Args, SelectionDAG &DAG) { 373 MachineFunction &MF = DAG.getMachineFunction(); 374 // Count the size of the outgoing arguments. 375 unsigned ArgsSize = 0; 376 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 377 switch (getValueType(Args[i].second)) { 378 default: assert(0 && "Unknown value type!"); 379 case MVT::i1: 380 case MVT::i8: 381 case MVT::i16: 382 case MVT::i32: 383 case MVT::f32: 384 ArgsSize += 4; 385 break; 386 case MVT::i64: 387 case MVT::f64: 388 ArgsSize += 8; 389 break; 390 } 391 } 392 if (ArgsSize > 4*6) 393 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 394 else 395 ArgsSize = 0; 396 397 // Keep stack frames 8-byte aligned. 398 ArgsSize = (ArgsSize+7) & ~7; 399 400 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 401 DAG.getConstant(ArgsSize, getPointerTy())); 402 403 SDOperand StackPtr, NullSV; 404 std::vector<SDOperand> Stores; 405 std::vector<SDOperand> RegValuesToPass; 406 unsigned ArgOffset = 68; 407 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 408 SDOperand Val = Args[i].first; 409 MVT::ValueType ObjectVT = Val.getValueType(); 410 SDOperand ValToStore(0, 0); 411 unsigned ObjSize; 412 switch (ObjectVT) { 413 default: assert(0 && "Unhandled argument type!"); 414 case MVT::i1: 415 case MVT::i8: 416 case MVT::i16: 417 // Promote the integer to 32-bits. If the input type is signed, use a 418 // sign extend, otherwise use a zero extend. 419 if (Args[i].second->isSigned()) 420 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 421 else 422 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 423 // FALL THROUGH 424 case MVT::i32: 425 ObjSize = 4; 426 427 if (RegValuesToPass.size() >= 6) { 428 ValToStore = Val; 429 } else { 430 RegValuesToPass.push_back(Val); 431 } 432 break; 433 case MVT::f32: 434 ObjSize = 4; 435 if (RegValuesToPass.size() >= 6) { 436 ValToStore = Val; 437 } else { 438 // Convert this to a FP value in an int reg. 439 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 440 RegValuesToPass.push_back(Val); 441 } 442 break; 443 case MVT::f64: 444 ObjSize = 8; 445 // If we can store this directly into the outgoing slot, do so. We can 446 // do this when all ArgRegs are used and if the outgoing slot is aligned. 447 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 448 ValToStore = Val; 449 break; 450 } 451 452 // Otherwise, convert this to a FP value in int regs. 453 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 454 // FALL THROUGH 455 case MVT::i64: 456 ObjSize = 8; 457 if (RegValuesToPass.size() >= 6) { 458 ValToStore = Val; // Whole thing is passed in memory. 459 break; 460 } 461 462 // Split the value into top and bottom part. Top part goes in a reg. 463 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 464 DAG.getConstant(1, MVT::i32)); 465 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 466 DAG.getConstant(0, MVT::i32)); 467 RegValuesToPass.push_back(Hi); 468 469 if (RegValuesToPass.size() >= 6) { 470 ValToStore = Lo; 471 ArgOffset += 4; 472 ObjSize = 4; 473 } else { 474 RegValuesToPass.push_back(Lo); 475 } 476 break; 477 } 478 479 if (ValToStore.Val) { 480 if (!StackPtr.Val) { 481 StackPtr = DAG.getRegister(V8::O6, MVT::i32); 482 NullSV = DAG.getSrcValue(NULL); 483 } 484 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 485 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 486 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 487 ValToStore, PtrOff, NullSV)); 488 } 489 ArgOffset += ObjSize; 490 } 491 492 // Emit all stores, make sure the occur before any copies into physregs. 493 if (!Stores.empty()) 494 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 495 496 static const unsigned ArgRegs[] = { 497 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 498 }; 499 500 // Build a sequence of copy-to-reg nodes chained together with token chain 501 // and flag operands which copy the outgoing args into O[0-5]. 502 SDOperand InFlag; 503 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 504 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 505 InFlag = Chain.getValue(1); 506 } 507 508 // If the callee is a GlobalAddress node (quite common, every direct call is) 509 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 510 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 511 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 512 513 std::vector<MVT::ValueType> NodeTys; 514 NodeTys.push_back(MVT::Other); // Returns a chain 515 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 516 if (InFlag.Val) 517 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0); 518 else 519 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0); 520 InFlag = Chain.getValue(1); 521 522 MVT::ValueType RetTyVT = getValueType(RetTy); 523 SDOperand RetVal; 524 if (RetTyVT != MVT::isVoid) { 525 switch (RetTyVT) { 526 default: assert(0 && "Unknown value type to return!"); 527 case MVT::i1: 528 case MVT::i8: 529 case MVT::i16: 530 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 531 Chain = RetVal.getValue(1); 532 533 // Add a note to keep track of whether it is sign or zero extended. 534 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 535 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 536 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 537 break; 538 case MVT::i32: 539 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 540 Chain = RetVal.getValue(1); 541 break; 542 case MVT::f32: 543 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 544 Chain = RetVal.getValue(1); 545 break; 546 case MVT::f64: 547 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 548 Chain = RetVal.getValue(1); 549 break; 550 case MVT::i64: 551 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag); 552 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 553 Lo.getValue(2)); 554 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 555 Chain = Hi.getValue(1); 556 break; 557 } 558 } 559 560 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 561 DAG.getConstant(ArgsSize, getPointerTy())); 562 563 return std::make_pair(RetVal, Chain); 564} 565 566SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 567 SelectionDAG &DAG) { 568 SDOperand Copy; 569 switch (Op.getValueType()) { 570 default: assert(0 && "Unknown type to return!"); 571 case MVT::i32: 572 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand()); 573 break; 574 case MVT::f32: 575 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand()); 576 break; 577 case MVT::f64: 578 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand()); 579 break; 580 case MVT::i64: 581 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 582 DAG.getConstant(1, MVT::i32)); 583 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 584 DAG.getConstant(0, MVT::i32)); 585 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand()); 586 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1)); 587 break; 588 } 589 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 590} 591 592SDOperand SparcV8TargetLowering:: 593LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, 594 SelectionDAG &DAG) { 595 596 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 597 DAG.getRegister(V8::I6, MVT::i32), 598 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 599 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset, 600 VAListP, DAG.getSrcValue(VAListV)); 601} 602 603std::pair<SDOperand,SDOperand> SparcV8TargetLowering:: 604LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 605 const Type *ArgTy, SelectionDAG &DAG) { 606 // Load the pointer out of the valist. 607 SDOperand Ptr = DAG.getLoad(MVT::i32, Chain, 608 VAListP, DAG.getSrcValue(VAListV)); 609 MVT::ValueType ArgVT = getValueType(ArgTy); 610 SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1), 611 Ptr, DAG.getSrcValue(NULL)); 612 // Increment the pointer. 613 Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr, 614 DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32)); 615 // Store it back to the valist. 616 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr, 617 VAListP, DAG.getSrcValue(VAListV)); 618 return std::make_pair(Val, Chain); 619} 620 621std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 622LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 623 SelectionDAG &DAG) { 624 assert(0 && "Unimp"); 625 abort(); 626} 627 628SDOperand SparcV8TargetLowering:: 629LowerOperation(SDOperand Op, SelectionDAG &DAG) { 630 switch (Op.getOpcode()) { 631 default: assert(0 && "Should not custom lower this!"); 632 case ISD::GlobalAddress: { 633 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 634 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 635 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 636 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 637 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 638 } 639 case ISD::ConstantPool: { 640 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 641 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 642 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 643 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 644 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 645 } 646 case ISD::FP_TO_SINT: 647 // Convert the fp value to integer in an FP register. 648 assert(Op.getValueType() == MVT::i32); 649 Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0)); 650 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 651 case ISD::SINT_TO_FP: { 652 assert(Op.getOperand(0).getValueType() == MVT::i32); 653 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 654 // Convert the int value to FP in an FP register. 655 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp); 656 } 657 case ISD::BR_CC: { 658 SDOperand Chain = Op.getOperand(0); 659 SDOperand CC = Op.getOperand(1); 660 SDOperand LHS = Op.getOperand(2); 661 SDOperand RHS = Op.getOperand(3); 662 SDOperand Dest = Op.getOperand(4); 663 664 // Get the condition flag. 665 if (LHS.getValueType() == MVT::i32) { 666 std::vector<MVT::ValueType> VTs; 667 VTs.push_back(MVT::i32); 668 VTs.push_back(MVT::Flag); 669 std::vector<SDOperand> Ops; 670 Ops.push_back(LHS); 671 Ops.push_back(RHS); 672 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); 673 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 674 } else { 675 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 676 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 677 } 678 } 679 case ISD::SELECT_CC: { 680 SDOperand LHS = Op.getOperand(0); 681 SDOperand RHS = Op.getOperand(1); 682 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 683 SDOperand TrueVal = Op.getOperand(2); 684 SDOperand FalseVal = Op.getOperand(3); 685 686 SDOperand CompareFlag; 687 unsigned Opc; 688 if (LHS.getValueType() == MVT::i32) { 689 std::vector<MVT::ValueType> VTs; 690 VTs.push_back(LHS.getValueType()); // subcc returns a value 691 VTs.push_back(MVT::Flag); 692 std::vector<SDOperand> Ops; 693 Ops.push_back(LHS); 694 Ops.push_back(RHS); 695 CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1); 696 Opc = V8ISD::SELECT_ICC; 697 } else { 698 CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 699 Opc = V8ISD::SELECT_FCC; 700 } 701 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 702 DAG.getConstant(CC, MVT::i32), CompareFlag); 703 } 704 case ISD::DYNAMIC_STACKALLOC: { 705 SDOperand Chain = Op.getOperand(0); 706 SDOperand Size = Op.getOperand(1); 707 708 SDOperand SP = DAG.getCopyFromReg(Chain, V8::O6, MVT::i32); 709 Chain = SP.getValue(1); 710 SDOperand Res = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); 711 Chain = DAG.getCopyToReg(Chain, V8::O6, Res); 712 713 std::vector<MVT::ValueType> VTs(Op.Val->value_begin(), Op.Val->value_end()); 714 std::vector<SDOperand> Ops; 715 Ops.push_back(Res); 716 Ops.push_back(Chain); 717 return DAG.getNode(ISD::MERGE_VALUES, VTs, Ops); 718 } 719 } 720} 721 722MachineBasicBlock * 723SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 724 MachineBasicBlock *BB) { 725 unsigned BROpcode; 726 // Figure out the conditional branch opcode to use for this select_cc. 727 switch (MI->getOpcode()) { 728 default: assert(0 && "Unknown SELECT_CC!"); 729 case V8::SELECT_CC_Int_ICC: 730 case V8::SELECT_CC_FP_ICC: 731 case V8::SELECT_CC_DFP_ICC: 732 // Integer compare. 733 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 734 default: assert(0 && "Unknown integer condition code!"); 735 case ISD::SETEQ: BROpcode = V8::BE; break; 736 case ISD::SETNE: BROpcode = V8::BNE; break; 737 case ISD::SETLT: BROpcode = V8::BL; break; 738 case ISD::SETGT: BROpcode = V8::BG; break; 739 case ISD::SETLE: BROpcode = V8::BLE; break; 740 case ISD::SETGE: BROpcode = V8::BGE; break; 741 case ISD::SETULT: BROpcode = V8::BCS; break; 742 case ISD::SETULE: BROpcode = V8::BLEU; break; 743 case ISD::SETUGT: BROpcode = V8::BGU; break; 744 case ISD::SETUGE: BROpcode = V8::BCC; break; 745 } 746 break; 747 case V8::SELECT_CC_Int_FCC: 748 case V8::SELECT_CC_FP_FCC: 749 case V8::SELECT_CC_DFP_FCC: 750 // FP compare. 751 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 752 default: assert(0 && "Unknown fp condition code!"); 753 case ISD::SETEQ: BROpcode = V8::FBE; break; 754 case ISD::SETNE: BROpcode = V8::FBNE; break; 755 case ISD::SETLT: BROpcode = V8::FBL; break; 756 case ISD::SETGT: BROpcode = V8::FBG; break; 757 case ISD::SETLE: BROpcode = V8::FBLE; break; 758 case ISD::SETGE: BROpcode = V8::FBGE; break; 759 case ISD::SETULT: BROpcode = V8::FBUL; break; 760 case ISD::SETULE: BROpcode = V8::FBULE; break; 761 case ISD::SETUGT: BROpcode = V8::FBUG; break; 762 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 763 case ISD::SETUO: BROpcode = V8::FBU; break; 764 case ISD::SETO: BROpcode = V8::FBO; break; 765 case ISD::SETONE: BROpcode = V8::FBLG; break; 766 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 767 } 768 break; 769 } 770 771 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 772 // control-flow pattern. The incoming instruction knows the destination vreg 773 // to set, the condition code register to branch on, the true/false values to 774 // select between, and a branch opcode to use. 775 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 776 ilist<MachineBasicBlock>::iterator It = BB; 777 ++It; 778 779 // thisMBB: 780 // ... 781 // TrueVal = ... 782 // [f]bCC copy1MBB 783 // fallthrough --> copy0MBB 784 MachineBasicBlock *thisMBB = BB; 785 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 786 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 787 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 788 MachineFunction *F = BB->getParent(); 789 F->getBasicBlockList().insert(It, copy0MBB); 790 F->getBasicBlockList().insert(It, sinkMBB); 791 // Update machine-CFG edges 792 BB->addSuccessor(copy0MBB); 793 BB->addSuccessor(sinkMBB); 794 795 // copy0MBB: 796 // %FalseValue = ... 797 // # fallthrough to sinkMBB 798 BB = copy0MBB; 799 800 // Update machine-CFG edges 801 BB->addSuccessor(sinkMBB); 802 803 // sinkMBB: 804 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 805 // ... 806 BB = sinkMBB; 807 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 808 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 809 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 810 811 delete MI; // The pseudo instruction is gone now. 812 return BB; 813} 814 815//===----------------------------------------------------------------------===// 816// Instruction Selector Implementation 817//===----------------------------------------------------------------------===// 818 819//===--------------------------------------------------------------------===// 820/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine 821/// instructions for SelectionDAG operations. 822/// 823namespace { 824class SparcV8DAGToDAGISel : public SelectionDAGISel { 825 SparcV8TargetLowering V8Lowering; 826public: 827 SparcV8DAGToDAGISel(TargetMachine &TM) 828 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 829 830 SDOperand Select(SDOperand Op); 831 832 // Complex Pattern Selectors. 833 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 834 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 835 836 /// InstructionSelectBasicBlock - This callback is invoked by 837 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 838 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 839 840 virtual const char *getPassName() const { 841 return "PowerPC DAG->DAG Pattern Instruction Selection"; 842 } 843 844 // Include the pieces autogenerated from the target description. 845#include "SparcV8GenDAGISel.inc" 846}; 847} // end anonymous namespace 848 849/// InstructionSelectBasicBlock - This callback is invoked by 850/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 851void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 852 DEBUG(BB->dump()); 853 854 // Select target instructions for the DAG. 855 DAG.setRoot(Select(DAG.getRoot())); 856 CodeGenMap.clear(); 857 DAG.RemoveDeadNodes(); 858 859 // Emit machine code to BB. 860 ScheduleAndEmitDAG(DAG); 861} 862 863bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 864 SDOperand &Offset) { 865 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 866 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 867 Offset = CurDAG->getTargetConstant(0, MVT::i32); 868 return true; 869 } 870 871 if (Addr.getOpcode() == ISD::ADD) { 872 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 873 if (Predicate_simm13(CN)) { 874 if (FrameIndexSDNode *FIN = 875 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 876 // Constant offset from frame ref. 877 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 878 } else { 879 Base = Select(Addr.getOperand(0)); 880 } 881 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 882 return true; 883 } 884 } 885 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 886 Base = Select(Addr.getOperand(1)); 887 Offset = Addr.getOperand(0).getOperand(0); 888 return true; 889 } 890 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 891 Base = Select(Addr.getOperand(0)); 892 Offset = Addr.getOperand(1).getOperand(0); 893 return true; 894 } 895 } 896 Base = Select(Addr); 897 Offset = CurDAG->getTargetConstant(0, MVT::i32); 898 return true; 899} 900 901bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 902 SDOperand &R2) { 903 if (Addr.getOpcode() == ISD::FrameIndex) return false; 904 if (Addr.getOpcode() == ISD::ADD) { 905 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 906 Predicate_simm13(Addr.getOperand(1).Val)) 907 return false; // Let the reg+imm pattern catch this! 908 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 909 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 910 return false; // Let the reg+imm pattern catch this! 911 R1 = Select(Addr.getOperand(0)); 912 R2 = Select(Addr.getOperand(1)); 913 return true; 914 } 915 916 R1 = Select(Addr); 917 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 918 return true; 919} 920 921SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 922 SDNode *N = Op.Val; 923 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 924 N->getOpcode() < V8ISD::FIRST_NUMBER) 925 return Op; // Already selected. 926 // If this has already been converted, use it. 927 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 928 if (CGMI != CodeGenMap.end()) return CGMI->second; 929 930 switch (N->getOpcode()) { 931 default: break; 932 case ISD::FrameIndex: { 933 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 934 if (N->hasOneUse()) 935 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 936 CurDAG->getTargetFrameIndex(FI, MVT::i32), 937 CurDAG->getTargetConstant(0, MVT::i32)); 938 return CodeGenMap[Op] = 939 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 940 CurDAG->getTargetFrameIndex(FI, MVT::i32), 941 CurDAG->getTargetConstant(0, MVT::i32)); 942 } 943 case ISD::ADD_PARTS: { 944 SDOperand LHSL = Select(N->getOperand(0)); 945 SDOperand LHSH = Select(N->getOperand(1)); 946 SDOperand RHSL = Select(N->getOperand(2)); 947 SDOperand RHSH = Select(N->getOperand(3)); 948 // FIXME, handle immediate RHS. 949 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 950 LHSL, RHSL); 951 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 952 Low.getValue(1)); 953 CodeGenMap[SDOperand(N, 0)] = Low; 954 CodeGenMap[SDOperand(N, 1)] = Hi; 955 return Op.ResNo ? Hi : Low; 956 } 957 case ISD::SUB_PARTS: { 958 SDOperand LHSL = Select(N->getOperand(0)); 959 SDOperand LHSH = Select(N->getOperand(1)); 960 SDOperand RHSL = Select(N->getOperand(2)); 961 SDOperand RHSH = Select(N->getOperand(3)); 962 // FIXME, handle immediate RHS. 963 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 964 LHSL, RHSL); 965 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 966 Low.getValue(1)); 967 CodeGenMap[SDOperand(N, 0)] = Low; 968 CodeGenMap[SDOperand(N, 1)] = Hi; 969 return Op.ResNo ? Hi : Low; 970 } 971 case ISD::SDIV: 972 case ISD::UDIV: { 973 // FIXME: should use a custom expander to expose the SRA to the dag. 974 SDOperand DivLHS = Select(N->getOperand(0)); 975 SDOperand DivRHS = Select(N->getOperand(1)); 976 977 // Set the Y register to the high-part. 978 SDOperand TopPart; 979 if (N->getOpcode() == ISD::SDIV) { 980 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 981 CurDAG->getTargetConstant(31, MVT::i32)); 982 } else { 983 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 984 } 985 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 986 CurDAG->getRegister(V8::G0, MVT::i32)); 987 988 // FIXME: Handle div by immediate. 989 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 990 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 991 } 992 case ISD::MULHU: 993 case ISD::MULHS: { 994 // FIXME: Handle mul by immediate. 995 SDOperand MulLHS = Select(N->getOperand(0)); 996 SDOperand MulRHS = Select(N->getOperand(1)); 997 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 998 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 999 MulLHS, MulRHS); 1000 // The high part is in the Y register. 1001 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 1002 } 1003 case ISD::CALL: 1004 // FIXME: This is a workaround for a bug in tblgen. 1005 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 1006 // Emits: (CALL:void (tglobaladdr:i32):$dst) 1007 // Pattern complexity = 2 cost = 1 1008 SDOperand N1 = N->getOperand(1); 1009 if (N1.getOpcode() != ISD::TargetGlobalAddress && 1010 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 1011 SDOperand InFlag = SDOperand(0, 0); 1012 SDOperand Chain = N->getOperand(0); 1013 SDOperand Tmp0 = N1; 1014 Chain = Select(Chain); 1015 SDOperand Result; 1016 if (N->getNumOperands() == 3) { 1017 InFlag = Select(N->getOperand(2)); 1018 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 1019 Chain, InFlag); 1020 } else { 1021 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 1022 Chain); 1023 } 1024 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 1025 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 1026 return Result.getValue(Op.ResNo); 1027 } 1028 P47Fail:; 1029 1030 } 1031 1032 return SelectCode(Op); 1033} 1034 1035 1036/// createPPCISelDag - This pass converts a legalized DAG into a 1037/// PowerPC-specific DAG, ready for instruction scheduling. 1038/// 1039FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 1040 return new SparcV8DAGToDAGISel(TM); 1041} 1042