X86DisassemblerDecoder.c revision 06f554d06ab0f9390d04bcbaabb76f572d940249
1/*===- X86DisassemblerDecoder.c - Disassembler decoder -------------*- C -*-==* 2 * 3 * The LLVM Compiler Infrastructure 4 * 5 * This file is distributed under the University of Illinois Open Source 6 * License. See LICENSE.TXT for details. 7 * 8 *===----------------------------------------------------------------------===* 9 * 10 * This file is part of the X86 Disassembler. 11 * It contains the implementation of the instruction decoder. 12 * Documentation for the disassembler can be found in X86Disassembler.h. 13 * 14 *===----------------------------------------------------------------------===*/ 15 16#include <stdarg.h> /* for va_*() */ 17#include <stdio.h> /* for vsnprintf() */ 18#include <stdlib.h> /* for exit() */ 19#include <string.h> /* for memset() */ 20 21#include "X86DisassemblerDecoder.h" 22 23#include "X86GenDisassemblerTables.inc" 24 25#define TRUE 1 26#define FALSE 0 27 28typedef int8_t bool; 29 30#ifndef NDEBUG 31#define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0) 32#else 33#define debug(s) do { } while (0) 34#endif 35 36 37/* 38 * contextForAttrs - Client for the instruction context table. Takes a set of 39 * attributes and returns the appropriate decode context. 40 * 41 * @param attrMask - Attributes, from the enumeration attributeBits. 42 * @return - The InstructionContext to use when looking up an 43 * an instruction with these attributes. 44 */ 45static InstructionContext contextForAttrs(uint8_t attrMask) { 46 return CONTEXTS_SYM[attrMask]; 47} 48 49/* 50 * modRMRequired - Reads the appropriate instruction table to determine whether 51 * the ModR/M byte is required to decode a particular instruction. 52 * 53 * @param type - The opcode type (i.e., how many bytes it has). 54 * @param insnContext - The context for the instruction, as returned by 55 * contextForAttrs. 56 * @param opcode - The last byte of the instruction's opcode, not counting 57 * ModR/M extensions and escapes. 58 * @return - TRUE if the ModR/M byte is required, FALSE otherwise. 59 */ 60static int modRMRequired(OpcodeType type, 61 InstructionContext insnContext, 62 uint8_t opcode) { 63 const struct ContextDecision* decision = 0; 64 65 switch (type) { 66 case ONEBYTE: 67 decision = &ONEBYTE_SYM; 68 break; 69 case TWOBYTE: 70 decision = &TWOBYTE_SYM; 71 break; 72 case THREEBYTE_38: 73 decision = &THREEBYTE38_SYM; 74 break; 75 case THREEBYTE_3A: 76 decision = &THREEBYTE3A_SYM; 77 break; 78 case THREEBYTE_A6: 79 decision = &THREEBYTEA6_SYM; 80 break; 81 case THREEBYTE_A7: 82 decision = &THREEBYTEA7_SYM; 83 break; 84 } 85 86 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode]. 87 modrm_type != MODRM_ONEENTRY; 88 89 return 0; 90} 91 92/* 93 * decode - Reads the appropriate instruction table to obtain the unique ID of 94 * an instruction. 95 * 96 * @param type - See modRMRequired(). 97 * @param insnContext - See modRMRequired(). 98 * @param opcode - See modRMRequired(). 99 * @param modRM - The ModR/M byte if required, or any value if not. 100 * @return - The UID of the instruction, or 0 on failure. 101 */ 102static InstrUID decode(OpcodeType type, 103 InstructionContext insnContext, 104 uint8_t opcode, 105 uint8_t modRM) { 106 const struct ModRMDecision* dec; 107 108 switch (type) { 109 default: 110 debug("Unknown opcode type"); 111 return 0; 112 case ONEBYTE: 113 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 114 break; 115 case TWOBYTE: 116 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 117 break; 118 case THREEBYTE_38: 119 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 120 break; 121 case THREEBYTE_3A: 122 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 123 break; 124 case THREEBYTE_A6: 125 dec = &THREEBYTEA6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 126 break; 127 case THREEBYTE_A7: 128 dec = &THREEBYTEA7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 129 break; 130 } 131 132 switch (dec->modrm_type) { 133 default: 134 debug("Corrupt table! Unknown modrm_type"); 135 return 0; 136 case MODRM_ONEENTRY: 137 return dec->instructionIDs[0]; 138 case MODRM_SPLITRM: 139 if (modFromModRM(modRM) == 0x3) 140 return dec->instructionIDs[1]; 141 else 142 return dec->instructionIDs[0]; 143 case MODRM_FULL: 144 return dec->instructionIDs[modRM]; 145 } 146} 147 148/* 149 * specifierForUID - Given a UID, returns the name and operand specification for 150 * that instruction. 151 * 152 * @param uid - The unique ID for the instruction. This should be returned by 153 * decode(); specifierForUID will not check bounds. 154 * @return - A pointer to the specification for that instruction. 155 */ 156static const struct InstructionSpecifier *specifierForUID(InstrUID uid) { 157 return &INSTRUCTIONS_SYM[uid]; 158} 159 160/* 161 * consumeByte - Uses the reader function provided by the user to consume one 162 * byte from the instruction's memory and advance the cursor. 163 * 164 * @param insn - The instruction with the reader function to use. The cursor 165 * for this instruction is advanced. 166 * @param byte - A pointer to a pre-allocated memory buffer to be populated 167 * with the data read. 168 * @return - 0 if the read was successful; nonzero otherwise. 169 */ 170static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) { 171 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor); 172 173 if (!ret) 174 ++(insn->readerCursor); 175 176 return ret; 177} 178 179/* 180 * lookAtByte - Like consumeByte, but does not advance the cursor. 181 * 182 * @param insn - See consumeByte(). 183 * @param byte - See consumeByte(). 184 * @return - See consumeByte(). 185 */ 186static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) { 187 return insn->reader(insn->readerArg, byte, insn->readerCursor); 188} 189 190static void unconsumeByte(struct InternalInstruction* insn) { 191 insn->readerCursor--; 192} 193 194#define CONSUME_FUNC(name, type) \ 195 static int name(struct InternalInstruction* insn, type* ptr) { \ 196 type combined = 0; \ 197 unsigned offset; \ 198 for (offset = 0; offset < sizeof(type); ++offset) { \ 199 uint8_t byte; \ 200 int ret = insn->reader(insn->readerArg, \ 201 &byte, \ 202 insn->readerCursor + offset); \ 203 if (ret) \ 204 return ret; \ 205 combined = combined | ((type)byte << ((type)offset * 8)); \ 206 } \ 207 *ptr = combined; \ 208 insn->readerCursor += sizeof(type); \ 209 return 0; \ 210 } 211 212/* 213 * consume* - Use the reader function provided by the user to consume data 214 * values of various sizes from the instruction's memory and advance the 215 * cursor appropriately. These readers perform endian conversion. 216 * 217 * @param insn - See consumeByte(). 218 * @param ptr - A pointer to a pre-allocated memory of appropriate size to 219 * be populated with the data read. 220 * @return - See consumeByte(). 221 */ 222CONSUME_FUNC(consumeInt8, int8_t) 223CONSUME_FUNC(consumeInt16, int16_t) 224CONSUME_FUNC(consumeInt32, int32_t) 225CONSUME_FUNC(consumeUInt16, uint16_t) 226CONSUME_FUNC(consumeUInt32, uint32_t) 227CONSUME_FUNC(consumeUInt64, uint64_t) 228 229/* 230 * dbgprintf - Uses the logging function provided by the user to log a single 231 * message, typically without a carriage-return. 232 * 233 * @param insn - The instruction containing the logging function. 234 * @param format - See printf(). 235 * @param ... - See printf(). 236 */ 237static void dbgprintf(struct InternalInstruction* insn, 238 const char* format, 239 ...) { 240 char buffer[256]; 241 va_list ap; 242 243 if (!insn->dlog) 244 return; 245 246 va_start(ap, format); 247 (void)vsnprintf(buffer, sizeof(buffer), format, ap); 248 va_end(ap); 249 250 insn->dlog(insn->dlogArg, buffer); 251 252 return; 253} 254 255/* 256 * setPrefixPresent - Marks that a particular prefix is present at a particular 257 * location. 258 * 259 * @param insn - The instruction to be marked as having the prefix. 260 * @param prefix - The prefix that is present. 261 * @param location - The location where the prefix is located (in the address 262 * space of the instruction's reader). 263 */ 264static void setPrefixPresent(struct InternalInstruction* insn, 265 uint8_t prefix, 266 uint64_t location) 267{ 268 insn->prefixPresent[prefix] = 1; 269 insn->prefixLocations[prefix] = location; 270} 271 272/* 273 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is 274 * present at a given location. 275 * 276 * @param insn - The instruction to be queried. 277 * @param prefix - The prefix. 278 * @param location - The location to query. 279 * @return - Whether the prefix is at that location. 280 */ 281static BOOL isPrefixAtLocation(struct InternalInstruction* insn, 282 uint8_t prefix, 283 uint64_t location) 284{ 285 if (insn->prefixPresent[prefix] == 1 && 286 insn->prefixLocations[prefix] == location) 287 return TRUE; 288 else 289 return FALSE; 290} 291 292/* 293 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the 294 * instruction as having them. Also sets the instruction's default operand, 295 * address, and other relevant data sizes to report operands correctly. 296 * 297 * @param insn - The instruction whose prefixes are to be read. 298 * @return - 0 if the instruction could be read until the end of the prefix 299 * bytes, and no prefixes conflicted; nonzero otherwise. 300 */ 301static int readPrefixes(struct InternalInstruction* insn) { 302 BOOL isPrefix = TRUE; 303 BOOL prefixGroups[4] = { FALSE }; 304 uint64_t prefixLocation; 305 uint8_t byte = 0; 306 307 BOOL hasAdSize = FALSE; 308 BOOL hasOpSize = FALSE; 309 310 dbgprintf(insn, "readPrefixes()"); 311 312 while (isPrefix) { 313 prefixLocation = insn->readerCursor; 314 315 if (consumeByte(insn, &byte)) 316 return -1; 317 318 switch (byte) { 319 case 0xf0: /* LOCK */ 320 case 0xf2: /* REPNE/REPNZ */ 321 case 0xf3: /* REP or REPE/REPZ */ 322 if (prefixGroups[0]) 323 dbgprintf(insn, "Redundant Group 1 prefix"); 324 prefixGroups[0] = TRUE; 325 setPrefixPresent(insn, byte, prefixLocation); 326 break; 327 case 0x2e: /* CS segment override -OR- Branch not taken */ 328 case 0x36: /* SS segment override -OR- Branch taken */ 329 case 0x3e: /* DS segment override */ 330 case 0x26: /* ES segment override */ 331 case 0x64: /* FS segment override */ 332 case 0x65: /* GS segment override */ 333 switch (byte) { 334 case 0x2e: 335 insn->segmentOverride = SEG_OVERRIDE_CS; 336 break; 337 case 0x36: 338 insn->segmentOverride = SEG_OVERRIDE_SS; 339 break; 340 case 0x3e: 341 insn->segmentOverride = SEG_OVERRIDE_DS; 342 break; 343 case 0x26: 344 insn->segmentOverride = SEG_OVERRIDE_ES; 345 break; 346 case 0x64: 347 insn->segmentOverride = SEG_OVERRIDE_FS; 348 break; 349 case 0x65: 350 insn->segmentOverride = SEG_OVERRIDE_GS; 351 break; 352 default: 353 debug("Unhandled override"); 354 return -1; 355 } 356 if (prefixGroups[1]) 357 dbgprintf(insn, "Redundant Group 2 prefix"); 358 prefixGroups[1] = TRUE; 359 setPrefixPresent(insn, byte, prefixLocation); 360 break; 361 case 0x66: /* Operand-size override */ 362 if (prefixGroups[2]) 363 dbgprintf(insn, "Redundant Group 3 prefix"); 364 prefixGroups[2] = TRUE; 365 hasOpSize = TRUE; 366 setPrefixPresent(insn, byte, prefixLocation); 367 break; 368 case 0x67: /* Address-size override */ 369 if (prefixGroups[3]) 370 dbgprintf(insn, "Redundant Group 4 prefix"); 371 prefixGroups[3] = TRUE; 372 hasAdSize = TRUE; 373 setPrefixPresent(insn, byte, prefixLocation); 374 break; 375 default: /* Not a prefix byte */ 376 isPrefix = FALSE; 377 break; 378 } 379 380 if (isPrefix) 381 dbgprintf(insn, "Found prefix 0x%hhx", byte); 382 } 383 384 insn->vexSize = 0; 385 386 if (byte == 0xc4) { 387 uint8_t byte1; 388 389 if (lookAtByte(insn, &byte1)) { 390 dbgprintf(insn, "Couldn't read second byte of VEX"); 391 return -1; 392 } 393 394 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) { 395 insn->vexSize = 3; 396 insn->necessaryPrefixLocation = insn->readerCursor - 1; 397 } 398 else { 399 unconsumeByte(insn); 400 insn->necessaryPrefixLocation = insn->readerCursor - 1; 401 } 402 403 if (insn->vexSize == 3) { 404 insn->vexPrefix[0] = byte; 405 consumeByte(insn, &insn->vexPrefix[1]); 406 consumeByte(insn, &insn->vexPrefix[2]); 407 408 /* We simulate the REX prefix for simplicity's sake */ 409 410 if (insn->mode == MODE_64BIT) { 411 insn->rexPrefix = 0x40 412 | (wFromVEX3of3(insn->vexPrefix[2]) << 3) 413 | (rFromVEX2of3(insn->vexPrefix[1]) << 2) 414 | (xFromVEX2of3(insn->vexPrefix[1]) << 1) 415 | (bFromVEX2of3(insn->vexPrefix[1]) << 0); 416 } 417 418 switch (ppFromVEX3of3(insn->vexPrefix[2])) 419 { 420 default: 421 break; 422 case VEX_PREFIX_66: 423 hasOpSize = TRUE; 424 break; 425 } 426 427 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1], insn->vexPrefix[2]); 428 } 429 } 430 else if (byte == 0xc5) { 431 uint8_t byte1; 432 433 if (lookAtByte(insn, &byte1)) { 434 dbgprintf(insn, "Couldn't read second byte of VEX"); 435 return -1; 436 } 437 438 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) { 439 insn->vexSize = 2; 440 } 441 else { 442 unconsumeByte(insn); 443 } 444 445 if (insn->vexSize == 2) { 446 insn->vexPrefix[0] = byte; 447 consumeByte(insn, &insn->vexPrefix[1]); 448 449 if (insn->mode == MODE_64BIT) { 450 insn->rexPrefix = 0x40 451 | (rFromVEX2of2(insn->vexPrefix[1]) << 2); 452 } 453 454 switch (ppFromVEX2of2(insn->vexPrefix[1])) 455 { 456 default: 457 break; 458 case VEX_PREFIX_66: 459 hasOpSize = TRUE; 460 break; 461 } 462 463 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1]); 464 } 465 } 466 else { 467 if (insn->mode == MODE_64BIT) { 468 if ((byte & 0xf0) == 0x40) { 469 uint8_t opcodeByte; 470 471 if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) { 472 dbgprintf(insn, "Redundant REX prefix"); 473 return -1; 474 } 475 476 insn->rexPrefix = byte; 477 insn->necessaryPrefixLocation = insn->readerCursor - 2; 478 479 dbgprintf(insn, "Found REX prefix 0x%hhx", byte); 480 } else { 481 unconsumeByte(insn); 482 insn->necessaryPrefixLocation = insn->readerCursor - 1; 483 } 484 } else { 485 unconsumeByte(insn); 486 insn->necessaryPrefixLocation = insn->readerCursor - 1; 487 } 488 } 489 490 if (insn->mode == MODE_16BIT) { 491 insn->registerSize = (hasOpSize ? 4 : 2); 492 insn->addressSize = (hasAdSize ? 4 : 2); 493 insn->displacementSize = (hasAdSize ? 4 : 2); 494 insn->immediateSize = (hasOpSize ? 4 : 2); 495 } else if (insn->mode == MODE_32BIT) { 496 insn->registerSize = (hasOpSize ? 2 : 4); 497 insn->addressSize = (hasAdSize ? 2 : 4); 498 insn->displacementSize = (hasAdSize ? 2 : 4); 499 insn->immediateSize = (hasOpSize ? 2 : 4); 500 } else if (insn->mode == MODE_64BIT) { 501 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) { 502 insn->registerSize = 8; 503 insn->addressSize = (hasAdSize ? 4 : 8); 504 insn->displacementSize = 4; 505 insn->immediateSize = 4; 506 } else if (insn->rexPrefix) { 507 insn->registerSize = (hasOpSize ? 2 : 4); 508 insn->addressSize = (hasAdSize ? 4 : 8); 509 insn->displacementSize = (hasOpSize ? 2 : 4); 510 insn->immediateSize = (hasOpSize ? 2 : 4); 511 } else { 512 insn->registerSize = (hasOpSize ? 2 : 4); 513 insn->addressSize = (hasAdSize ? 4 : 8); 514 insn->displacementSize = (hasOpSize ? 2 : 4); 515 insn->immediateSize = (hasOpSize ? 2 : 4); 516 } 517 } 518 519 return 0; 520} 521 522/* 523 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of 524 * extended or escape opcodes). 525 * 526 * @param insn - The instruction whose opcode is to be read. 527 * @return - 0 if the opcode could be read successfully; nonzero otherwise. 528 */ 529static int readOpcode(struct InternalInstruction* insn) { 530 /* Determine the length of the primary opcode */ 531 532 uint8_t current; 533 534 dbgprintf(insn, "readOpcode()"); 535 536 insn->opcodeType = ONEBYTE; 537 538 if (insn->vexSize == 3) 539 { 540 switch (mmmmmFromVEX2of3(insn->vexPrefix[1])) 541 { 542 default: 543 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", mmmmmFromVEX2of3(insn->vexPrefix[1])); 544 return -1; 545 case 0: 546 break; 547 case VEX_LOB_0F: 548 insn->twoByteEscape = 0x0f; 549 insn->opcodeType = TWOBYTE; 550 return consumeByte(insn, &insn->opcode); 551 case VEX_LOB_0F38: 552 insn->twoByteEscape = 0x0f; 553 insn->threeByteEscape = 0x38; 554 insn->opcodeType = THREEBYTE_38; 555 return consumeByte(insn, &insn->opcode); 556 case VEX_LOB_0F3A: 557 insn->twoByteEscape = 0x0f; 558 insn->threeByteEscape = 0x3a; 559 insn->opcodeType = THREEBYTE_3A; 560 return consumeByte(insn, &insn->opcode); 561 } 562 } 563 else if (insn->vexSize == 2) 564 { 565 insn->twoByteEscape = 0x0f; 566 insn->opcodeType = TWOBYTE; 567 return consumeByte(insn, &insn->opcode); 568 } 569 570 if (consumeByte(insn, ¤t)) 571 return -1; 572 573 if (current == 0x0f) { 574 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current); 575 576 insn->twoByteEscape = current; 577 578 if (consumeByte(insn, ¤t)) 579 return -1; 580 581 if (current == 0x38) { 582 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); 583 584 insn->threeByteEscape = current; 585 586 if (consumeByte(insn, ¤t)) 587 return -1; 588 589 insn->opcodeType = THREEBYTE_38; 590 } else if (current == 0x3a) { 591 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); 592 593 insn->threeByteEscape = current; 594 595 if (consumeByte(insn, ¤t)) 596 return -1; 597 598 insn->opcodeType = THREEBYTE_3A; 599 } else if (current == 0xa6) { 600 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); 601 602 insn->threeByteEscape = current; 603 604 if (consumeByte(insn, ¤t)) 605 return -1; 606 607 insn->opcodeType = THREEBYTE_A6; 608 } else if (current == 0xa7) { 609 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); 610 611 insn->threeByteEscape = current; 612 613 if (consumeByte(insn, ¤t)) 614 return -1; 615 616 insn->opcodeType = THREEBYTE_A7; 617 } else { 618 dbgprintf(insn, "Didn't find a three-byte escape prefix"); 619 620 insn->opcodeType = TWOBYTE; 621 } 622 } 623 624 /* 625 * At this point we have consumed the full opcode. 626 * Anything we consume from here on must be unconsumed. 627 */ 628 629 insn->opcode = current; 630 631 return 0; 632} 633 634static int readModRM(struct InternalInstruction* insn); 635 636/* 637 * getIDWithAttrMask - Determines the ID of an instruction, consuming 638 * the ModR/M byte as appropriate for extended and escape opcodes, 639 * and using a supplied attribute mask. 640 * 641 * @param instructionID - A pointer whose target is filled in with the ID of the 642 * instruction. 643 * @param insn - The instruction whose ID is to be determined. 644 * @param attrMask - The attribute mask to search. 645 * @return - 0 if the ModR/M could be read when needed or was not 646 * needed; nonzero otherwise. 647 */ 648static int getIDWithAttrMask(uint16_t* instructionID, 649 struct InternalInstruction* insn, 650 uint8_t attrMask) { 651 BOOL hasModRMExtension; 652 653 uint8_t instructionClass; 654 655 instructionClass = contextForAttrs(attrMask); 656 657 hasModRMExtension = modRMRequired(insn->opcodeType, 658 instructionClass, 659 insn->opcode); 660 661 if (hasModRMExtension) { 662 if (readModRM(insn)) 663 return -1; 664 665 *instructionID = decode(insn->opcodeType, 666 instructionClass, 667 insn->opcode, 668 insn->modRM); 669 } else { 670 *instructionID = decode(insn->opcodeType, 671 instructionClass, 672 insn->opcode, 673 0); 674 } 675 676 return 0; 677} 678 679/* 680 * is16BitEquivalent - Determines whether two instruction names refer to 681 * equivalent instructions but one is 16-bit whereas the other is not. 682 * 683 * @param orig - The instruction that is not 16-bit 684 * @param equiv - The instruction that is 16-bit 685 */ 686static BOOL is16BitEquvalent(const char* orig, const char* equiv) { 687 off_t i; 688 689 for (i = 0;; i++) { 690 if (orig[i] == '\0' && equiv[i] == '\0') 691 return TRUE; 692 if (orig[i] == '\0' || equiv[i] == '\0') 693 return FALSE; 694 if (orig[i] != equiv[i]) { 695 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W') 696 continue; 697 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1') 698 continue; 699 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6') 700 continue; 701 return FALSE; 702 } 703 } 704} 705 706/* 707 * getID - Determines the ID of an instruction, consuming the ModR/M byte as 708 * appropriate for extended and escape opcodes. Determines the attributes and 709 * context for the instruction before doing so. 710 * 711 * @param insn - The instruction whose ID is to be determined. 712 * @return - 0 if the ModR/M could be read when needed or was not needed; 713 * nonzero otherwise. 714 */ 715static int getID(struct InternalInstruction* insn) { 716 uint8_t attrMask; 717 uint16_t instructionID; 718 719 dbgprintf(insn, "getID()"); 720 721 attrMask = ATTR_NONE; 722 723 if (insn->mode == MODE_64BIT) 724 attrMask |= ATTR_64BIT; 725 726 if (insn->vexSize) { 727 attrMask |= ATTR_VEX; 728 729 if (insn->vexSize == 3) { 730 switch (ppFromVEX3of3(insn->vexPrefix[2])) { 731 case VEX_PREFIX_66: 732 attrMask |= ATTR_OPSIZE; 733 break; 734 case VEX_PREFIX_F3: 735 attrMask |= ATTR_XS; 736 break; 737 case VEX_PREFIX_F2: 738 attrMask |= ATTR_XD; 739 break; 740 } 741 742 if (lFromVEX3of3(insn->vexPrefix[2])) 743 attrMask |= ATTR_VEXL; 744 } 745 else if (insn->vexSize == 2) { 746 switch (ppFromVEX2of2(insn->vexPrefix[1])) { 747 case VEX_PREFIX_66: 748 attrMask |= ATTR_OPSIZE; 749 break; 750 case VEX_PREFIX_F3: 751 attrMask |= ATTR_XS; 752 break; 753 case VEX_PREFIX_F2: 754 attrMask |= ATTR_XD; 755 break; 756 } 757 758 if (lFromVEX2of2(insn->vexPrefix[1])) 759 attrMask |= ATTR_VEXL; 760 } 761 else { 762 return -1; 763 } 764 } 765 else { 766 if (isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation)) 767 attrMask |= ATTR_OPSIZE; 768 else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation)) 769 attrMask |= ATTR_XS; 770 else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation)) 771 attrMask |= ATTR_XD; 772 } 773 774 if (insn->rexPrefix & 0x08) 775 attrMask |= ATTR_REXW; 776 777 if (getIDWithAttrMask(&instructionID, insn, attrMask)) 778 return -1; 779 780 /* The following clauses compensate for limitations of the tables. */ 781 782 if ((attrMask & ATTR_VEXL) && (attrMask & ATTR_REXW) && 783 !(attrMask & ATTR_OPSIZE)) { 784 /* 785 * Some VEX instructions ignore the L-bit, but use the W-bit. Normally L-bit 786 * has precedence since there are no L-bit with W-bit entries in the tables. 787 * So if the L-bit isn't significant we should use the W-bit instead. 788 * We only need to do this if the instruction doesn't specify OpSize since 789 * there is a VEX_L_W_OPSIZE table. 790 */ 791 792 const struct InstructionSpecifier *spec; 793 uint16_t instructionIDWithWBit; 794 const struct InstructionSpecifier *specWithWBit; 795 796 spec = specifierForUID(instructionID); 797 798 if (getIDWithAttrMask(&instructionIDWithWBit, 799 insn, 800 (attrMask & (~ATTR_VEXL)) | ATTR_REXW)) { 801 insn->instructionID = instructionID; 802 insn->spec = spec; 803 return 0; 804 } 805 806 specWithWBit = specifierForUID(instructionIDWithWBit); 807 808 if (instructionID != instructionIDWithWBit) { 809 insn->instructionID = instructionIDWithWBit; 810 insn->spec = specWithWBit; 811 } else { 812 insn->instructionID = instructionID; 813 insn->spec = spec; 814 } 815 return 0; 816 } 817 818 if (insn->prefixPresent[0x66] && !(attrMask & ATTR_OPSIZE)) { 819 /* 820 * The instruction tables make no distinction between instructions that 821 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a 822 * particular spot (i.e., many MMX operations). In general we're 823 * conservative, but in the specific case where OpSize is present but not 824 * in the right place we check if there's a 16-bit operation. 825 */ 826 827 const struct InstructionSpecifier *spec; 828 uint16_t instructionIDWithOpsize; 829 const struct InstructionSpecifier *specWithOpsize; 830 831 spec = specifierForUID(instructionID); 832 833 if (getIDWithAttrMask(&instructionIDWithOpsize, 834 insn, 835 attrMask | ATTR_OPSIZE)) { 836 /* 837 * ModRM required with OpSize but not present; give up and return version 838 * without OpSize set 839 */ 840 841 insn->instructionID = instructionID; 842 insn->spec = spec; 843 return 0; 844 } 845 846 specWithOpsize = specifierForUID(instructionIDWithOpsize); 847 848 if (is16BitEquvalent(spec->name, specWithOpsize->name)) { 849 insn->instructionID = instructionIDWithOpsize; 850 insn->spec = specWithOpsize; 851 } else { 852 insn->instructionID = instructionID; 853 insn->spec = spec; 854 } 855 return 0; 856 } 857 858 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 && 859 insn->rexPrefix & 0x01) { 860 /* 861 * NOOP shouldn't decode as NOOP if REX.b is set. Instead 862 * it should decode as XCHG %r8, %eax. 863 */ 864 865 const struct InstructionSpecifier *spec; 866 uint16_t instructionIDWithNewOpcode; 867 const struct InstructionSpecifier *specWithNewOpcode; 868 869 spec = specifierForUID(instructionID); 870 871 /* Borrow opcode from one of the other XCHGar opcodes */ 872 insn->opcode = 0x91; 873 874 if (getIDWithAttrMask(&instructionIDWithNewOpcode, 875 insn, 876 attrMask)) { 877 insn->opcode = 0x90; 878 879 insn->instructionID = instructionID; 880 insn->spec = spec; 881 return 0; 882 } 883 884 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode); 885 886 /* Change back */ 887 insn->opcode = 0x90; 888 889 insn->instructionID = instructionIDWithNewOpcode; 890 insn->spec = specWithNewOpcode; 891 892 return 0; 893 } 894 895 insn->instructionID = instructionID; 896 insn->spec = specifierForUID(insn->instructionID); 897 898 return 0; 899} 900 901/* 902 * readSIB - Consumes the SIB byte to determine addressing information for an 903 * instruction. 904 * 905 * @param insn - The instruction whose SIB byte is to be read. 906 * @return - 0 if the SIB byte was successfully read; nonzero otherwise. 907 */ 908static int readSIB(struct InternalInstruction* insn) { 909 SIBIndex sibIndexBase = 0; 910 SIBBase sibBaseBase = 0; 911 uint8_t index, base; 912 913 dbgprintf(insn, "readSIB()"); 914 915 if (insn->consumedSIB) 916 return 0; 917 918 insn->consumedSIB = TRUE; 919 920 switch (insn->addressSize) { 921 case 2: 922 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode"); 923 return -1; 924 break; 925 case 4: 926 sibIndexBase = SIB_INDEX_EAX; 927 sibBaseBase = SIB_BASE_EAX; 928 break; 929 case 8: 930 sibIndexBase = SIB_INDEX_RAX; 931 sibBaseBase = SIB_BASE_RAX; 932 break; 933 } 934 935 if (consumeByte(insn, &insn->sib)) 936 return -1; 937 938 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3); 939 940 switch (index) { 941 case 0x4: 942 insn->sibIndex = SIB_INDEX_NONE; 943 break; 944 default: 945 insn->sibIndex = (SIBIndex)(sibIndexBase + index); 946 if (insn->sibIndex == SIB_INDEX_sib || 947 insn->sibIndex == SIB_INDEX_sib64) 948 insn->sibIndex = SIB_INDEX_NONE; 949 break; 950 } 951 952 switch (scaleFromSIB(insn->sib)) { 953 case 0: 954 insn->sibScale = 1; 955 break; 956 case 1: 957 insn->sibScale = 2; 958 break; 959 case 2: 960 insn->sibScale = 4; 961 break; 962 case 3: 963 insn->sibScale = 8; 964 break; 965 } 966 967 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3); 968 969 switch (base) { 970 case 0x5: 971 switch (modFromModRM(insn->modRM)) { 972 case 0x0: 973 insn->eaDisplacement = EA_DISP_32; 974 insn->sibBase = SIB_BASE_NONE; 975 break; 976 case 0x1: 977 insn->eaDisplacement = EA_DISP_8; 978 insn->sibBase = (insn->addressSize == 4 ? 979 SIB_BASE_EBP : SIB_BASE_RBP); 980 break; 981 case 0x2: 982 insn->eaDisplacement = EA_DISP_32; 983 insn->sibBase = (insn->addressSize == 4 ? 984 SIB_BASE_EBP : SIB_BASE_RBP); 985 break; 986 case 0x3: 987 debug("Cannot have Mod = 0b11 and a SIB byte"); 988 return -1; 989 } 990 break; 991 default: 992 insn->sibBase = (SIBBase)(sibBaseBase + base); 993 break; 994 } 995 996 return 0; 997} 998 999/* 1000 * readDisplacement - Consumes the displacement of an instruction. 1001 * 1002 * @param insn - The instruction whose displacement is to be read. 1003 * @return - 0 if the displacement byte was successfully read; nonzero 1004 * otherwise. 1005 */ 1006static int readDisplacement(struct InternalInstruction* insn) { 1007 int8_t d8; 1008 int16_t d16; 1009 int32_t d32; 1010 1011 dbgprintf(insn, "readDisplacement()"); 1012 1013 if (insn->consumedDisplacement) 1014 return 0; 1015 1016 insn->consumedDisplacement = TRUE; 1017 1018 switch (insn->eaDisplacement) { 1019 case EA_DISP_NONE: 1020 insn->consumedDisplacement = FALSE; 1021 break; 1022 case EA_DISP_8: 1023 if (consumeInt8(insn, &d8)) 1024 return -1; 1025 insn->displacement = d8; 1026 break; 1027 case EA_DISP_16: 1028 if (consumeInt16(insn, &d16)) 1029 return -1; 1030 insn->displacement = d16; 1031 break; 1032 case EA_DISP_32: 1033 if (consumeInt32(insn, &d32)) 1034 return -1; 1035 insn->displacement = d32; 1036 break; 1037 } 1038 1039 insn->consumedDisplacement = TRUE; 1040 return 0; 1041} 1042 1043/* 1044 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and 1045 * displacement) for an instruction and interprets it. 1046 * 1047 * @param insn - The instruction whose addressing information is to be read. 1048 * @return - 0 if the information was successfully read; nonzero otherwise. 1049 */ 1050static int readModRM(struct InternalInstruction* insn) { 1051 uint8_t mod, rm, reg; 1052 1053 dbgprintf(insn, "readModRM()"); 1054 1055 if (insn->consumedModRM) 1056 return 0; 1057 1058 if (consumeByte(insn, &insn->modRM)) 1059 return -1; 1060 insn->consumedModRM = TRUE; 1061 1062 mod = modFromModRM(insn->modRM); 1063 rm = rmFromModRM(insn->modRM); 1064 reg = regFromModRM(insn->modRM); 1065 1066 /* 1067 * This goes by insn->registerSize to pick the correct register, which messes 1068 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in 1069 * fixupReg(). 1070 */ 1071 switch (insn->registerSize) { 1072 case 2: 1073 insn->regBase = MODRM_REG_AX; 1074 insn->eaRegBase = EA_REG_AX; 1075 break; 1076 case 4: 1077 insn->regBase = MODRM_REG_EAX; 1078 insn->eaRegBase = EA_REG_EAX; 1079 break; 1080 case 8: 1081 insn->regBase = MODRM_REG_RAX; 1082 insn->eaRegBase = EA_REG_RAX; 1083 break; 1084 } 1085 1086 reg |= rFromREX(insn->rexPrefix) << 3; 1087 rm |= bFromREX(insn->rexPrefix) << 3; 1088 1089 insn->reg = (Reg)(insn->regBase + reg); 1090 1091 switch (insn->addressSize) { 1092 case 2: 1093 insn->eaBaseBase = EA_BASE_BX_SI; 1094 1095 switch (mod) { 1096 case 0x0: 1097 if (rm == 0x6) { 1098 insn->eaBase = EA_BASE_NONE; 1099 insn->eaDisplacement = EA_DISP_16; 1100 if (readDisplacement(insn)) 1101 return -1; 1102 } else { 1103 insn->eaBase = (EABase)(insn->eaBaseBase + rm); 1104 insn->eaDisplacement = EA_DISP_NONE; 1105 } 1106 break; 1107 case 0x1: 1108 insn->eaBase = (EABase)(insn->eaBaseBase + rm); 1109 insn->eaDisplacement = EA_DISP_8; 1110 if (readDisplacement(insn)) 1111 return -1; 1112 break; 1113 case 0x2: 1114 insn->eaBase = (EABase)(insn->eaBaseBase + rm); 1115 insn->eaDisplacement = EA_DISP_16; 1116 if (readDisplacement(insn)) 1117 return -1; 1118 break; 1119 case 0x3: 1120 insn->eaBase = (EABase)(insn->eaRegBase + rm); 1121 if (readDisplacement(insn)) 1122 return -1; 1123 break; 1124 } 1125 break; 1126 case 4: 1127 case 8: 1128 insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX); 1129 1130 switch (mod) { 1131 case 0x0: 1132 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */ 1133 switch (rm) { 1134 case 0x4: 1135 case 0xc: /* in case REXW.b is set */ 1136 insn->eaBase = (insn->addressSize == 4 ? 1137 EA_BASE_sib : EA_BASE_sib64); 1138 readSIB(insn); 1139 if (readDisplacement(insn)) 1140 return -1; 1141 break; 1142 case 0x5: 1143 insn->eaBase = EA_BASE_NONE; 1144 insn->eaDisplacement = EA_DISP_32; 1145 if (readDisplacement(insn)) 1146 return -1; 1147 break; 1148 default: 1149 insn->eaBase = (EABase)(insn->eaBaseBase + rm); 1150 break; 1151 } 1152 break; 1153 case 0x1: 1154 case 0x2: 1155 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32); 1156 switch (rm) { 1157 case 0x4: 1158 case 0xc: /* in case REXW.b is set */ 1159 insn->eaBase = EA_BASE_sib; 1160 readSIB(insn); 1161 if (readDisplacement(insn)) 1162 return -1; 1163 break; 1164 default: 1165 insn->eaBase = (EABase)(insn->eaBaseBase + rm); 1166 if (readDisplacement(insn)) 1167 return -1; 1168 break; 1169 } 1170 break; 1171 case 0x3: 1172 insn->eaDisplacement = EA_DISP_NONE; 1173 insn->eaBase = (EABase)(insn->eaRegBase + rm); 1174 break; 1175 } 1176 break; 1177 } /* switch (insn->addressSize) */ 1178 1179 return 0; 1180} 1181 1182#define GENERIC_FIXUP_FUNC(name, base, prefix) \ 1183 static uint8_t name(struct InternalInstruction *insn, \ 1184 OperandType type, \ 1185 uint8_t index, \ 1186 uint8_t *valid) { \ 1187 *valid = 1; \ 1188 switch (type) { \ 1189 default: \ 1190 debug("Unhandled register type"); \ 1191 *valid = 0; \ 1192 return 0; \ 1193 case TYPE_Rv: \ 1194 return base + index; \ 1195 case TYPE_R8: \ 1196 if (insn->rexPrefix && \ 1197 index >= 4 && index <= 7) { \ 1198 return prefix##_SPL + (index - 4); \ 1199 } else { \ 1200 return prefix##_AL + index; \ 1201 } \ 1202 case TYPE_R16: \ 1203 return prefix##_AX + index; \ 1204 case TYPE_R32: \ 1205 return prefix##_EAX + index; \ 1206 case TYPE_R64: \ 1207 return prefix##_RAX + index; \ 1208 case TYPE_XMM256: \ 1209 return prefix##_YMM0 + index; \ 1210 case TYPE_XMM128: \ 1211 case TYPE_XMM64: \ 1212 case TYPE_XMM32: \ 1213 case TYPE_XMM: \ 1214 return prefix##_XMM0 + index; \ 1215 case TYPE_MM64: \ 1216 case TYPE_MM32: \ 1217 case TYPE_MM: \ 1218 if (index > 7) \ 1219 *valid = 0; \ 1220 return prefix##_MM0 + index; \ 1221 case TYPE_SEGMENTREG: \ 1222 if (index > 5) \ 1223 *valid = 0; \ 1224 return prefix##_ES + index; \ 1225 case TYPE_DEBUGREG: \ 1226 if (index > 7) \ 1227 *valid = 0; \ 1228 return prefix##_DR0 + index; \ 1229 case TYPE_CONTROLREG: \ 1230 if (index > 8) \ 1231 *valid = 0; \ 1232 return prefix##_CR0 + index; \ 1233 } \ 1234 } 1235 1236/* 1237 * fixup*Value - Consults an operand type to determine the meaning of the 1238 * reg or R/M field. If the operand is an XMM operand, for example, an 1239 * operand would be XMM0 instead of AX, which readModRM() would otherwise 1240 * misinterpret it as. 1241 * 1242 * @param insn - The instruction containing the operand. 1243 * @param type - The operand type. 1244 * @param index - The existing value of the field as reported by readModRM(). 1245 * @param valid - The address of a uint8_t. The target is set to 1 if the 1246 * field is valid for the register class; 0 if not. 1247 * @return - The proper value. 1248 */ 1249GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG) 1250GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG) 1251 1252/* 1253 * fixupReg - Consults an operand specifier to determine which of the 1254 * fixup*Value functions to use in correcting readModRM()'ss interpretation. 1255 * 1256 * @param insn - See fixup*Value(). 1257 * @param op - The operand specifier. 1258 * @return - 0 if fixup was successful; -1 if the register returned was 1259 * invalid for its class. 1260 */ 1261static int fixupReg(struct InternalInstruction *insn, 1262 const struct OperandSpecifier *op) { 1263 uint8_t valid; 1264 1265 dbgprintf(insn, "fixupReg()"); 1266 1267 switch ((OperandEncoding)op->encoding) { 1268 default: 1269 debug("Expected a REG or R/M encoding in fixupReg"); 1270 return -1; 1271 case ENCODING_VVVV: 1272 insn->vvvv = (Reg)fixupRegValue(insn, 1273 (OperandType)op->type, 1274 insn->vvvv, 1275 &valid); 1276 if (!valid) 1277 return -1; 1278 break; 1279 case ENCODING_REG: 1280 insn->reg = (Reg)fixupRegValue(insn, 1281 (OperandType)op->type, 1282 insn->reg - insn->regBase, 1283 &valid); 1284 if (!valid) 1285 return -1; 1286 break; 1287 case ENCODING_RM: 1288 if (insn->eaBase >= insn->eaRegBase) { 1289 insn->eaBase = (EABase)fixupRMValue(insn, 1290 (OperandType)op->type, 1291 insn->eaBase - insn->eaRegBase, 1292 &valid); 1293 if (!valid) 1294 return -1; 1295 } 1296 break; 1297 } 1298 1299 return 0; 1300} 1301 1302/* 1303 * readOpcodeModifier - Reads an operand from the opcode field of an 1304 * instruction. Handles AddRegFrm instructions. 1305 * 1306 * @param insn - The instruction whose opcode field is to be read. 1307 * @param inModRM - Indicates that the opcode field is to be read from the 1308 * ModR/M extension; useful for escape opcodes 1309 * @return - 0 on success; nonzero otherwise. 1310 */ 1311static int readOpcodeModifier(struct InternalInstruction* insn) { 1312 dbgprintf(insn, "readOpcodeModifier()"); 1313 1314 if (insn->consumedOpcodeModifier) 1315 return 0; 1316 1317 insn->consumedOpcodeModifier = TRUE; 1318 1319 switch (insn->spec->modifierType) { 1320 default: 1321 debug("Unknown modifier type."); 1322 return -1; 1323 case MODIFIER_NONE: 1324 debug("No modifier but an operand expects one."); 1325 return -1; 1326 case MODIFIER_OPCODE: 1327 insn->opcodeModifier = insn->opcode - insn->spec->modifierBase; 1328 return 0; 1329 case MODIFIER_MODRM: 1330 insn->opcodeModifier = insn->modRM - insn->spec->modifierBase; 1331 return 0; 1332 } 1333} 1334 1335/* 1336 * readOpcodeRegister - Reads an operand from the opcode field of an 1337 * instruction and interprets it appropriately given the operand width. 1338 * Handles AddRegFrm instructions. 1339 * 1340 * @param insn - See readOpcodeModifier(). 1341 * @param size - The width (in bytes) of the register being specified. 1342 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means 1343 * RAX. 1344 * @return - 0 on success; nonzero otherwise. 1345 */ 1346static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) { 1347 dbgprintf(insn, "readOpcodeRegister()"); 1348 1349 if (readOpcodeModifier(insn)) 1350 return -1; 1351 1352 if (size == 0) 1353 size = insn->registerSize; 1354 1355 switch (size) { 1356 case 1: 1357 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3) 1358 | insn->opcodeModifier)); 1359 if (insn->rexPrefix && 1360 insn->opcodeRegister >= MODRM_REG_AL + 0x4 && 1361 insn->opcodeRegister < MODRM_REG_AL + 0x8) { 1362 insn->opcodeRegister = (Reg)(MODRM_REG_SPL 1363 + (insn->opcodeRegister - MODRM_REG_AL - 4)); 1364 } 1365 1366 break; 1367 case 2: 1368 insn->opcodeRegister = (Reg)(MODRM_REG_AX 1369 + ((bFromREX(insn->rexPrefix) << 3) 1370 | insn->opcodeModifier)); 1371 break; 1372 case 4: 1373 insn->opcodeRegister = (Reg)(MODRM_REG_EAX 1374 + ((bFromREX(insn->rexPrefix) << 3) 1375 | insn->opcodeModifier)); 1376 break; 1377 case 8: 1378 insn->opcodeRegister = (Reg)(MODRM_REG_RAX 1379 + ((bFromREX(insn->rexPrefix) << 3) 1380 | insn->opcodeModifier)); 1381 break; 1382 } 1383 1384 return 0; 1385} 1386 1387/* 1388 * readImmediate - Consumes an immediate operand from an instruction, given the 1389 * desired operand size. 1390 * 1391 * @param insn - The instruction whose operand is to be read. 1392 * @param size - The width (in bytes) of the operand. 1393 * @return - 0 if the immediate was successfully consumed; nonzero 1394 * otherwise. 1395 */ 1396static int readImmediate(struct InternalInstruction* insn, uint8_t size) { 1397 uint8_t imm8; 1398 uint16_t imm16; 1399 uint32_t imm32; 1400 uint64_t imm64; 1401 1402 dbgprintf(insn, "readImmediate()"); 1403 1404 if (insn->numImmediatesConsumed == 2) { 1405 debug("Already consumed two immediates"); 1406 return -1; 1407 } 1408 1409 if (size == 0) 1410 size = insn->immediateSize; 1411 else 1412 insn->immediateSize = size; 1413 1414 switch (size) { 1415 case 1: 1416 if (consumeByte(insn, &imm8)) 1417 return -1; 1418 insn->immediates[insn->numImmediatesConsumed] = imm8; 1419 break; 1420 case 2: 1421 if (consumeUInt16(insn, &imm16)) 1422 return -1; 1423 insn->immediates[insn->numImmediatesConsumed] = imm16; 1424 break; 1425 case 4: 1426 if (consumeUInt32(insn, &imm32)) 1427 return -1; 1428 insn->immediates[insn->numImmediatesConsumed] = imm32; 1429 break; 1430 case 8: 1431 if (consumeUInt64(insn, &imm64)) 1432 return -1; 1433 insn->immediates[insn->numImmediatesConsumed] = imm64; 1434 break; 1435 } 1436 1437 insn->numImmediatesConsumed++; 1438 1439 return 0; 1440} 1441 1442/* 1443 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix. 1444 * 1445 * @param insn - The instruction whose operand is to be read. 1446 * @return - 0 if the vvvv was successfully consumed; nonzero 1447 * otherwise. 1448 */ 1449static int readVVVV(struct InternalInstruction* insn) { 1450 dbgprintf(insn, "readVVVV()"); 1451 1452 if (insn->vexSize == 3) 1453 insn->vvvv = vvvvFromVEX3of3(insn->vexPrefix[2]); 1454 else if (insn->vexSize == 2) 1455 insn->vvvv = vvvvFromVEX2of2(insn->vexPrefix[1]); 1456 else 1457 return -1; 1458 1459 if (insn->mode != MODE_64BIT) 1460 insn->vvvv &= 0x7; 1461 1462 return 0; 1463} 1464 1465/* 1466 * readOperands - Consults the specifier for an instruction and consumes all 1467 * operands for that instruction, interpreting them as it goes. 1468 * 1469 * @param insn - The instruction whose operands are to be read and interpreted. 1470 * @return - 0 if all operands could be read; nonzero otherwise. 1471 */ 1472static int readOperands(struct InternalInstruction* insn) { 1473 int index; 1474 int hasVVVV, needVVVV; 1475 int sawRegImm = 0; 1476 1477 dbgprintf(insn, "readOperands()"); 1478 1479 /* If non-zero vvvv specified, need to make sure one of the operands 1480 uses it. */ 1481 hasVVVV = !readVVVV(insn); 1482 needVVVV = hasVVVV && (insn->vvvv != 0); 1483 1484 for (index = 0; index < X86_MAX_OPERANDS; ++index) { 1485 switch (insn->spec->operands[index].encoding) { 1486 case ENCODING_NONE: 1487 break; 1488 case ENCODING_REG: 1489 case ENCODING_RM: 1490 if (readModRM(insn)) 1491 return -1; 1492 if (fixupReg(insn, &insn->spec->operands[index])) 1493 return -1; 1494 break; 1495 case ENCODING_CB: 1496 case ENCODING_CW: 1497 case ENCODING_CD: 1498 case ENCODING_CP: 1499 case ENCODING_CO: 1500 case ENCODING_CT: 1501 dbgprintf(insn, "We currently don't hande code-offset encodings"); 1502 return -1; 1503 case ENCODING_IB: 1504 if (sawRegImm) { 1505 // saw a register immediate so don't read again and instead split the previous immediate 1506 // FIXME: This is a hack 1507 insn->immediates[insn->numImmediatesConsumed++] = insn->immediates[insn->numImmediatesConsumed - 1] & 0xf; 1508 break; 1509 } 1510 if (readImmediate(insn, 1)) 1511 return -1; 1512 if (insn->spec->operands[index].type == TYPE_IMM3 && 1513 insn->immediates[insn->numImmediatesConsumed - 1] > 7) 1514 return -1; 1515 if (insn->spec->operands[index].type == TYPE_XMM128 || 1516 insn->spec->operands[index].type == TYPE_XMM256) 1517 sawRegImm = 1; 1518 break; 1519 case ENCODING_IW: 1520 if (readImmediate(insn, 2)) 1521 return -1; 1522 break; 1523 case ENCODING_ID: 1524 if (readImmediate(insn, 4)) 1525 return -1; 1526 break; 1527 case ENCODING_IO: 1528 if (readImmediate(insn, 8)) 1529 return -1; 1530 break; 1531 case ENCODING_Iv: 1532 if (readImmediate(insn, insn->immediateSize)) 1533 return -1; 1534 break; 1535 case ENCODING_Ia: 1536 if (readImmediate(insn, insn->addressSize)) 1537 return -1; 1538 break; 1539 case ENCODING_RB: 1540 if (readOpcodeRegister(insn, 1)) 1541 return -1; 1542 break; 1543 case ENCODING_RW: 1544 if (readOpcodeRegister(insn, 2)) 1545 return -1; 1546 break; 1547 case ENCODING_RD: 1548 if (readOpcodeRegister(insn, 4)) 1549 return -1; 1550 break; 1551 case ENCODING_RO: 1552 if (readOpcodeRegister(insn, 8)) 1553 return -1; 1554 break; 1555 case ENCODING_Rv: 1556 if (readOpcodeRegister(insn, 0)) 1557 return -1; 1558 break; 1559 case ENCODING_I: 1560 if (readOpcodeModifier(insn)) 1561 return -1; 1562 break; 1563 case ENCODING_VVVV: 1564 needVVVV = 0; /* Mark that we have found a VVVV operand. */ 1565 if (!hasVVVV) 1566 return -1; 1567 if (fixupReg(insn, &insn->spec->operands[index])) 1568 return -1; 1569 break; 1570 case ENCODING_DUP: 1571 break; 1572 default: 1573 dbgprintf(insn, "Encountered an operand with an unknown encoding."); 1574 return -1; 1575 } 1576 } 1577 1578 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */ 1579 if (needVVVV) return -1; 1580 1581 return 0; 1582} 1583 1584/* 1585 * decodeInstruction - Reads and interprets a full instruction provided by the 1586 * user. 1587 * 1588 * @param insn - A pointer to the instruction to be populated. Must be 1589 * pre-allocated. 1590 * @param reader - The function to be used to read the instruction's bytes. 1591 * @param readerArg - A generic argument to be passed to the reader to store 1592 * any internal state. 1593 * @param logger - If non-NULL, the function to be used to write log messages 1594 * and warnings. 1595 * @param loggerArg - A generic argument to be passed to the logger to store 1596 * any internal state. 1597 * @param startLoc - The address (in the reader's address space) of the first 1598 * byte in the instruction. 1599 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to 1600 * decode the instruction in. 1601 * @return - 0 if the instruction's memory could be read; nonzero if 1602 * not. 1603 */ 1604int decodeInstruction(struct InternalInstruction* insn, 1605 byteReader_t reader, 1606 void* readerArg, 1607 dlog_t logger, 1608 void* loggerArg, 1609 uint64_t startLoc, 1610 DisassemblerMode mode) { 1611 memset(insn, 0, sizeof(struct InternalInstruction)); 1612 1613 insn->reader = reader; 1614 insn->readerArg = readerArg; 1615 insn->dlog = logger; 1616 insn->dlogArg = loggerArg; 1617 insn->startLocation = startLoc; 1618 insn->readerCursor = startLoc; 1619 insn->mode = mode; 1620 insn->numImmediatesConsumed = 0; 1621 1622 if (readPrefixes(insn) || 1623 readOpcode(insn) || 1624 getID(insn) || 1625 insn->instructionID == 0 || 1626 readOperands(insn)) 1627 return -1; 1628 1629 insn->length = insn->readerCursor - insn->startLocation; 1630 1631 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu", 1632 startLoc, insn->readerCursor, insn->length); 1633 1634 if (insn->length > 15) 1635 dbgprintf(insn, "Instruction exceeds 15-byte limit"); 1636 1637 return 0; 1638} 1639