X86DisassemblerDecoder.c revision 29480fd798dc6452948f63825ff41c66f09c2493
1/*===- X86DisassemblerDecoder.c - Disassembler decoder -------------*- C -*-==* 2 * 3 * The LLVM Compiler Infrastructure 4 * 5 * This file is distributed under the University of Illinois Open Source 6 * License. See LICENSE.TXT for details. 7 * 8 *===----------------------------------------------------------------------===* 9 * 10 * This file is part of the X86 Disassembler. 11 * It contains the implementation of the instruction decoder. 12 * Documentation for the disassembler can be found in X86Disassembler.h. 13 * 14 *===----------------------------------------------------------------------===*/ 15 16#include <stdarg.h> /* for va_*() */ 17#include <stdio.h> /* for vsnprintf() */ 18#include <stdlib.h> /* for exit() */ 19#include <string.h> /* for memset() */ 20 21#include "X86DisassemblerDecoder.h" 22 23#include "X86GenDisassemblerTables.inc" 24 25#define TRUE 1 26#define FALSE 0 27 28typedef int8_t bool; 29 30#ifndef NDEBUG 31#define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0) 32#else 33#define debug(s) do { } while (0) 34#endif 35 36 37/* 38 * contextForAttrs - Client for the instruction context table. Takes a set of 39 * attributes and returns the appropriate decode context. 40 * 41 * @param attrMask - Attributes, from the enumeration attributeBits. 42 * @return - The InstructionContext to use when looking up an 43 * an instruction with these attributes. 44 */ 45static InstructionContext contextForAttrs(uint8_t attrMask) { 46 return CONTEXTS_SYM[attrMask]; 47} 48 49/* 50 * modRMRequired - Reads the appropriate instruction table to determine whether 51 * the ModR/M byte is required to decode a particular instruction. 52 * 53 * @param type - The opcode type (i.e., how many bytes it has). 54 * @param insnContext - The context for the instruction, as returned by 55 * contextForAttrs. 56 * @param opcode - The last byte of the instruction's opcode, not counting 57 * ModR/M extensions and escapes. 58 * @return - TRUE if the ModR/M byte is required, FALSE otherwise. 59 */ 60static int modRMRequired(OpcodeType type, 61 InstructionContext insnContext, 62 uint8_t opcode) { 63 const struct ContextDecision* decision = 0; 64 65 switch (type) { 66 case ONEBYTE: 67 decision = &ONEBYTE_SYM; 68 break; 69 case TWOBYTE: 70 decision = &TWOBYTE_SYM; 71 break; 72 case THREEBYTE_38: 73 decision = &THREEBYTE38_SYM; 74 break; 75 case THREEBYTE_3A: 76 decision = &THREEBYTE3A_SYM; 77 break; 78 case THREEBYTE_A6: 79 decision = &THREEBYTEA6_SYM; 80 break; 81 case THREEBYTE_A7: 82 decision = &THREEBYTEA7_SYM; 83 break; 84 } 85 86 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode]. 87 modrm_type != MODRM_ONEENTRY; 88 89 return 0; 90} 91 92/* 93 * decode - Reads the appropriate instruction table to obtain the unique ID of 94 * an instruction. 95 * 96 * @param type - See modRMRequired(). 97 * @param insnContext - See modRMRequired(). 98 * @param opcode - See modRMRequired(). 99 * @param modRM - The ModR/M byte if required, or any value if not. 100 * @return - The UID of the instruction, or 0 on failure. 101 */ 102static InstrUID decode(OpcodeType type, 103 InstructionContext insnContext, 104 uint8_t opcode, 105 uint8_t modRM) { 106 const struct ModRMDecision* dec; 107 108 switch (type) { 109 default: 110 debug("Unknown opcode type"); 111 return 0; 112 case ONEBYTE: 113 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 114 break; 115 case TWOBYTE: 116 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 117 break; 118 case THREEBYTE_38: 119 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 120 break; 121 case THREEBYTE_3A: 122 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 123 break; 124 case THREEBYTE_A6: 125 dec = &THREEBYTEA6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 126 break; 127 case THREEBYTE_A7: 128 dec = &THREEBYTEA7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; 129 break; 130 } 131 132 switch (dec->modrm_type) { 133 default: 134 debug("Corrupt table! Unknown modrm_type"); 135 return 0; 136 case MODRM_ONEENTRY: 137 return dec->instructionIDs[0]; 138 case MODRM_SPLITRM: 139 if (modFromModRM(modRM) == 0x3) 140 return dec->instructionIDs[1]; 141 else 142 return dec->instructionIDs[0]; 143 case MODRM_FULL: 144 return dec->instructionIDs[modRM]; 145 } 146} 147 148/* 149 * specifierForUID - Given a UID, returns the name and operand specification for 150 * that instruction. 151 * 152 * @param uid - The unique ID for the instruction. This should be returned by 153 * decode(); specifierForUID will not check bounds. 154 * @return - A pointer to the specification for that instruction. 155 */ 156static const struct InstructionSpecifier *specifierForUID(InstrUID uid) { 157 return &INSTRUCTIONS_SYM[uid]; 158} 159 160/* 161 * consumeByte - Uses the reader function provided by the user to consume one 162 * byte from the instruction's memory and advance the cursor. 163 * 164 * @param insn - The instruction with the reader function to use. The cursor 165 * for this instruction is advanced. 166 * @param byte - A pointer to a pre-allocated memory buffer to be populated 167 * with the data read. 168 * @return - 0 if the read was successful; nonzero otherwise. 169 */ 170static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) { 171 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor); 172 173 if (!ret) 174 ++(insn->readerCursor); 175 176 return ret; 177} 178 179/* 180 * lookAtByte - Like consumeByte, but does not advance the cursor. 181 * 182 * @param insn - See consumeByte(). 183 * @param byte - See consumeByte(). 184 * @return - See consumeByte(). 185 */ 186static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) { 187 return insn->reader(insn->readerArg, byte, insn->readerCursor); 188} 189 190static void unconsumeByte(struct InternalInstruction* insn) { 191 insn->readerCursor--; 192} 193 194#define CONSUME_FUNC(name, type) \ 195 static int name(struct InternalInstruction* insn, type* ptr) { \ 196 type combined = 0; \ 197 unsigned offset; \ 198 for (offset = 0; offset < sizeof(type); ++offset) { \ 199 uint8_t byte; \ 200 int ret = insn->reader(insn->readerArg, \ 201 &byte, \ 202 insn->readerCursor + offset); \ 203 if (ret) \ 204 return ret; \ 205 combined = combined | ((type)byte << ((type)offset * 8)); \ 206 } \ 207 *ptr = combined; \ 208 insn->readerCursor += sizeof(type); \ 209 return 0; \ 210 } 211 212/* 213 * consume* - Use the reader function provided by the user to consume data 214 * values of various sizes from the instruction's memory and advance the 215 * cursor appropriately. These readers perform endian conversion. 216 * 217 * @param insn - See consumeByte(). 218 * @param ptr - A pointer to a pre-allocated memory of appropriate size to 219 * be populated with the data read. 220 * @return - See consumeByte(). 221 */ 222CONSUME_FUNC(consumeInt8, int8_t) 223CONSUME_FUNC(consumeInt16, int16_t) 224CONSUME_FUNC(consumeInt32, int32_t) 225CONSUME_FUNC(consumeUInt16, uint16_t) 226CONSUME_FUNC(consumeUInt32, uint32_t) 227CONSUME_FUNC(consumeUInt64, uint64_t) 228 229/* 230 * dbgprintf - Uses the logging function provided by the user to log a single 231 * message, typically without a carriage-return. 232 * 233 * @param insn - The instruction containing the logging function. 234 * @param format - See printf(). 235 * @param ... - See printf(). 236 */ 237static void dbgprintf(struct InternalInstruction* insn, 238 const char* format, 239 ...) { 240 char buffer[256]; 241 va_list ap; 242 243 if (!insn->dlog) 244 return; 245 246 va_start(ap, format); 247 (void)vsnprintf(buffer, sizeof(buffer), format, ap); 248 va_end(ap); 249 250 insn->dlog(insn->dlogArg, buffer); 251 252 return; 253} 254 255/* 256 * setPrefixPresent - Marks that a particular prefix is present at a particular 257 * location. 258 * 259 * @param insn - The instruction to be marked as having the prefix. 260 * @param prefix - The prefix that is present. 261 * @param location - The location where the prefix is located (in the address 262 * space of the instruction's reader). 263 */ 264static void setPrefixPresent(struct InternalInstruction* insn, 265 uint8_t prefix, 266 uint64_t location) 267{ 268 insn->prefixPresent[prefix] = 1; 269 insn->prefixLocations[prefix] = location; 270} 271 272/* 273 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is 274 * present at a given location. 275 * 276 * @param insn - The instruction to be queried. 277 * @param prefix - The prefix. 278 * @param location - The location to query. 279 * @return - Whether the prefix is at that location. 280 */ 281static BOOL isPrefixAtLocation(struct InternalInstruction* insn, 282 uint8_t prefix, 283 uint64_t location) 284{ 285 if (insn->prefixPresent[prefix] == 1 && 286 insn->prefixLocations[prefix] == location) 287 return TRUE; 288 else 289 return FALSE; 290} 291 292/* 293 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the 294 * instruction as having them. Also sets the instruction's default operand, 295 * address, and other relevant data sizes to report operands correctly. 296 * 297 * @param insn - The instruction whose prefixes are to be read. 298 * @return - 0 if the instruction could be read until the end of the prefix 299 * bytes, and no prefixes conflicted; nonzero otherwise. 300 */ 301static int readPrefixes(struct InternalInstruction* insn) { 302 BOOL isPrefix = TRUE; 303 BOOL prefixGroups[4] = { FALSE }; 304 uint64_t prefixLocation; 305 uint8_t byte = 0; 306 307 BOOL hasAdSize = FALSE; 308 BOOL hasOpSize = FALSE; 309 310 dbgprintf(insn, "readPrefixes()"); 311 312 while (isPrefix) { 313 prefixLocation = insn->readerCursor; 314 315 if (consumeByte(insn, &byte)) 316 return -1; 317 318 switch (byte) { 319 case 0xf0: /* LOCK */ 320 case 0xf2: /* REPNE/REPNZ */ 321 case 0xf3: /* REP or REPE/REPZ */ 322 if (prefixGroups[0]) 323 dbgprintf(insn, "Redundant Group 1 prefix"); 324 prefixGroups[0] = TRUE; 325 setPrefixPresent(insn, byte, prefixLocation); 326 break; 327 case 0x2e: /* CS segment override -OR- Branch not taken */ 328 case 0x36: /* SS segment override -OR- Branch taken */ 329 case 0x3e: /* DS segment override */ 330 case 0x26: /* ES segment override */ 331 case 0x64: /* FS segment override */ 332 case 0x65: /* GS segment override */ 333 switch (byte) { 334 case 0x2e: 335 insn->segmentOverride = SEG_OVERRIDE_CS; 336 break; 337 case 0x36: 338 insn->segmentOverride = SEG_OVERRIDE_SS; 339 break; 340 case 0x3e: 341 insn->segmentOverride = SEG_OVERRIDE_DS; 342 break; 343 case 0x26: 344 insn->segmentOverride = SEG_OVERRIDE_ES; 345 break; 346 case 0x64: 347 insn->segmentOverride = SEG_OVERRIDE_FS; 348 break; 349 case 0x65: 350 insn->segmentOverride = SEG_OVERRIDE_GS; 351 break; 352 default: 353 debug("Unhandled override"); 354 return -1; 355 } 356 if (prefixGroups[1]) 357 dbgprintf(insn, "Redundant Group 2 prefix"); 358 prefixGroups[1] = TRUE; 359 setPrefixPresent(insn, byte, prefixLocation); 360 break; 361 case 0x66: /* Operand-size override */ 362 if (prefixGroups[2]) 363 dbgprintf(insn, "Redundant Group 3 prefix"); 364 prefixGroups[2] = TRUE; 365 hasOpSize = TRUE; 366 setPrefixPresent(insn, byte, prefixLocation); 367 break; 368 case 0x67: /* Address-size override */ 369 if (prefixGroups[3]) 370 dbgprintf(insn, "Redundant Group 4 prefix"); 371 prefixGroups[3] = TRUE; 372 hasAdSize = TRUE; 373 setPrefixPresent(insn, byte, prefixLocation); 374 break; 375 default: /* Not a prefix byte */ 376 isPrefix = FALSE; 377 break; 378 } 379 380 if (isPrefix) 381 dbgprintf(insn, "Found prefix 0x%hhx", byte); 382 } 383 384 insn->vexSize = 0; 385 386 if (byte == 0xc4) { 387 uint8_t byte1; 388 389 if (lookAtByte(insn, &byte1)) { 390 dbgprintf(insn, "Couldn't read second byte of VEX"); 391 return -1; 392 } 393 394 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) { 395 insn->vexSize = 3; 396 insn->necessaryPrefixLocation = insn->readerCursor - 1; 397 } 398 else { 399 unconsumeByte(insn); 400 insn->necessaryPrefixLocation = insn->readerCursor - 1; 401 } 402 403 if (insn->vexSize == 3) { 404 insn->vexPrefix[0] = byte; 405 consumeByte(insn, &insn->vexPrefix[1]); 406 consumeByte(insn, &insn->vexPrefix[2]); 407 408 /* We simulate the REX prefix for simplicity's sake */ 409 410 if (insn->mode == MODE_64BIT) { 411 insn->rexPrefix = 0x40 412 | (wFromVEX3of3(insn->vexPrefix[2]) << 3) 413 | (rFromVEX2of3(insn->vexPrefix[1]) << 2) 414 | (xFromVEX2of3(insn->vexPrefix[1]) << 1) 415 | (bFromVEX2of3(insn->vexPrefix[1]) << 0); 416 } 417 418 switch (ppFromVEX3of3(insn->vexPrefix[2])) 419 { 420 default: 421 break; 422 case VEX_PREFIX_66: 423 hasOpSize = TRUE; 424 break; 425 } 426 427 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1], insn->vexPrefix[2]); 428 } 429 } 430 else if (byte == 0xc5) { 431 uint8_t byte1; 432 433 if (lookAtByte(insn, &byte1)) { 434 dbgprintf(insn, "Couldn't read second byte of VEX"); 435 return -1; 436 } 437 438 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) { 439 insn->vexSize = 2; 440 } 441 else { 442 unconsumeByte(insn); 443 } 444 445 if (insn->vexSize == 2) { 446 insn->vexPrefix[0] = byte; 447 consumeByte(insn, &insn->vexPrefix[1]); 448 449 if (insn->mode == MODE_64BIT) { 450 insn->rexPrefix = 0x40 451 | (rFromVEX2of2(insn->vexPrefix[1]) << 2); 452 } 453 454 switch (ppFromVEX2of2(insn->vexPrefix[1])) 455 { 456 default: 457 break; 458 case VEX_PREFIX_66: 459 hasOpSize = TRUE; 460 break; 461 } 462 463 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1]); 464 } 465 } 466 else { 467 if (insn->mode == MODE_64BIT) { 468 if ((byte & 0xf0) == 0x40) { 469 uint8_t opcodeByte; 470 471 if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) { 472 dbgprintf(insn, "Redundant REX prefix"); 473 return -1; 474 } 475 476 insn->rexPrefix = byte; 477 insn->necessaryPrefixLocation = insn->readerCursor - 2; 478 479 dbgprintf(insn, "Found REX prefix 0x%hhx", byte); 480 } else { 481 unconsumeByte(insn); 482 insn->necessaryPrefixLocation = insn->readerCursor - 1; 483 } 484 } else { 485 unconsumeByte(insn); 486 insn->necessaryPrefixLocation = insn->readerCursor - 1; 487 } 488 } 489 490 if (insn->mode == MODE_16BIT) { 491 insn->registerSize = (hasOpSize ? 4 : 2); 492 insn->addressSize = (hasAdSize ? 4 : 2); 493 insn->displacementSize = (hasAdSize ? 4 : 2); 494 insn->immediateSize = (hasOpSize ? 4 : 2); 495 } else if (insn->mode == MODE_32BIT) { 496 insn->registerSize = (hasOpSize ? 2 : 4); 497 insn->addressSize = (hasAdSize ? 2 : 4); 498 insn->displacementSize = (hasAdSize ? 2 : 4); 499 insn->immediateSize = (hasOpSize ? 2 : 4); 500 } else if (insn->mode == MODE_64BIT) { 501 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) { 502 insn->registerSize = 8; 503 insn->addressSize = (hasAdSize ? 4 : 8); 504 insn->displacementSize = 4; 505 insn->immediateSize = 4; 506 } else if (insn->rexPrefix) { 507 insn->registerSize = (hasOpSize ? 2 : 4); 508 insn->addressSize = (hasAdSize ? 4 : 8); 509 insn->displacementSize = (hasOpSize ? 2 : 4); 510 insn->immediateSize = (hasOpSize ? 2 : 4); 511 } else { 512 insn->registerSize = (hasOpSize ? 2 : 4); 513 insn->addressSize = (hasAdSize ? 4 : 8); 514 insn->displacementSize = (hasOpSize ? 2 : 4); 515 insn->immediateSize = (hasOpSize ? 2 : 4); 516 } 517 } 518 519 return 0; 520} 521 522/* 523 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of 524 * extended or escape opcodes). 525 * 526 * @param insn - The instruction whose opcode is to be read. 527 * @return - 0 if the opcode could be read successfully; nonzero otherwise. 528 */ 529static int readOpcode(struct InternalInstruction* insn) { 530 /* Determine the length of the primary opcode */ 531 532 uint8_t current; 533 534 dbgprintf(insn, "readOpcode()"); 535 536 insn->opcodeType = ONEBYTE; 537 538 if (insn->vexSize == 3) 539 { 540 switch (mmmmmFromVEX2of3(insn->vexPrefix[1])) 541 { 542 default: 543 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", mmmmmFromVEX2of3(insn->vexPrefix[1])); 544 return -1; 545 case 0: 546 break; 547 case VEX_LOB_0F: 548 insn->twoByteEscape = 0x0f; 549 insn->opcodeType = TWOBYTE; 550 return consumeByte(insn, &insn->opcode); 551 case VEX_LOB_0F38: 552 insn->twoByteEscape = 0x0f; 553 insn->threeByteEscape = 0x38; 554 insn->opcodeType = THREEBYTE_38; 555 return consumeByte(insn, &insn->opcode); 556 case VEX_LOB_0F3A: 557 insn->twoByteEscape = 0x0f; 558 insn->threeByteEscape = 0x3a; 559 insn->opcodeType = THREEBYTE_3A; 560 return consumeByte(insn, &insn->opcode); 561 } 562 } 563 else if (insn->vexSize == 2) 564 { 565 insn->twoByteEscape = 0x0f; 566 insn->opcodeType = TWOBYTE; 567 return consumeByte(insn, &insn->opcode); 568 } 569 570 if (consumeByte(insn, ¤t)) 571 return -1; 572 573 if (current == 0x0f) { 574 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current); 575 576 insn->twoByteEscape = current; 577 578 if (consumeByte(insn, ¤t)) 579 return -1; 580 581 if (current == 0x38) { 582 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); 583 584 insn->threeByteEscape = current; 585 586 if (consumeByte(insn, ¤t)) 587 return -1; 588 589 insn->opcodeType = THREEBYTE_38; 590 } else if (current == 0x3a) { 591 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); 592 593 insn->threeByteEscape = current; 594 595 if (consumeByte(insn, ¤t)) 596 return -1; 597 598 insn->opcodeType = THREEBYTE_3A; 599 } else if (current == 0xa6) { 600 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); 601 602 insn->threeByteEscape = current; 603 604 if (consumeByte(insn, ¤t)) 605 return -1; 606 607 insn->opcodeType = THREEBYTE_A6; 608 } else if (current == 0xa7) { 609 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); 610 611 insn->threeByteEscape = current; 612 613 if (consumeByte(insn, ¤t)) 614 return -1; 615 616 insn->opcodeType = THREEBYTE_A7; 617 } else { 618 dbgprintf(insn, "Didn't find a three-byte escape prefix"); 619 620 insn->opcodeType = TWOBYTE; 621 } 622 } 623 624 /* 625 * At this point we have consumed the full opcode. 626 * Anything we consume from here on must be unconsumed. 627 */ 628 629 insn->opcode = current; 630 631 return 0; 632} 633 634static int readModRM(struct InternalInstruction* insn); 635 636/* 637 * getIDWithAttrMask - Determines the ID of an instruction, consuming 638 * the ModR/M byte as appropriate for extended and escape opcodes, 639 * and using a supplied attribute mask. 640 * 641 * @param instructionID - A pointer whose target is filled in with the ID of the 642 * instruction. 643 * @param insn - The instruction whose ID is to be determined. 644 * @param attrMask - The attribute mask to search. 645 * @return - 0 if the ModR/M could be read when needed or was not 646 * needed; nonzero otherwise. 647 */ 648static int getIDWithAttrMask(uint16_t* instructionID, 649 struct InternalInstruction* insn, 650 uint8_t attrMask) { 651 BOOL hasModRMExtension; 652 653 uint8_t instructionClass; 654 655 instructionClass = contextForAttrs(attrMask); 656 657 hasModRMExtension = modRMRequired(insn->opcodeType, 658 instructionClass, 659 insn->opcode); 660 661 if (hasModRMExtension) { 662 if (readModRM(insn)) 663 return -1; 664 665 *instructionID = decode(insn->opcodeType, 666 instructionClass, 667 insn->opcode, 668 insn->modRM); 669 } else { 670 *instructionID = decode(insn->opcodeType, 671 instructionClass, 672 insn->opcode, 673 0); 674 } 675 676 return 0; 677} 678 679/* 680 * is16BitEquivalent - Determines whether two instruction names refer to 681 * equivalent instructions but one is 16-bit whereas the other is not. 682 * 683 * @param orig - The instruction that is not 16-bit 684 * @param equiv - The instruction that is 16-bit 685 */ 686static BOOL is16BitEquvalent(const char* orig, const char* equiv) { 687 off_t i; 688 689 for (i = 0;; i++) { 690 if (orig[i] == '\0' && equiv[i] == '\0') 691 return TRUE; 692 if (orig[i] == '\0' || equiv[i] == '\0') 693 return FALSE; 694 if (orig[i] != equiv[i]) { 695 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W') 696 continue; 697 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1') 698 continue; 699 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6') 700 continue; 701 return FALSE; 702 } 703 } 704} 705 706/* 707 * getID - Determines the ID of an instruction, consuming the ModR/M byte as 708 * appropriate for extended and escape opcodes. Determines the attributes and 709 * context for the instruction before doing so. 710 * 711 * @param insn - The instruction whose ID is to be determined. 712 * @return - 0 if the ModR/M could be read when needed or was not needed; 713 * nonzero otherwise. 714 */ 715static int getID(struct InternalInstruction* insn) { 716 uint8_t attrMask; 717 uint16_t instructionID; 718 719 dbgprintf(insn, "getID()"); 720 721 attrMask = ATTR_NONE; 722 723 if (insn->mode == MODE_64BIT) 724 attrMask |= ATTR_64BIT; 725 726 if (insn->vexSize) { 727 attrMask |= ATTR_VEX; 728 729 if (insn->vexSize == 3) { 730 switch (ppFromVEX3of3(insn->vexPrefix[2])) { 731 case VEX_PREFIX_66: 732 attrMask |= ATTR_OPSIZE; 733 break; 734 case VEX_PREFIX_F3: 735 attrMask |= ATTR_XS; 736 break; 737 case VEX_PREFIX_F2: 738 attrMask |= ATTR_XD; 739 break; 740 } 741 742 if (lFromVEX3of3(insn->vexPrefix[2])) 743 attrMask |= ATTR_VEXL; 744 } 745 else if (insn->vexSize == 2) { 746 switch (ppFromVEX2of2(insn->vexPrefix[1])) { 747 case VEX_PREFIX_66: 748 attrMask |= ATTR_OPSIZE; 749 break; 750 case VEX_PREFIX_F3: 751 attrMask |= ATTR_XS; 752 break; 753 case VEX_PREFIX_F2: 754 attrMask |= ATTR_XD; 755 break; 756 } 757 758 if (lFromVEX2of2(insn->vexPrefix[1])) 759 attrMask |= ATTR_VEXL; 760 } 761 else { 762 return -1; 763 } 764 } 765 else { 766 if (isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation)) 767 attrMask |= ATTR_OPSIZE; 768 else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation)) 769 attrMask |= ATTR_XS; 770 else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation)) 771 attrMask |= ATTR_XD; 772 } 773 774 if (insn->rexPrefix & 0x08) 775 attrMask |= ATTR_REXW; 776 777 if (getIDWithAttrMask(&instructionID, insn, attrMask)) 778 return -1; 779 780 /* The following clauses compensate for limitations of the tables. */ 781 782 if ((attrMask & ATTR_VEXL) && (attrMask & ATTR_REXW)) { 783 /* 784 * Some VEX instructions ignore the L-bit, but use the W-bit. Normally L-bit 785 * has precedence since there are no L-bit with W-bit entries in the tables. 786 * So if the L-bit isn't significant we should use the W-bit instead. 787 */ 788 789 const struct InstructionSpecifier *spec; 790 uint16_t instructionIDWithWBit; 791 const struct InstructionSpecifier *specWithWBit; 792 793 spec = specifierForUID(instructionID); 794 795 if (getIDWithAttrMask(&instructionIDWithWBit, 796 insn, 797 (attrMask & (~ATTR_VEXL)) | ATTR_REXW)) { 798 insn->instructionID = instructionID; 799 insn->spec = spec; 800 return 0; 801 } 802 803 specWithWBit = specifierForUID(instructionIDWithWBit); 804 805 if (instructionID != instructionIDWithWBit) { 806 insn->instructionID = instructionIDWithWBit; 807 insn->spec = specWithWBit; 808 } else { 809 insn->instructionID = instructionID; 810 insn->spec = spec; 811 } 812 return 0; 813 } 814 815 if (insn->prefixPresent[0x66] && !(attrMask & ATTR_OPSIZE)) { 816 /* 817 * The instruction tables make no distinction between instructions that 818 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a 819 * particular spot (i.e., many MMX operations). In general we're 820 * conservative, but in the specific case where OpSize is present but not 821 * in the right place we check if there's a 16-bit operation. 822 */ 823 824 const struct InstructionSpecifier *spec; 825 uint16_t instructionIDWithOpsize; 826 const struct InstructionSpecifier *specWithOpsize; 827 828 spec = specifierForUID(instructionID); 829 830 if (getIDWithAttrMask(&instructionIDWithOpsize, 831 insn, 832 attrMask | ATTR_OPSIZE)) { 833 /* 834 * ModRM required with OpSize but not present; give up and return version 835 * without OpSize set 836 */ 837 838 insn->instructionID = instructionID; 839 insn->spec = spec; 840 return 0; 841 } 842 843 specWithOpsize = specifierForUID(instructionIDWithOpsize); 844 845 if (is16BitEquvalent(spec->name, specWithOpsize->name)) { 846 insn->instructionID = instructionIDWithOpsize; 847 insn->spec = specWithOpsize; 848 } else { 849 insn->instructionID = instructionID; 850 insn->spec = spec; 851 } 852 return 0; 853 } 854 855 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 && 856 insn->rexPrefix & 0x01) { 857 /* 858 * NOOP shouldn't decode as NOOP if REX.b is set. Instead 859 * it should decode as XCHG %r8, %eax. 860 */ 861 862 const struct InstructionSpecifier *spec; 863 uint16_t instructionIDWithNewOpcode; 864 const struct InstructionSpecifier *specWithNewOpcode; 865 866 spec = specifierForUID(instructionID); 867 868 /* Borrow opcode from one of the other XCHGar opcodes */ 869 insn->opcode = 0x91; 870 871 if (getIDWithAttrMask(&instructionIDWithNewOpcode, 872 insn, 873 attrMask)) { 874 insn->opcode = 0x90; 875 876 insn->instructionID = instructionID; 877 insn->spec = spec; 878 return 0; 879 } 880 881 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode); 882 883 /* Change back */ 884 insn->opcode = 0x90; 885 886 insn->instructionID = instructionIDWithNewOpcode; 887 insn->spec = specWithNewOpcode; 888 889 return 0; 890 } 891 892 insn->instructionID = instructionID; 893 insn->spec = specifierForUID(insn->instructionID); 894 895 return 0; 896} 897 898/* 899 * readSIB - Consumes the SIB byte to determine addressing information for an 900 * instruction. 901 * 902 * @param insn - The instruction whose SIB byte is to be read. 903 * @return - 0 if the SIB byte was successfully read; nonzero otherwise. 904 */ 905static int readSIB(struct InternalInstruction* insn) { 906 SIBIndex sibIndexBase = 0; 907 SIBBase sibBaseBase = 0; 908 uint8_t index, base; 909 910 dbgprintf(insn, "readSIB()"); 911 912 if (insn->consumedSIB) 913 return 0; 914 915 insn->consumedSIB = TRUE; 916 917 switch (insn->addressSize) { 918 case 2: 919 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode"); 920 return -1; 921 break; 922 case 4: 923 sibIndexBase = SIB_INDEX_EAX; 924 sibBaseBase = SIB_BASE_EAX; 925 break; 926 case 8: 927 sibIndexBase = SIB_INDEX_RAX; 928 sibBaseBase = SIB_BASE_RAX; 929 break; 930 } 931 932 if (consumeByte(insn, &insn->sib)) 933 return -1; 934 935 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3); 936 937 switch (index) { 938 case 0x4: 939 insn->sibIndex = SIB_INDEX_NONE; 940 break; 941 default: 942 insn->sibIndex = (SIBIndex)(sibIndexBase + index); 943 if (insn->sibIndex == SIB_INDEX_sib || 944 insn->sibIndex == SIB_INDEX_sib64) 945 insn->sibIndex = SIB_INDEX_NONE; 946 break; 947 } 948 949 switch (scaleFromSIB(insn->sib)) { 950 case 0: 951 insn->sibScale = 1; 952 break; 953 case 1: 954 insn->sibScale = 2; 955 break; 956 case 2: 957 insn->sibScale = 4; 958 break; 959 case 3: 960 insn->sibScale = 8; 961 break; 962 } 963 964 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3); 965 966 switch (base) { 967 case 0x5: 968 switch (modFromModRM(insn->modRM)) { 969 case 0x0: 970 insn->eaDisplacement = EA_DISP_32; 971 insn->sibBase = SIB_BASE_NONE; 972 break; 973 case 0x1: 974 insn->eaDisplacement = EA_DISP_8; 975 insn->sibBase = (insn->addressSize == 4 ? 976 SIB_BASE_EBP : SIB_BASE_RBP); 977 break; 978 case 0x2: 979 insn->eaDisplacement = EA_DISP_32; 980 insn->sibBase = (insn->addressSize == 4 ? 981 SIB_BASE_EBP : SIB_BASE_RBP); 982 break; 983 case 0x3: 984 debug("Cannot have Mod = 0b11 and a SIB byte"); 985 return -1; 986 } 987 break; 988 default: 989 insn->sibBase = (SIBBase)(sibBaseBase + base); 990 break; 991 } 992 993 return 0; 994} 995 996/* 997 * readDisplacement - Consumes the displacement of an instruction. 998 * 999 * @param insn - The instruction whose displacement is to be read. 1000 * @return - 0 if the displacement byte was successfully read; nonzero 1001 * otherwise. 1002 */ 1003static int readDisplacement(struct InternalInstruction* insn) { 1004 int8_t d8; 1005 int16_t d16; 1006 int32_t d32; 1007 1008 dbgprintf(insn, "readDisplacement()"); 1009 1010 if (insn->consumedDisplacement) 1011 return 0; 1012 1013 insn->consumedDisplacement = TRUE; 1014 1015 switch (insn->eaDisplacement) { 1016 case EA_DISP_NONE: 1017 insn->consumedDisplacement = FALSE; 1018 break; 1019 case EA_DISP_8: 1020 if (consumeInt8(insn, &d8)) 1021 return -1; 1022 insn->displacement = d8; 1023 break; 1024 case EA_DISP_16: 1025 if (consumeInt16(insn, &d16)) 1026 return -1; 1027 insn->displacement = d16; 1028 break; 1029 case EA_DISP_32: 1030 if (consumeInt32(insn, &d32)) 1031 return -1; 1032 insn->displacement = d32; 1033 break; 1034 } 1035 1036 insn->consumedDisplacement = TRUE; 1037 return 0; 1038} 1039 1040/* 1041 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and 1042 * displacement) for an instruction and interprets it. 1043 * 1044 * @param insn - The instruction whose addressing information is to be read. 1045 * @return - 0 if the information was successfully read; nonzero otherwise. 1046 */ 1047static int readModRM(struct InternalInstruction* insn) { 1048 uint8_t mod, rm, reg; 1049 1050 dbgprintf(insn, "readModRM()"); 1051 1052 if (insn->consumedModRM) 1053 return 0; 1054 1055 if (consumeByte(insn, &insn->modRM)) 1056 return -1; 1057 insn->consumedModRM = TRUE; 1058 1059 mod = modFromModRM(insn->modRM); 1060 rm = rmFromModRM(insn->modRM); 1061 reg = regFromModRM(insn->modRM); 1062 1063 /* 1064 * This goes by insn->registerSize to pick the correct register, which messes 1065 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in 1066 * fixupReg(). 1067 */ 1068 switch (insn->registerSize) { 1069 case 2: 1070 insn->regBase = MODRM_REG_AX; 1071 insn->eaRegBase = EA_REG_AX; 1072 break; 1073 case 4: 1074 insn->regBase = MODRM_REG_EAX; 1075 insn->eaRegBase = EA_REG_EAX; 1076 break; 1077 case 8: 1078 insn->regBase = MODRM_REG_RAX; 1079 insn->eaRegBase = EA_REG_RAX; 1080 break; 1081 } 1082 1083 reg |= rFromREX(insn->rexPrefix) << 3; 1084 rm |= bFromREX(insn->rexPrefix) << 3; 1085 1086 insn->reg = (Reg)(insn->regBase + reg); 1087 1088 switch (insn->addressSize) { 1089 case 2: 1090 insn->eaBaseBase = EA_BASE_BX_SI; 1091 1092 switch (mod) { 1093 case 0x0: 1094 if (rm == 0x6) { 1095 insn->eaBase = EA_BASE_NONE; 1096 insn->eaDisplacement = EA_DISP_16; 1097 if (readDisplacement(insn)) 1098 return -1; 1099 } else { 1100 insn->eaBase = (EABase)(insn->eaBaseBase + rm); 1101 insn->eaDisplacement = EA_DISP_NONE; 1102 } 1103 break; 1104 case 0x1: 1105 insn->eaBase = (EABase)(insn->eaBaseBase + rm); 1106 insn->eaDisplacement = EA_DISP_8; 1107 if (readDisplacement(insn)) 1108 return -1; 1109 break; 1110 case 0x2: 1111 insn->eaBase = (EABase)(insn->eaBaseBase + rm); 1112 insn->eaDisplacement = EA_DISP_16; 1113 if (readDisplacement(insn)) 1114 return -1; 1115 break; 1116 case 0x3: 1117 insn->eaBase = (EABase)(insn->eaRegBase + rm); 1118 if (readDisplacement(insn)) 1119 return -1; 1120 break; 1121 } 1122 break; 1123 case 4: 1124 case 8: 1125 insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX); 1126 1127 switch (mod) { 1128 case 0x0: 1129 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */ 1130 switch (rm) { 1131 case 0x4: 1132 case 0xc: /* in case REXW.b is set */ 1133 insn->eaBase = (insn->addressSize == 4 ? 1134 EA_BASE_sib : EA_BASE_sib64); 1135 readSIB(insn); 1136 if (readDisplacement(insn)) 1137 return -1; 1138 break; 1139 case 0x5: 1140 insn->eaBase = EA_BASE_NONE; 1141 insn->eaDisplacement = EA_DISP_32; 1142 if (readDisplacement(insn)) 1143 return -1; 1144 break; 1145 default: 1146 insn->eaBase = (EABase)(insn->eaBaseBase + rm); 1147 break; 1148 } 1149 break; 1150 case 0x1: 1151 case 0x2: 1152 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32); 1153 switch (rm) { 1154 case 0x4: 1155 case 0xc: /* in case REXW.b is set */ 1156 insn->eaBase = EA_BASE_sib; 1157 readSIB(insn); 1158 if (readDisplacement(insn)) 1159 return -1; 1160 break; 1161 default: 1162 insn->eaBase = (EABase)(insn->eaBaseBase + rm); 1163 if (readDisplacement(insn)) 1164 return -1; 1165 break; 1166 } 1167 break; 1168 case 0x3: 1169 insn->eaDisplacement = EA_DISP_NONE; 1170 insn->eaBase = (EABase)(insn->eaRegBase + rm); 1171 break; 1172 } 1173 break; 1174 } /* switch (insn->addressSize) */ 1175 1176 return 0; 1177} 1178 1179#define GENERIC_FIXUP_FUNC(name, base, prefix) \ 1180 static uint8_t name(struct InternalInstruction *insn, \ 1181 OperandType type, \ 1182 uint8_t index, \ 1183 uint8_t *valid) { \ 1184 *valid = 1; \ 1185 switch (type) { \ 1186 default: \ 1187 debug("Unhandled register type"); \ 1188 *valid = 0; \ 1189 return 0; \ 1190 case TYPE_Rv: \ 1191 return base + index; \ 1192 case TYPE_R8: \ 1193 if (insn->rexPrefix && \ 1194 index >= 4 && index <= 7) { \ 1195 return prefix##_SPL + (index - 4); \ 1196 } else { \ 1197 return prefix##_AL + index; \ 1198 } \ 1199 case TYPE_R16: \ 1200 return prefix##_AX + index; \ 1201 case TYPE_R32: \ 1202 return prefix##_EAX + index; \ 1203 case TYPE_R64: \ 1204 return prefix##_RAX + index; \ 1205 case TYPE_XMM256: \ 1206 return prefix##_YMM0 + index; \ 1207 case TYPE_XMM128: \ 1208 case TYPE_XMM64: \ 1209 case TYPE_XMM32: \ 1210 case TYPE_XMM: \ 1211 return prefix##_XMM0 + index; \ 1212 case TYPE_MM64: \ 1213 case TYPE_MM32: \ 1214 case TYPE_MM: \ 1215 if (index > 7) \ 1216 *valid = 0; \ 1217 return prefix##_MM0 + index; \ 1218 case TYPE_SEGMENTREG: \ 1219 if (index > 5) \ 1220 *valid = 0; \ 1221 return prefix##_ES + index; \ 1222 case TYPE_DEBUGREG: \ 1223 if (index > 7) \ 1224 *valid = 0; \ 1225 return prefix##_DR0 + index; \ 1226 case TYPE_CONTROLREG: \ 1227 if (index > 8) \ 1228 *valid = 0; \ 1229 return prefix##_CR0 + index; \ 1230 } \ 1231 } 1232 1233/* 1234 * fixup*Value - Consults an operand type to determine the meaning of the 1235 * reg or R/M field. If the operand is an XMM operand, for example, an 1236 * operand would be XMM0 instead of AX, which readModRM() would otherwise 1237 * misinterpret it as. 1238 * 1239 * @param insn - The instruction containing the operand. 1240 * @param type - The operand type. 1241 * @param index - The existing value of the field as reported by readModRM(). 1242 * @param valid - The address of a uint8_t. The target is set to 1 if the 1243 * field is valid for the register class; 0 if not. 1244 * @return - The proper value. 1245 */ 1246GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG) 1247GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG) 1248 1249/* 1250 * fixupReg - Consults an operand specifier to determine which of the 1251 * fixup*Value functions to use in correcting readModRM()'ss interpretation. 1252 * 1253 * @param insn - See fixup*Value(). 1254 * @param op - The operand specifier. 1255 * @return - 0 if fixup was successful; -1 if the register returned was 1256 * invalid for its class. 1257 */ 1258static int fixupReg(struct InternalInstruction *insn, 1259 const struct OperandSpecifier *op) { 1260 uint8_t valid; 1261 1262 dbgprintf(insn, "fixupReg()"); 1263 1264 switch ((OperandEncoding)op->encoding) { 1265 default: 1266 debug("Expected a REG or R/M encoding in fixupReg"); 1267 return -1; 1268 case ENCODING_VVVV: 1269 insn->vvvv = (Reg)fixupRegValue(insn, 1270 (OperandType)op->type, 1271 insn->vvvv, 1272 &valid); 1273 if (!valid) 1274 return -1; 1275 break; 1276 case ENCODING_REG: 1277 insn->reg = (Reg)fixupRegValue(insn, 1278 (OperandType)op->type, 1279 insn->reg - insn->regBase, 1280 &valid); 1281 if (!valid) 1282 return -1; 1283 break; 1284 case ENCODING_RM: 1285 if (insn->eaBase >= insn->eaRegBase) { 1286 insn->eaBase = (EABase)fixupRMValue(insn, 1287 (OperandType)op->type, 1288 insn->eaBase - insn->eaRegBase, 1289 &valid); 1290 if (!valid) 1291 return -1; 1292 } 1293 break; 1294 } 1295 1296 return 0; 1297} 1298 1299/* 1300 * readOpcodeModifier - Reads an operand from the opcode field of an 1301 * instruction. Handles AddRegFrm instructions. 1302 * 1303 * @param insn - The instruction whose opcode field is to be read. 1304 * @param inModRM - Indicates that the opcode field is to be read from the 1305 * ModR/M extension; useful for escape opcodes 1306 * @return - 0 on success; nonzero otherwise. 1307 */ 1308static int readOpcodeModifier(struct InternalInstruction* insn) { 1309 dbgprintf(insn, "readOpcodeModifier()"); 1310 1311 if (insn->consumedOpcodeModifier) 1312 return 0; 1313 1314 insn->consumedOpcodeModifier = TRUE; 1315 1316 switch (insn->spec->modifierType) { 1317 default: 1318 debug("Unknown modifier type."); 1319 return -1; 1320 case MODIFIER_NONE: 1321 debug("No modifier but an operand expects one."); 1322 return -1; 1323 case MODIFIER_OPCODE: 1324 insn->opcodeModifier = insn->opcode - insn->spec->modifierBase; 1325 return 0; 1326 case MODIFIER_MODRM: 1327 insn->opcodeModifier = insn->modRM - insn->spec->modifierBase; 1328 return 0; 1329 } 1330} 1331 1332/* 1333 * readOpcodeRegister - Reads an operand from the opcode field of an 1334 * instruction and interprets it appropriately given the operand width. 1335 * Handles AddRegFrm instructions. 1336 * 1337 * @param insn - See readOpcodeModifier(). 1338 * @param size - The width (in bytes) of the register being specified. 1339 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means 1340 * RAX. 1341 * @return - 0 on success; nonzero otherwise. 1342 */ 1343static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) { 1344 dbgprintf(insn, "readOpcodeRegister()"); 1345 1346 if (readOpcodeModifier(insn)) 1347 return -1; 1348 1349 if (size == 0) 1350 size = insn->registerSize; 1351 1352 switch (size) { 1353 case 1: 1354 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3) 1355 | insn->opcodeModifier)); 1356 if (insn->rexPrefix && 1357 insn->opcodeRegister >= MODRM_REG_AL + 0x4 && 1358 insn->opcodeRegister < MODRM_REG_AL + 0x8) { 1359 insn->opcodeRegister = (Reg)(MODRM_REG_SPL 1360 + (insn->opcodeRegister - MODRM_REG_AL - 4)); 1361 } 1362 1363 break; 1364 case 2: 1365 insn->opcodeRegister = (Reg)(MODRM_REG_AX 1366 + ((bFromREX(insn->rexPrefix) << 3) 1367 | insn->opcodeModifier)); 1368 break; 1369 case 4: 1370 insn->opcodeRegister = (Reg)(MODRM_REG_EAX 1371 + ((bFromREX(insn->rexPrefix) << 3) 1372 | insn->opcodeModifier)); 1373 break; 1374 case 8: 1375 insn->opcodeRegister = (Reg)(MODRM_REG_RAX 1376 + ((bFromREX(insn->rexPrefix) << 3) 1377 | insn->opcodeModifier)); 1378 break; 1379 } 1380 1381 return 0; 1382} 1383 1384/* 1385 * readImmediate - Consumes an immediate operand from an instruction, given the 1386 * desired operand size. 1387 * 1388 * @param insn - The instruction whose operand is to be read. 1389 * @param size - The width (in bytes) of the operand. 1390 * @return - 0 if the immediate was successfully consumed; nonzero 1391 * otherwise. 1392 */ 1393static int readImmediate(struct InternalInstruction* insn, uint8_t size) { 1394 uint8_t imm8; 1395 uint16_t imm16; 1396 uint32_t imm32; 1397 uint64_t imm64; 1398 1399 dbgprintf(insn, "readImmediate()"); 1400 1401 if (insn->numImmediatesConsumed == 2) { 1402 debug("Already consumed two immediates"); 1403 return -1; 1404 } 1405 1406 if (size == 0) 1407 size = insn->immediateSize; 1408 else 1409 insn->immediateSize = size; 1410 1411 switch (size) { 1412 case 1: 1413 if (consumeByte(insn, &imm8)) 1414 return -1; 1415 insn->immediates[insn->numImmediatesConsumed] = imm8; 1416 break; 1417 case 2: 1418 if (consumeUInt16(insn, &imm16)) 1419 return -1; 1420 insn->immediates[insn->numImmediatesConsumed] = imm16; 1421 break; 1422 case 4: 1423 if (consumeUInt32(insn, &imm32)) 1424 return -1; 1425 insn->immediates[insn->numImmediatesConsumed] = imm32; 1426 break; 1427 case 8: 1428 if (consumeUInt64(insn, &imm64)) 1429 return -1; 1430 insn->immediates[insn->numImmediatesConsumed] = imm64; 1431 break; 1432 } 1433 1434 insn->numImmediatesConsumed++; 1435 1436 return 0; 1437} 1438 1439/* 1440 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix. 1441 * 1442 * @param insn - The instruction whose operand is to be read. 1443 * @return - 0 if the vvvv was successfully consumed; nonzero 1444 * otherwise. 1445 */ 1446static int readVVVV(struct InternalInstruction* insn) { 1447 dbgprintf(insn, "readVVVV()"); 1448 1449 if (insn->vexSize == 3) 1450 insn->vvvv = vvvvFromVEX3of3(insn->vexPrefix[2]); 1451 else if (insn->vexSize == 2) 1452 insn->vvvv = vvvvFromVEX2of2(insn->vexPrefix[1]); 1453 else 1454 return -1; 1455 1456 if (insn->mode != MODE_64BIT) 1457 insn->vvvv &= 0x7; 1458 1459 return 0; 1460} 1461 1462/* 1463 * readOperands - Consults the specifier for an instruction and consumes all 1464 * operands for that instruction, interpreting them as it goes. 1465 * 1466 * @param insn - The instruction whose operands are to be read and interpreted. 1467 * @return - 0 if all operands could be read; nonzero otherwise. 1468 */ 1469static int readOperands(struct InternalInstruction* insn) { 1470 int index; 1471 int hasVVVV, needVVVV; 1472 1473 dbgprintf(insn, "readOperands()"); 1474 1475 /* If non-zero vvvv specified, need to make sure one of the operands 1476 uses it. */ 1477 hasVVVV = !readVVVV(insn); 1478 needVVVV = hasVVVV && (insn->vvvv != 0); 1479 1480 for (index = 0; index < X86_MAX_OPERANDS; ++index) { 1481 switch (insn->spec->operands[index].encoding) { 1482 case ENCODING_NONE: 1483 break; 1484 case ENCODING_REG: 1485 case ENCODING_RM: 1486 if (readModRM(insn)) 1487 return -1; 1488 if (fixupReg(insn, &insn->spec->operands[index])) 1489 return -1; 1490 break; 1491 case ENCODING_CB: 1492 case ENCODING_CW: 1493 case ENCODING_CD: 1494 case ENCODING_CP: 1495 case ENCODING_CO: 1496 case ENCODING_CT: 1497 dbgprintf(insn, "We currently don't hande code-offset encodings"); 1498 return -1; 1499 case ENCODING_IB: 1500 if (readImmediate(insn, 1)) 1501 return -1; 1502 if (insn->spec->operands[index].type == TYPE_IMM3 && 1503 insn->immediates[insn->numImmediatesConsumed - 1] > 7) 1504 return -1; 1505 break; 1506 case ENCODING_IW: 1507 if (readImmediate(insn, 2)) 1508 return -1; 1509 break; 1510 case ENCODING_ID: 1511 if (readImmediate(insn, 4)) 1512 return -1; 1513 break; 1514 case ENCODING_IO: 1515 if (readImmediate(insn, 8)) 1516 return -1; 1517 break; 1518 case ENCODING_Iv: 1519 if (readImmediate(insn, insn->immediateSize)) 1520 return -1; 1521 break; 1522 case ENCODING_Ia: 1523 if (readImmediate(insn, insn->addressSize)) 1524 return -1; 1525 break; 1526 case ENCODING_RB: 1527 if (readOpcodeRegister(insn, 1)) 1528 return -1; 1529 break; 1530 case ENCODING_RW: 1531 if (readOpcodeRegister(insn, 2)) 1532 return -1; 1533 break; 1534 case ENCODING_RD: 1535 if (readOpcodeRegister(insn, 4)) 1536 return -1; 1537 break; 1538 case ENCODING_RO: 1539 if (readOpcodeRegister(insn, 8)) 1540 return -1; 1541 break; 1542 case ENCODING_Rv: 1543 if (readOpcodeRegister(insn, 0)) 1544 return -1; 1545 break; 1546 case ENCODING_I: 1547 if (readOpcodeModifier(insn)) 1548 return -1; 1549 break; 1550 case ENCODING_VVVV: 1551 needVVVV = 0; /* Mark that we have found a VVVV operand. */ 1552 if (!hasVVVV) 1553 return -1; 1554 if (fixupReg(insn, &insn->spec->operands[index])) 1555 return -1; 1556 break; 1557 case ENCODING_DUP: 1558 break; 1559 default: 1560 dbgprintf(insn, "Encountered an operand with an unknown encoding."); 1561 return -1; 1562 } 1563 } 1564 1565 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */ 1566 if (needVVVV) return -1; 1567 1568 return 0; 1569} 1570 1571/* 1572 * decodeInstruction - Reads and interprets a full instruction provided by the 1573 * user. 1574 * 1575 * @param insn - A pointer to the instruction to be populated. Must be 1576 * pre-allocated. 1577 * @param reader - The function to be used to read the instruction's bytes. 1578 * @param readerArg - A generic argument to be passed to the reader to store 1579 * any internal state. 1580 * @param logger - If non-NULL, the function to be used to write log messages 1581 * and warnings. 1582 * @param loggerArg - A generic argument to be passed to the logger to store 1583 * any internal state. 1584 * @param startLoc - The address (in the reader's address space) of the first 1585 * byte in the instruction. 1586 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to 1587 * decode the instruction in. 1588 * @return - 0 if the instruction's memory could be read; nonzero if 1589 * not. 1590 */ 1591int decodeInstruction(struct InternalInstruction* insn, 1592 byteReader_t reader, 1593 void* readerArg, 1594 dlog_t logger, 1595 void* loggerArg, 1596 uint64_t startLoc, 1597 DisassemblerMode mode) { 1598 memset(insn, 0, sizeof(struct InternalInstruction)); 1599 1600 insn->reader = reader; 1601 insn->readerArg = readerArg; 1602 insn->dlog = logger; 1603 insn->dlogArg = loggerArg; 1604 insn->startLocation = startLoc; 1605 insn->readerCursor = startLoc; 1606 insn->mode = mode; 1607 insn->numImmediatesConsumed = 0; 1608 1609 if (readPrefixes(insn) || 1610 readOpcode(insn) || 1611 getID(insn) || 1612 insn->instructionID == 0 || 1613 readOperands(insn)) 1614 return -1; 1615 1616 insn->length = insn->readerCursor - insn->startLocation; 1617 1618 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu", 1619 startLoc, insn->readerCursor, insn->length); 1620 1621 if (insn->length > 15) 1622 dbgprintf(insn, "Instruction exceeds 15-byte limit"); 1623 1624 return 0; 1625} 1626