XCoreInstrInfo.cpp revision 6ffcccab5191ef1dcde876800c24a1f58b3b7ad8
1//===- XCoreInstrInfo.cpp - XCore Instruction Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the XCore implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "XCoreMachineFunctionInfo.h" 15#include "XCoreInstrInfo.h" 16#include "XCore.h" 17#include "llvm/ADT/STLExtras.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineLocation.h" 21#include "llvm/CodeGen/MachineModuleInfo.h" 22#include "XCoreGenInstrInfo.inc" 23#include "llvm/Support/Debug.h" 24#include "llvm/Support/ErrorHandling.h" 25 26namespace llvm { 27namespace XCore { 28 29 // XCore Condition Codes 30 enum CondCode { 31 COND_TRUE, 32 COND_FALSE, 33 COND_INVALID 34 }; 35} 36} 37 38using namespace llvm; 39 40XCoreInstrInfo::XCoreInstrInfo() 41 : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts)), 42 RI(*this) { 43} 44 45static bool isZeroImm(const MachineOperand &op) { 46 return op.isImm() && op.getImm() == 0; 47} 48 49/// Return true if the instruction is a register to register move and 50/// leave the source and dest operands in the passed parameters. 51/// 52bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI, 53 unsigned &SrcReg, unsigned &DstReg, 54 unsigned &SrcSR, unsigned &DstSR) const { 55 SrcSR = DstSR = 0; // No sub-registers. 56 57 // We look for 4 kinds of patterns here: 58 // add dst, src, 0 59 // sub dst, src, 0 60 // or dst, src, src 61 // and dst, src, src 62 if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() == XCore::SUB_2rus) 63 && isZeroImm(MI.getOperand(2))) { 64 DstReg = MI.getOperand(0).getReg(); 65 SrcReg = MI.getOperand(1).getReg(); 66 return true; 67 } else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() == XCore::AND_3r) 68 && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { 69 DstReg = MI.getOperand(0).getReg(); 70 SrcReg = MI.getOperand(1).getReg(); 71 return true; 72 } 73 return false; 74} 75 76/// isLoadFromStackSlot - If the specified machine instruction is a direct 77/// load from a stack slot, return the virtual or physical register number of 78/// the destination along with the FrameIndex of the loaded stack slot. If 79/// not, return 0. This predicate must return 0 if the instruction has 80/// any side effects other than loading from the stack slot. 81unsigned 82XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{ 83 int Opcode = MI->getOpcode(); 84 if (Opcode == XCore::LDWFI) 85 { 86 if ((MI->getOperand(1).isFI()) && // is a stack slot 87 (MI->getOperand(2).isImm()) && // the imm is zero 88 (isZeroImm(MI->getOperand(2)))) 89 { 90 FrameIndex = MI->getOperand(1).getIndex(); 91 return MI->getOperand(0).getReg(); 92 } 93 } 94 return 0; 95} 96 97 /// isStoreToStackSlot - If the specified machine instruction is a direct 98 /// store to a stack slot, return the virtual or physical register number of 99 /// the source reg along with the FrameIndex of the loaded stack slot. If 100 /// not, return 0. This predicate must return 0 if the instruction has 101 /// any side effects other than storing to the stack slot. 102unsigned 103XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 104 int &FrameIndex) const { 105 int Opcode = MI->getOpcode(); 106 if (Opcode == XCore::STWFI) 107 { 108 if ((MI->getOperand(1).isFI()) && // is a stack slot 109 (MI->getOperand(2).isImm()) && // the imm is zero 110 (isZeroImm(MI->getOperand(2)))) 111 { 112 FrameIndex = MI->getOperand(1).getIndex(); 113 return MI->getOperand(0).getReg(); 114 } 115 } 116 return 0; 117} 118 119//===----------------------------------------------------------------------===// 120// Branch Analysis 121//===----------------------------------------------------------------------===// 122 123static inline bool IsBRU(unsigned BrOpc) { 124 return BrOpc == XCore::BRFU_u6 125 || BrOpc == XCore::BRFU_lu6 126 || BrOpc == XCore::BRBU_u6 127 || BrOpc == XCore::BRBU_lu6; 128} 129 130static inline bool IsBRT(unsigned BrOpc) { 131 return BrOpc == XCore::BRFT_ru6 132 || BrOpc == XCore::BRFT_lru6 133 || BrOpc == XCore::BRBT_ru6 134 || BrOpc == XCore::BRBT_lru6; 135} 136 137static inline bool IsBRF(unsigned BrOpc) { 138 return BrOpc == XCore::BRFF_ru6 139 || BrOpc == XCore::BRFF_lru6 140 || BrOpc == XCore::BRBF_ru6 141 || BrOpc == XCore::BRBF_lru6; 142} 143 144static inline bool IsCondBranch(unsigned BrOpc) { 145 return IsBRF(BrOpc) || IsBRT(BrOpc); 146} 147 148static inline bool IsBR_JT(unsigned BrOpc) { 149 return BrOpc == XCore::BR_JT 150 || BrOpc == XCore::BR_JT32; 151} 152 153/// GetCondFromBranchOpc - Return the XCore CC that matches 154/// the correspondent Branch instruction opcode. 155static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) 156{ 157 if (IsBRT(BrOpc)) { 158 return XCore::COND_TRUE; 159 } else if (IsBRF(BrOpc)) { 160 return XCore::COND_FALSE; 161 } else { 162 return XCore::COND_INVALID; 163 } 164} 165 166/// GetCondBranchFromCond - Return the Branch instruction 167/// opcode that matches the cc. 168static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) 169{ 170 switch (CC) { 171 default: llvm_unreachable("Illegal condition code!"); 172 case XCore::COND_TRUE : return XCore::BRFT_lru6; 173 case XCore::COND_FALSE : return XCore::BRFF_lru6; 174 } 175} 176 177/// GetOppositeBranchCondition - Return the inverse of the specified 178/// condition, e.g. turning COND_E to COND_NE. 179static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) 180{ 181 switch (CC) { 182 default: llvm_unreachable("Illegal condition code!"); 183 case XCore::COND_TRUE : return XCore::COND_FALSE; 184 case XCore::COND_FALSE : return XCore::COND_TRUE; 185 } 186} 187 188/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 189/// true if it cannot be understood (e.g. it's a switch dispatch or isn't 190/// implemented for a target). Upon success, this returns false and returns 191/// with the following information in various cases: 192/// 193/// 1. If this block ends with no branches (it just falls through to its succ) 194/// just return false, leaving TBB/FBB null. 195/// 2. If this block ends with only an unconditional branch, it sets TBB to be 196/// the destination block. 197/// 3. If this block ends with an conditional branch and it falls through to 198/// an successor block, it sets TBB to be the branch destination block and a 199/// list of operands that evaluate the condition. These 200/// operands can be passed to other TargetInstrInfo methods to create new 201/// branches. 202/// 4. If this block ends with an conditional branch and an unconditional 203/// block, it returns the 'true' destination in TBB, the 'false' destination 204/// in FBB, and a list of operands that evaluate the condition. These 205/// operands can be passed to other TargetInstrInfo methods to create new 206/// branches. 207/// 208/// Note that RemoveBranch and InsertBranch must be implemented to support 209/// cases where this method returns success. 210/// 211bool 212XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 213 MachineBasicBlock *&FBB, 214 SmallVectorImpl<MachineOperand> &Cond, 215 bool AllowModify) const { 216 // If the block has no terminators, it just falls into the block after it. 217 MachineBasicBlock::iterator I = MBB.end(); 218 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) 219 return false; 220 221 // Get the last instruction in the block. 222 MachineInstr *LastInst = I; 223 224 // If there is only one terminator instruction, process it. 225 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 226 if (IsBRU(LastInst->getOpcode())) { 227 TBB = LastInst->getOperand(0).getMBB(); 228 return false; 229 } 230 231 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 232 if (BranchCode == XCore::COND_INVALID) 233 return true; // Can't handle indirect branch. 234 235 // Conditional branch 236 // Block ends with fall-through condbranch. 237 238 TBB = LastInst->getOperand(1).getMBB(); 239 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 240 Cond.push_back(LastInst->getOperand(0)); 241 return false; 242 } 243 244 // Get the instruction before it if it's a terminator. 245 MachineInstr *SecondLastInst = I; 246 247 // If there are three terminators, we don't know what sort of block this is. 248 if (SecondLastInst && I != MBB.begin() && 249 isUnpredicatedTerminator(--I)) 250 return true; 251 252 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 253 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); 254 255 // If the block ends with conditional branch followed by unconditional, 256 // handle it. 257 if (BranchCode != XCore::COND_INVALID 258 && IsBRU(LastInst->getOpcode())) { 259 260 TBB = SecondLastInst->getOperand(1).getMBB(); 261 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 262 Cond.push_back(SecondLastInst->getOperand(0)); 263 264 FBB = LastInst->getOperand(0).getMBB(); 265 return false; 266 } 267 268 // If the block ends with two unconditional branches, handle it. The second 269 // one is not executed, so remove it. 270 if (IsBRU(SecondLastInst->getOpcode()) && 271 IsBRU(LastInst->getOpcode())) { 272 TBB = SecondLastInst->getOperand(0).getMBB(); 273 I = LastInst; 274 if (AllowModify) 275 I->eraseFromParent(); 276 return false; 277 } 278 279 // Likewise if it ends with a branch table followed by an unconditional branch. 280 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { 281 I = LastInst; 282 if (AllowModify) 283 I->eraseFromParent(); 284 return true; 285 } 286 287 // Otherwise, can't handle this. 288 return true; 289} 290 291unsigned 292XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 293 MachineBasicBlock *FBB, 294 const SmallVectorImpl<MachineOperand> &Cond)const{ 295 // FIXME there should probably be a DebugLoc argument here 296 DebugLoc dl = DebugLoc::getUnknownLoc(); 297 // Shouldn't be a fall through. 298 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 299 assert((Cond.size() == 2 || Cond.size() == 0) && 300 "Unexpected number of components!"); 301 302 if (FBB == 0) { // One way branch. 303 if (Cond.empty()) { 304 // Unconditional branch 305 BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(TBB); 306 } else { 307 // Conditional branch. 308 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 309 BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) 310 .addMBB(TBB); 311 } 312 return 1; 313 } 314 315 // Two-way Conditional branch. 316 assert(Cond.size() == 2 && "Unexpected number of components!"); 317 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 318 BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) 319 .addMBB(TBB); 320 BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(FBB); 321 return 2; 322} 323 324unsigned 325XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 326 MachineBasicBlock::iterator I = MBB.end(); 327 if (I == MBB.begin()) return 0; 328 --I; 329 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode())) 330 return 0; 331 332 // Remove the branch. 333 I->eraseFromParent(); 334 335 I = MBB.end(); 336 337 if (I == MBB.begin()) return 1; 338 --I; 339 if (!IsCondBranch(I->getOpcode())) 340 return 1; 341 342 // Remove the branch. 343 I->eraseFromParent(); 344 return 2; 345} 346 347bool XCoreInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 348 MachineBasicBlock::iterator I, 349 unsigned DestReg, unsigned SrcReg, 350 const TargetRegisterClass *DestRC, 351 const TargetRegisterClass *SrcRC) const { 352 DebugLoc DL = DebugLoc::getUnknownLoc(); 353 if (I != MBB.end()) DL = I->getDebugLoc(); 354 355 if (DestRC == SrcRC) { 356 if (DestRC == XCore::GRRegsRegisterClass) { 357 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) 358 .addReg(SrcReg) 359 .addImm(0); 360 return true; 361 } else { 362 return false; 363 } 364 } 365 366 if (SrcRC == XCore::RRegsRegisterClass && SrcReg == XCore::SP && 367 DestRC == XCore::GRRegsRegisterClass) { 368 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg) 369 .addImm(0); 370 return true; 371 } 372 if (DestRC == XCore::RRegsRegisterClass && DestReg == XCore::SP && 373 SrcRC == XCore::GRRegsRegisterClass) { 374 BuildMI(MBB, I, DL, get(XCore::SETSP_1r)) 375 .addReg(SrcReg); 376 return true; 377 } 378 return false; 379} 380 381void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 382 MachineBasicBlock::iterator I, 383 unsigned SrcReg, bool isKill, 384 int FrameIndex, 385 const TargetRegisterClass *RC) const 386{ 387 DebugLoc DL = DebugLoc::getUnknownLoc(); 388 if (I != MBB.end()) DL = I->getDebugLoc(); 389 BuildMI(MBB, I, DL, get(XCore::STWFI)) 390 .addReg(SrcReg, getKillRegState(isKill)) 391 .addFrameIndex(FrameIndex) 392 .addImm(0); 393} 394 395void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 396 MachineBasicBlock::iterator I, 397 unsigned DestReg, int FrameIndex, 398 const TargetRegisterClass *RC) const 399{ 400 DebugLoc DL = DebugLoc::getUnknownLoc(); 401 if (I != MBB.end()) DL = I->getDebugLoc(); 402 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) 403 .addFrameIndex(FrameIndex) 404 .addImm(0); 405} 406 407bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 408 MachineBasicBlock::iterator MI, 409 const std::vector<CalleeSavedInfo> &CSI) const 410{ 411 if (CSI.empty()) { 412 return true; 413 } 414 MachineFunction *MF = MBB.getParent(); 415 const MachineFrameInfo *MFI = MF->getFrameInfo(); 416 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 417 XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>(); 418 419 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); 420 421 DebugLoc DL = DebugLoc::getUnknownLoc(); 422 if (MI != MBB.end()) DL = MI->getDebugLoc(); 423 424 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin(); 425 it != CSI.end(); ++it) { 426 // Add the callee-saved register as live-in. It's killed at the spill. 427 MBB.addLiveIn(it->getReg()); 428 429 storeRegToStackSlot(MBB, MI, it->getReg(), true, 430 it->getFrameIdx(), it->getRegClass()); 431 if (emitFrameMoves) { 432 unsigned SaveLabelId = MMI->NextLabelID(); 433 BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)) 434 .addSym(MMI->getLabelSym(SaveLabelId)); 435 XFI->getSpillLabels().push_back( 436 std::pair<unsigned, CalleeSavedInfo>(SaveLabelId, *it)); 437 } 438 } 439 return true; 440} 441 442bool XCoreInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 443 MachineBasicBlock::iterator MI, 444 const std::vector<CalleeSavedInfo> &CSI) const 445{ 446 bool AtStart = MI == MBB.begin(); 447 MachineBasicBlock::iterator BeforeI = MI; 448 if (!AtStart) 449 --BeforeI; 450 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin(); 451 it != CSI.end(); ++it) { 452 453 loadRegFromStackSlot(MBB, MI, it->getReg(), 454 it->getFrameIdx(), 455 it->getRegClass()); 456 assert(MI != MBB.begin() && 457 "loadRegFromStackSlot didn't insert any code!"); 458 // Insert in reverse order. loadRegFromStackSlot can insert multiple 459 // instructions. 460 if (AtStart) 461 MI = MBB.begin(); 462 else { 463 MI = BeforeI; 464 ++MI; 465 } 466 } 467 return true; 468} 469 470/// ReverseBranchCondition - Return the inverse opcode of the 471/// specified Branch instruction. 472bool XCoreInstrInfo:: 473ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 474{ 475 assert((Cond.size() == 2) && 476 "Invalid XCore branch condition!"); 477 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); 478 return false; 479} 480