X86RecognizableInstr.h revision 4da632e6e09b96db4b3f9202cde4e6ca732001c1 
1//===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the interface of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef X86RECOGNIZABLEINSTR_H
18#define X86RECOGNIZABLEINSTR_H
19
20#include "X86DisassemblerTables.h"
21
22#include "CodeGenTarget.h"
23#include "Record.h"
24
25#include "llvm/Support/DataTypes.h"
26#include "llvm/ADT/SmallVector.h"
27
28namespace llvm {
29
30namespace X86Disassembler {
31
32/// RecognizableInstr - Encapsulates all information required to decode a single
33///   instruction, as extracted from the LLVM instruction tables.  Has methods
34///   to interpret the information available in the LLVM tables, and to emit the
35///   instruction into DisassemblerTables.
36class RecognizableInstr {
37private:
38  /// The opcode of the instruction, as used in an MCInst
39  InstrUID UID;
40  /// The record from the .td files corresponding to this instruction
41  const Record* Rec;
42  /// The prefix field from the record
43  uint8_t Prefix;
44  /// The opcode field from the record; this is the opcode used in the Intel
45  /// encoding and therefore distinct from the UID
46  uint8_t Opcode;
47  /// The form field from the record
48  uint8_t Form;
49  /// The segment override field from the record
50  uint8_t SegOvr;
51  /// The hasOpSizePrefix field from the record
52  bool HasOpSizePrefix;
53  /// The hasREX_WPrefix field from the record
54  bool HasREX_WPrefix;
55  /// The hasVEXPrefix field from the record
56  bool HasVEXPrefix;
57  /// The hasVEX_4VPrefix field from the record
58  bool HasVEX_4VPrefix;
59  /// The hasVEX_WPrefix field from the record
60  bool HasVEX_WPrefix;
61  /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
62  bool HasVEX_LPrefix;
63  /// The hasLockPrefix field from the record
64  bool HasLockPrefix;
65  /// The isCodeGenOnly filed from the record
66  bool IsCodeGenOnly;
67  // Whether the instruction has the predicate "In64BitMode"
68  bool Is64Bit;
69  // Whether the instruction has the predicate "In32BitMode"
70  bool Is32Bit;
71
72  /// The instruction name as listed in the tables
73  std::string Name;
74  /// The AT&T AsmString for the instruction
75  std::string AsmString;
76
77  /// Indicates whether the instruction is SSE
78  bool IsSSE;
79  /// Indicates whether the instruction has FR operands - MOVs with FR operands
80  /// are typically ignored
81  bool HasFROperands;
82  /// Indicates whether the instruction should be emitted into the decode
83  /// tables; regardless, it will be emitted into the instruction info table
84  bool ShouldBeEmitted;
85
86  /// The operands of the instruction, as listed in the CodeGenInstruction.
87  /// They are not one-to-one with operands listed in the MCInst; for example,
88  /// memory operands expand to 5 operands in the MCInst
89  const std::vector<CGIOperandList::OperandInfo>* Operands;
90
91  /// The description of the instruction that is emitted into the instruction
92  /// info table
93  InstructionSpecifier* Spec;
94
95  /// insnContext - Returns the primary context in which the instruction is
96  ///   valid.
97  ///
98  /// @return - The context in which the instruction is valid.
99  InstructionContext insnContext() const;
100
101  enum filter_ret {
102    FILTER_STRONG,    // instruction has no place in the instruction tables
103    FILTER_WEAK,      // instruction may conflict, and should be eliminated if
104                      // it does
105    FILTER_NORMAL     // instruction should have high priority and generate an
106                      // error if it conflcits with any other FILTER_NORMAL
107                      // instruction
108  };
109
110  /// filter - Determines whether the instruction should be decodable.  Some
111  ///   instructions are pure intrinsics and use unencodable operands; many
112  ///   synthetic instructions are duplicates of other instructions; other
113  ///   instructions only differ in the logical way in which they are used, and
114  ///   have the same decoding.  Because these would cause decode conflicts,
115  ///   they must be filtered out.
116  ///
117  /// @return - The degree of filtering to be applied (see filter_ret).
118  filter_ret filter() const;
119
120  /// hasFROperands - Returns true if any operand is a FR operand.
121  bool hasFROperands() const;
122
123  /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand.
124  bool has256BitOperands() const;
125
126  /// typeFromString - Translates an operand type from the string provided in
127  ///   the LLVM tables to an OperandType for use in the operand specifier.
128  ///
129  /// @param s              - The string, as extracted by calling Rec->getName()
130  ///                         on a CodeGenInstruction::OperandInfo.
131  /// @param isSSE          - Indicates whether the instruction is an SSE
132  ///                         instruction.  For SSE instructions, immediates are
133  ///                         fixed-size rather than being affected by the
134  ///                         mandatory OpSize prefix.
135  /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
136  ///                         prefix.  If it does, 32-bit register operands stay
137  ///                         32-bit regardless of the operand size.
138  /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize
139  ///                         prefix.  If it does not, then 16-bit register
140  ///                         operands stay 16-bit.
141  /// @return               - The operand's type.
142  static OperandType typeFromString(const std::string& s,
143                                    bool isSSE,
144                                    bool hasREX_WPrefix,
145                                    bool hasOpSizePrefix);
146
147  /// immediateEncodingFromString - Translates an immediate encoding from the
148  ///   string provided in the LLVM tables to an OperandEncoding for use in
149  ///   the operand specifier.
150  ///
151  /// @param s                - See typeFromString().
152  /// @param hasOpSizePrefix  - Indicates whether the instruction has an OpSize
153  ///                           prefix.  If it does not, then 16-bit immediate
154  ///                           operands stay 16-bit.
155  /// @return                 - The operand's encoding.
156  static OperandEncoding immediateEncodingFromString(const std::string &s,
157                                                     bool hasOpSizePrefix);
158
159  /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
160  ///   handles operands that are in the REG field of the ModR/M byte.
161  static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
162                                                      bool hasOpSizePrefix);
163
164  /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
165  ///   handles operands that are in the REG field of the ModR/M byte.
166  static OperandEncoding roRegisterEncodingFromString(const std::string &s,
167                                                      bool hasOpSizePrefix);
168  static OperandEncoding memoryEncodingFromString(const std::string &s,
169                                                  bool hasOpSizePrefix);
170  static OperandEncoding relocationEncodingFromString(const std::string &s,
171                                                      bool hasOpSizePrefix);
172  static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
173                                                          bool hasOpSizePrefix);
174  static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
175                                                        bool HasOpSizePrefix);
176
177  /// handleOperand - Converts a single operand from the LLVM table format to
178  ///   the emitted table format, handling any duplicate operands it encounters
179  ///   and then one non-duplicate.
180  ///
181  /// @param optional             - Determines whether to assert that the
182  ///                               operand exists.
183  /// @param operandIndex         - The index into the generated operand table.
184  ///                               Incremented by this function one or more
185  ///                               times to reflect possible duplicate
186  ///                               operands).
187  /// @param physicalOperandIndex - The index of the current operand into the
188  ///                               set of non-duplicate ('physical') operands.
189  ///                               Incremented by this function once.
190  /// @param numPhysicalOperands  - The number of non-duplicate operands in the
191  ///                               instructions.
192  /// @param operandMapping       - The operand mapping, which has an entry for
193  ///                               each operand that indicates whether it is a
194  ///                               duplicate, and of what.
195  void handleOperand(bool optional,
196                     unsigned &operandIndex,
197                     unsigned &physicalOperandIndex,
198                     unsigned &numPhysicalOperands,
199                     unsigned *operandMapping,
200                     OperandEncoding (*encodingFromString)
201                       (const std::string&,
202                        bool hasOpSizePrefix));
203
204  /// shouldBeEmitted - Returns the shouldBeEmitted field.  Although filter()
205  ///   filters out many instructions, at various points in decoding we
206  ///   determine that the instruction should not actually be decodable.  In
207  ///   particular, MMX MOV instructions aren't emitted, but they're only
208  ///   identified during operand parsing.
209  ///
210  /// @return - true if at this point we believe the instruction should be
211  ///   emitted; false if not.  This will return false if filter() returns false
212  ///   once emitInstructionSpecifier() has been called.
213  bool shouldBeEmitted() const {
214    return ShouldBeEmitted;
215  }
216
217  /// emitInstructionSpecifier - Loads the instruction specifier for the current
218  ///   instruction into a DisassemblerTables.
219  ///
220  /// @arg tables - The DisassemblerTables to populate with the specifier for
221  ///               the current instruction.
222  void emitInstructionSpecifier(DisassemblerTables &tables);
223
224  /// emitDecodePath - Populates the proper fields in the decode tables
225  ///   corresponding to the decode paths for this instruction.
226  ///
227  /// @arg tables - The DisassemblerTables to populate with the decode
228  ///               decode information for the current instruction.
229  void emitDecodePath(DisassemblerTables &tables) const;
230
231  /// Constructor - Initializes a RecognizableInstr with the appropriate fields
232  ///   from a CodeGenInstruction.
233  ///
234  /// @arg tables - The DisassemblerTables that the specifier will be added to.
235  /// @arg insn   - The CodeGenInstruction to extract information from.
236  /// @arg uid    - The unique ID of the current instruction.
237  RecognizableInstr(DisassemblerTables &tables,
238                    const CodeGenInstruction &insn,
239                    InstrUID uid);
240public:
241  /// processInstr - Accepts a CodeGenInstruction and loads decode information
242  ///   for it into a DisassemblerTables if appropriate.
243  ///
244  /// @arg tables - The DiassemblerTables to be populated with decode
245  ///               information.
246  /// @arg insn   - The CodeGenInstruction to be used as a source for this
247  ///               information.
248  /// @uid        - The unique ID of the instruction.
249  static void processInstr(DisassemblerTables &tables,
250                           const CodeGenInstruction &insn,
251                           InstrUID uid);
252};
253
254} // namespace X86Disassembler
255
256} // namespace llvm
257
258#endif
259