X86RecognizableInstr.h revision 7105259ce8e9fd78ce9fc1b7a9aaab123fb5db64
1//===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file is part of the X86 Disassembler Emitter. 11// It contains the interface of a single recognizable instruction. 12// Documentation for the disassembler emitter in general can be found in 13// X86DisasemblerEmitter.h. 14// 15//===----------------------------------------------------------------------===// 16 17#ifndef X86RECOGNIZABLEINSTR_H 18#define X86RECOGNIZABLEINSTR_H 19 20#include "X86DisassemblerTables.h" 21 22#include "CodeGenTarget.h" 23#include "Record.h" 24 25#include "llvm/Support/DataTypes.h" 26#include "llvm/ADT/SmallVector.h" 27 28namespace llvm { 29 30namespace X86Disassembler { 31 32/// RecognizableInstr - Encapsulates all information required to decode a single 33/// instruction, as extracted from the LLVM instruction tables. Has methods 34/// to interpret the information available in the LLVM tables, and to emit the 35/// instruction into DisassemblerTables. 36class RecognizableInstr { 37private: 38 /// The opcode of the instruction, as used in an MCInst 39 InstrUID UID; 40 /// The record from the .td files corresponding to this instruction 41 const Record* Rec; 42 /// The prefix field from the record 43 uint8_t Prefix; 44 /// The opcode field from the record; this is the opcode used in the Intel 45 /// encoding and therefore distinct from the UID 46 uint8_t Opcode; 47 /// The form field from the record 48 uint8_t Form; 49 /// The segment override field from the record 50 uint8_t SegOvr; 51 /// The hasOpSizePrefix field from the record 52 bool HasOpSizePrefix; 53 /// The hasREX_WPrefix field from the record 54 bool HasREX_WPrefix; 55 /// The hasVEXPrefix field from the record 56 bool HasVEXPrefix; 57 /// The hasVEX_4VPrefix field from the record 58 bool HasVEX_4VPrefix; 59 /// The hasVEX_WPrefix field from the record 60 bool HasVEX_WPrefix; 61 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set 62 bool HasVEX_LPrefix; 63 /// The hasLockPrefix field from the record 64 bool HasLockPrefix; 65 /// The isCodeGenOnly filed from the record 66 bool IsCodeGenOnly; 67 // Whether the instruction has the predicate "Mode64Bit" 68 bool Is64Bit; 69 70 /// The instruction name as listed in the tables 71 std::string Name; 72 /// The AT&T AsmString for the instruction 73 std::string AsmString; 74 75 /// Indicates whether the instruction is SSE 76 bool IsSSE; 77 /// Indicates whether the instruction has FR operands - MOVs with FR operands 78 /// are typically ignored 79 bool HasFROperands; 80 /// Indicates whether the instruction should be emitted into the decode 81 /// tables; regardless, it will be emitted into the instruction info table 82 bool ShouldBeEmitted; 83 84 /// The operands of the instruction, as listed in the CodeGenInstruction. 85 /// They are not one-to-one with operands listed in the MCInst; for example, 86 /// memory operands expand to 5 operands in the MCInst 87 const std::vector<CGIOperandList::OperandInfo>* Operands; 88 89 /// The description of the instruction that is emitted into the instruction 90 /// info table 91 InstructionSpecifier* Spec; 92 93 /// insnContext - Returns the primary context in which the instruction is 94 /// valid. 95 /// 96 /// @return - The context in which the instruction is valid. 97 InstructionContext insnContext() const; 98 99 enum filter_ret { 100 FILTER_STRONG, // instruction has no place in the instruction tables 101 FILTER_WEAK, // instruction may conflict, and should be eliminated if 102 // it does 103 FILTER_NORMAL // instruction should have high priority and generate an 104 // error if it conflcits with any other FILTER_NORMAL 105 // instruction 106 }; 107 108 /// filter - Determines whether the instruction should be decodable. Some 109 /// instructions are pure intrinsics and use unencodable operands; many 110 /// synthetic instructions are duplicates of other instructions; other 111 /// instructions only differ in the logical way in which they are used, and 112 /// have the same decoding. Because these would cause decode conflicts, 113 /// they must be filtered out. 114 /// 115 /// @return - The degree of filtering to be applied (see filter_ret). 116 filter_ret filter() const; 117 118 /// hasFROperands - Returns true if any operand is a FR operand. 119 bool hasFROperands() const; 120 121 /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand. 122 bool has256BitOperands() const; 123 124 /// typeFromString - Translates an operand type from the string provided in 125 /// the LLVM tables to an OperandType for use in the operand specifier. 126 /// 127 /// @param s - The string, as extracted by calling Rec->getName() 128 /// on a CodeGenInstruction::OperandInfo. 129 /// @param isSSE - Indicates whether the instruction is an SSE 130 /// instruction. For SSE instructions, immediates are 131 /// fixed-size rather than being affected by the 132 /// mandatory OpSize prefix. 133 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W 134 /// prefix. If it does, 32-bit register operands stay 135 /// 32-bit regardless of the operand size. 136 /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize 137 /// prefix. If it does not, then 16-bit register 138 /// operands stay 16-bit. 139 /// @return - The operand's type. 140 static OperandType typeFromString(const std::string& s, 141 bool isSSE, 142 bool hasREX_WPrefix, 143 bool hasOpSizePrefix); 144 145 /// immediateEncodingFromString - Translates an immediate encoding from the 146 /// string provided in the LLVM tables to an OperandEncoding for use in 147 /// the operand specifier. 148 /// 149 /// @param s - See typeFromString(). 150 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize 151 /// prefix. If it does not, then 16-bit immediate 152 /// operands stay 16-bit. 153 /// @return - The operand's encoding. 154 static OperandEncoding immediateEncodingFromString(const std::string &s, 155 bool hasOpSizePrefix); 156 157 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 158 /// handles operands that are in the REG field of the ModR/M byte. 159 static OperandEncoding rmRegisterEncodingFromString(const std::string &s, 160 bool hasOpSizePrefix); 161 162 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 163 /// handles operands that are in the REG field of the ModR/M byte. 164 static OperandEncoding roRegisterEncodingFromString(const std::string &s, 165 bool hasOpSizePrefix); 166 static OperandEncoding memoryEncodingFromString(const std::string &s, 167 bool hasOpSizePrefix); 168 static OperandEncoding relocationEncodingFromString(const std::string &s, 169 bool hasOpSizePrefix); 170 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, 171 bool hasOpSizePrefix); 172 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, 173 bool HasOpSizePrefix); 174 175 /// handleOperand - Converts a single operand from the LLVM table format to 176 /// the emitted table format, handling any duplicate operands it encounters 177 /// and then one non-duplicate. 178 /// 179 /// @param optional - Determines whether to assert that the 180 /// operand exists. 181 /// @param operandIndex - The index into the generated operand table. 182 /// Incremented by this function one or more 183 /// times to reflect possible duplicate 184 /// operands). 185 /// @param physicalOperandIndex - The index of the current operand into the 186 /// set of non-duplicate ('physical') operands. 187 /// Incremented by this function once. 188 /// @param numPhysicalOperands - The number of non-duplicate operands in the 189 /// instructions. 190 /// @param operandMapping - The operand mapping, which has an entry for 191 /// each operand that indicates whether it is a 192 /// duplicate, and of what. 193 void handleOperand(bool optional, 194 unsigned &operandIndex, 195 unsigned &physicalOperandIndex, 196 unsigned &numPhysicalOperands, 197 unsigned *operandMapping, 198 OperandEncoding (*encodingFromString) 199 (const std::string&, 200 bool hasOpSizePrefix)); 201 202 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter() 203 /// filters out many instructions, at various points in decoding we 204 /// determine that the instruction should not actually be decodable. In 205 /// particular, MMX MOV instructions aren't emitted, but they're only 206 /// identified during operand parsing. 207 /// 208 /// @return - true if at this point we believe the instruction should be 209 /// emitted; false if not. This will return false if filter() returns false 210 /// once emitInstructionSpecifier() has been called. 211 bool shouldBeEmitted() const { 212 return ShouldBeEmitted; 213 } 214 215 /// emitInstructionSpecifier - Loads the instruction specifier for the current 216 /// instruction into a DisassemblerTables. 217 /// 218 /// @arg tables - The DisassemblerTables to populate with the specifier for 219 /// the current instruction. 220 void emitInstructionSpecifier(DisassemblerTables &tables); 221 222 /// emitDecodePath - Populates the proper fields in the decode tables 223 /// corresponding to the decode paths for this instruction. 224 /// 225 /// @arg tables - The DisassemblerTables to populate with the decode 226 /// decode information for the current instruction. 227 void emitDecodePath(DisassemblerTables &tables) const; 228 229 /// Constructor - Initializes a RecognizableInstr with the appropriate fields 230 /// from a CodeGenInstruction. 231 /// 232 /// @arg tables - The DisassemblerTables that the specifier will be added to. 233 /// @arg insn - The CodeGenInstruction to extract information from. 234 /// @arg uid - The unique ID of the current instruction. 235 RecognizableInstr(DisassemblerTables &tables, 236 const CodeGenInstruction &insn, 237 InstrUID uid); 238public: 239 /// processInstr - Accepts a CodeGenInstruction and loads decode information 240 /// for it into a DisassemblerTables if appropriate. 241 /// 242 /// @arg tables - The DiassemblerTables to be populated with decode 243 /// information. 244 /// @arg insn - The CodeGenInstruction to be used as a source for this 245 /// information. 246 /// @uid - The unique ID of the instruction. 247 static void processInstr(DisassemblerTables &tables, 248 const CodeGenInstruction &insn, 249 InstrUID uid); 250}; 251 252} // namespace X86Disassembler 253 254} // namespace llvm 255 256#endif 257