cpu.h revision c7389bd69e570a2c8432b37399aff1976b021f0f
186797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* 286797937017f52bff088d02edf64fb931177a7eaJun Nakajima * i386 virtual CPU header 386797937017f52bff088d02edf64fb931177a7eaJun Nakajima * 486797937017f52bff088d02edf64fb931177a7eaJun Nakajima * Copyright (c) 2003 Fabrice Bellard 586797937017f52bff088d02edf64fb931177a7eaJun Nakajima * 686797937017f52bff088d02edf64fb931177a7eaJun Nakajima * This library is free software; you can redistribute it and/or 786797937017f52bff088d02edf64fb931177a7eaJun Nakajima * modify it under the terms of the GNU Lesser General Public 886797937017f52bff088d02edf64fb931177a7eaJun Nakajima * License as published by the Free Software Foundation; either 986797937017f52bff088d02edf64fb931177a7eaJun Nakajima * version 2 of the License, or (at your option) any later version. 1086797937017f52bff088d02edf64fb931177a7eaJun Nakajima * 1186797937017f52bff088d02edf64fb931177a7eaJun Nakajima * This library is distributed in the hope that it will be useful, 1286797937017f52bff088d02edf64fb931177a7eaJun Nakajima * but WITHOUT ANY WARRANTY; without even the implied warranty of 1386797937017f52bff088d02edf64fb931177a7eaJun Nakajima * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1486797937017f52bff088d02edf64fb931177a7eaJun Nakajima * Lesser General Public License for more details. 1586797937017f52bff088d02edf64fb931177a7eaJun Nakajima * 1686797937017f52bff088d02edf64fb931177a7eaJun Nakajima * You should have received a copy of the GNU Lesser General Public 1786797937017f52bff088d02edf64fb931177a7eaJun Nakajima * License along with this library; if not, write to the Free Software 1886797937017f52bff088d02edf64fb931177a7eaJun Nakajima * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA 1986797937017f52bff088d02edf64fb931177a7eaJun Nakajima */ 2086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifndef CPU_I386_H 2186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPU_I386_H 2286797937017f52bff088d02edf64fb931177a7eaJun Nakajima 2386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#include "config.h" 2486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 2586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifdef TARGET_X86_64 2686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define TARGET_LONG_BITS 64 2786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#else 2886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define TARGET_LONG_BITS 32 2986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 3086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 3186797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* target supports implicit self modifying code */ 3286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define TARGET_HAS_SMC 3386797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* support for self modifying code even if the modified instruction is 3486797937017f52bff088d02edf64fb931177a7eaJun Nakajima close to the modifying instruction */ 3586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define TARGET_HAS_PRECISE_SMC 3686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 3786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define TARGET_HAS_ICE 1 3886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 3986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifdef TARGET_X86_64 4086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define ELF_MACHINE EM_X86_64 4186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#else 4286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define ELF_MACHINE EM_386 4386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 4486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 4586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUState struct CPUX86State 4686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 4786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#include "cpu-defs.h" 4886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 4986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#include "softfloat.h" 5086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 5186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_EAX 0 5286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_ECX 1 5386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_EDX 2 5486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_EBX 3 5586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_ESP 4 5686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_EBP 5 5786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_ESI 6 5886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_EDI 7 5986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 6086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_AL 0 6186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_CL 1 6286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_DL 2 6386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_BL 3 6486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_AH 4 6586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_CH 5 6686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_DH 6 6786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_BH 7 6886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 6986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_ES 0 7086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_CS 1 7186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_SS 2 7286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_DS 3 7386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_FS 4 7486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define R_GS 5 7586797937017f52bff088d02edf64fb931177a7eaJun Nakajima 7686797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* segment descriptor fields */ 7786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_G_MASK (1 << 23) 7886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_B_SHIFT 22 7986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_B_MASK (1 << DESC_B_SHIFT) 8086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ 8186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_L_MASK (1 << DESC_L_SHIFT) 8286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_AVL_MASK (1 << 20) 8386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_P_MASK (1 << 15) 8486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_DPL_SHIFT 13 8586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) 8686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_S_MASK (1 << 12) 8786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_TYPE_SHIFT 8 8886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) 8986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_A_MASK (1 << 8) 9086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 9186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ 9286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_C_MASK (1 << 10) /* code: conforming */ 9386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_R_MASK (1 << 9) /* code: readable */ 9486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 9586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_E_MASK (1 << 10) /* data: expansion direction */ 9686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_W_MASK (1 << 9) /* data: writable */ 9786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 9886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DESC_TSS_BUSY_MASK (1 << 9) 9986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 10086797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* eflags masks */ 10186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CC_C 0x0001 10286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CC_P 0x0004 10386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CC_A 0x0010 10486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CC_Z 0x0040 10586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CC_S 0x0080 10686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CC_O 0x0800 10786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 10886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define TF_SHIFT 8 10986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define IOPL_SHIFT 12 11086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define VM_SHIFT 17 11186797937017f52bff088d02edf64fb931177a7eaJun Nakajima 11286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define TF_MASK 0x00000100 11386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define IF_MASK 0x00000200 11486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DF_MASK 0x00000400 11586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define IOPL_MASK 0x00003000 11686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define NT_MASK 0x00004000 11786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define RF_MASK 0x00010000 11886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define VM_MASK 0x00020000 11986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define AC_MASK 0x00040000 12086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define VIF_MASK 0x00080000 12186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define VIP_MASK 0x00100000 12286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define ID_MASK 0x00200000 12386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 12486797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* hidden flags - used internally by qemu to represent additional cpu 12586797937017f52bff088d02edf64fb931177a7eaJun Nakajima states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not 12686797937017f52bff088d02edf64fb931177a7eaJun Nakajima redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit 12786797937017f52bff088d02edf64fb931177a7eaJun Nakajima position to ease oring with eflags. */ 12886797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* current cpl */ 12986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_CPL_SHIFT 0 13086797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* true if soft mmu is being used */ 13186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_SOFTMMU_SHIFT 2 13286797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* true if hardware interrupts must be disabled for next instruction */ 13386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_INHIBIT_IRQ_SHIFT 3 13486797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* 16 or 32 segments */ 13586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_CS32_SHIFT 4 13686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_SS32_SHIFT 5 13786797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ 13886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_ADDSEG_SHIFT 6 13986797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* copy of CR0.PE (protected mode) */ 14086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_PE_SHIFT 7 14186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_TF_SHIFT 8 /* must be same as eflags */ 14286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ 14386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_EM_SHIFT 10 14486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_TS_SHIFT 11 14586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_IOPL_SHIFT 12 /* must be same as eflags */ 14686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ 14786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ 14886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_RF_SHIFT 16 /* must be same as eflags */ 14986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_VM_SHIFT 17 /* must be same as eflags */ 15086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_SMM_SHIFT 19 /* CPU in SMM mode */ 15186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ 15286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ 15386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ 15486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 15586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_CPL_MASK (3 << HF_CPL_SHIFT) 15686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) 15786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) 15886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_CS32_MASK (1 << HF_CS32_SHIFT) 15986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_SS32_MASK (1 << HF_SS32_SHIFT) 16086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) 16186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_PE_MASK (1 << HF_PE_SHIFT) 16286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_TF_MASK (1 << HF_TF_SHIFT) 16386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_MP_MASK (1 << HF_MP_SHIFT) 16486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_EM_MASK (1 << HF_EM_SHIFT) 16586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_TS_MASK (1 << HF_TS_SHIFT) 16686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) 16786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_LMA_MASK (1 << HF_LMA_SHIFT) 16886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_CS64_MASK (1 << HF_CS64_SHIFT) 16986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_RF_MASK (1 << HF_RF_SHIFT) 17086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_VM_MASK (1 << HF_VM_SHIFT) 17186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_SMM_MASK (1 << HF_SMM_SHIFT) 17286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_SVME_MASK (1 << HF_SVME_SHIFT) 17386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) 17486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) 17586797937017f52bff088d02edf64fb931177a7eaJun Nakajima 17686797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* hflags2 */ 17786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 17886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ 17986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ 18086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF2_NMI_SHIFT 2 /* CPU serving NMI */ 18186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ 18286797937017f52bff088d02edf64fb931177a7eaJun Nakajima 18386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) 184462564f31bbdc9939bf1d2376e2782defa7ef655David 'Digit' Turner#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) 18586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) 18686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) 18786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 18886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR0_PE_SHIFT 0 18986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR0_MP_SHIFT 1 19086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 19186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR0_PE_MASK (1 << 0) 19286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR0_MP_MASK (1 << 1) 19386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR0_EM_MASK (1 << 2) 19486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR0_TS_MASK (1 << 3) 19586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR0_ET_MASK (1 << 4) 19686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR0_NE_MASK (1 << 5) 19786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR0_WP_MASK (1 << 16) 19886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR0_AM_MASK (1 << 18) 19986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR0_PG_MASK (1 << 31) 20086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 20186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_VME_MASK (1 << 0) 20286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_PVI_MASK (1 << 1) 20386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_TSD_MASK (1 << 2) 20486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_DE_MASK (1 << 3) 20586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_PSE_MASK (1 << 4) 20686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_PAE_MASK (1 << 5) 20786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_MCE_MASK (1 << 6) 20886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_PGE_MASK (1 << 7) 20986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_PCE_MASK (1 << 8) 21086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_OSFXSR_SHIFT 9 21186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) 21286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CR4_OSXMMEXCPT_MASK (1 << 10) 21386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 21486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DR6_BD (1 << 13) 21586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DR6_BS (1 << 14) 21686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DR6_BT (1 << 15) 21786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DR6_FIXED_1 0xffff0ff0 21886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 21986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DR7_GD (1 << 13) 22086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DR7_TYPE_SHIFT 16 22186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DR7_LEN_SHIFT 18 22286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define DR7_FIXED_1 0x00000400 22386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 22486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_PRESENT_BIT 0 22586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_RW_BIT 1 22686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_USER_BIT 2 22786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_PWT_BIT 3 22886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_PCD_BIT 4 22986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_ACCESSED_BIT 5 23086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_DIRTY_BIT 6 23186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_PSE_BIT 7 23286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_GLOBAL_BIT 8 23386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_NX_BIT 63 23486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 23586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) 23686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_RW_MASK (1 << PG_RW_BIT) 23786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_USER_MASK (1 << PG_USER_BIT) 23886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_PWT_MASK (1 << PG_PWT_BIT) 23986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_PCD_MASK (1 << PG_PCD_BIT) 24086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 24186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) 24286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_PSE_MASK (1 << PG_PSE_BIT) 24386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) 24486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_NX_MASK (1LL << PG_NX_BIT) 24586797937017f52bff088d02edf64fb931177a7eaJun Nakajima 24686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_ERROR_W_BIT 1 24786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 24886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_ERROR_P_MASK 0x01 24986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) 25086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_ERROR_U_MASK 0x04 25186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_ERROR_RSVD_MASK 0x08 25286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define PG_ERROR_I_D_MASK 0x10 25386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 25486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */ 25586797937017f52bff088d02edf64fb931177a7eaJun Nakajima 25686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MCE_CAP_DEF MCG_CTL_P 25786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MCE_BANKS_DEF 10 25886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 25986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MCG_STATUS_MCIP (1UL<<2) /* machine check in progress */ 26086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 261c7389bd69e570a2c8432b37399aff1976b021f0fAndrew Hsieh#define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 262c7389bd69e570a2c8432b37399aff1976b021f0fAndrew Hsieh#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 263c7389bd69e570a2c8432b37399aff1976b021f0fAndrew Hsieh#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 26486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 26586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_IA32_TSC 0x10 26686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_IA32_APICBASE 0x1b 26786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_IA32_APICBASE_BSP (1<<8) 26886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_IA32_APICBASE_ENABLE (1<<11) 26986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 27086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 27186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRcap 0xfe 27286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRcap_VCNT 8 27386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) 27486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRcap_WC_SUPPORTED (1 << 10) 27586797937017f52bff088d02edf64fb931177a7eaJun Nakajima 27686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_IA32_SYSENTER_CS 0x174 27786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_IA32_SYSENTER_ESP 0x175 27886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_IA32_SYSENTER_EIP 0x176 27986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 28086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MCG_CAP 0x179 28186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MCG_STATUS 0x17a 28286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MCG_CTL 0x17b 28386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 28486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_IA32_PERF_STATUS 0x198 28586797937017f52bff088d02edf64fb931177a7eaJun Nakajima 28686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) 28786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) 28886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 28986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRfix64K_00000 0x250 29086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRfix16K_80000 0x258 29186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRfix16K_A0000 0x259 29286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRfix4K_C0000 0x268 29386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRfix4K_C8000 0x269 29486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRfix4K_D0000 0x26a 29586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRfix4K_D8000 0x26b 29686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRfix4K_E0000 0x26c 29786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRfix4K_E8000 0x26d 29886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRfix4K_F0000 0x26e 29986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRfix4K_F8000 0x26f 30086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 30186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_PAT 0x277 30286797937017f52bff088d02edf64fb931177a7eaJun Nakajima 30386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MTRRdefType 0x2ff 30486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 30586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MC0_CTL 0x400 30686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MC0_STATUS 0x401 30786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MC0_ADDR 0x402 30886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_MC0_MISC 0x403 30986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 31086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_EFER 0xc0000080 31186797937017f52bff088d02edf64fb931177a7eaJun Nakajima 31286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_EFER_SCE (1 << 0) 31386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_EFER_LME (1 << 8) 31486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_EFER_LMA (1 << 10) 31586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_EFER_NXE (1 << 11) 31686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_EFER_SVME (1 << 12) 31786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_EFER_FFXSR (1 << 14) 31886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 31986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_STAR 0xc0000081 32086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_LSTAR 0xc0000082 32186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_CSTAR 0xc0000083 32286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_FMASK 0xc0000084 32386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_FSBASE 0xc0000100 32486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_GSBASE 0xc0000101 32586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_KERNELGSBASE 0xc0000102 32686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 32786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MSR_VM_HSAVE_PA 0xc0010117 32886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 32986797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* cpuid_features bits */ 33086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_FP87 (1 << 0) 33186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_VME (1 << 1) 33286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_DE (1 << 2) 33386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_PSE (1 << 3) 33486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_TSC (1 << 4) 33586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_MSR (1 << 5) 33686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_PAE (1 << 6) 33786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_MCE (1 << 7) 33886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_CX8 (1 << 8) 33986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_APIC (1 << 9) 34086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_SEP (1 << 11) /* sysenter/sysexit */ 34186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_MTRR (1 << 12) 34286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_PGE (1 << 13) 34386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_MCA (1 << 14) 34486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_CMOV (1 << 15) 34586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_PAT (1 << 16) 34686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_PSE36 (1 << 17) 34786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_PN (1 << 18) 34886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_CLFLUSH (1 << 19) 34986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_DTS (1 << 21) 35086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_ACPI (1 << 22) 35186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_MMX (1 << 23) 35286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_FXSR (1 << 24) 35386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_SSE (1 << 25) 35486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_SSE2 (1 << 26) 35586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_SS (1 << 27) 35686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_HT (1 << 28) 35786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_TM (1 << 29) 35886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_IA64 (1 << 30) 35986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_PBE (1 << 31) 36086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 36186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_SSE3 (1 << 0) 36286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_DTES64 (1 << 2) 36386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_MONITOR (1 << 3) 36486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_DSCPL (1 << 4) 36586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_VMX (1 << 5) 36686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_SMX (1 << 6) 36786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_EST (1 << 7) 36886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_TM2 (1 << 8) 36986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_SSSE3 (1 << 9) 37086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_CID (1 << 10) 37186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_CX16 (1 << 13) 37286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_XTPR (1 << 14) 37386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_PDCM (1 << 15) 37486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_DCA (1 << 18) 37586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_SSE41 (1 << 19) 37686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_SSE42 (1 << 20) 37786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_X2APIC (1 << 21) 37886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_MOVBE (1 << 22) 37986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_POPCNT (1 << 23) 38086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_XSAVE (1 << 26) 38186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT_OSXSAVE (1 << 27) 38286797937017f52bff088d02edf64fb931177a7eaJun Nakajima 38386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT2_SYSCALL (1 << 11) 38486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT2_MP (1 << 19) 38586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT2_NX (1 << 20) 38686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT2_MMXEXT (1 << 22) 38786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT2_FFXSR (1 << 25) 38886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT2_PDPE1GB (1 << 26) 38986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT2_RDTSCP (1 << 27) 39086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT2_LM (1 << 29) 39186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT2_3DNOWEXT (1 << 30) 39286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT2_3DNOW (1 << 31) 39386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 39486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_LAHF_LM (1 << 0) 39586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_CMP_LEG (1 << 1) 39686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_SVM (1 << 2) 39786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_EXTAPIC (1 << 3) 39886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_CR8LEG (1 << 4) 39986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_ABM (1 << 5) 40086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_SSE4A (1 << 6) 40186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_MISALIGNSSE (1 << 7) 40286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_3DNOWPREFETCH (1 << 8) 40386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_OSVW (1 << 9) 40486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_IBS (1 << 10) 40586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_EXT3_SKINIT (1 << 12) 40686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 40786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ 40886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ 40986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ 41086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 41186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ 412462564f31bbdc9939bf1d2376e2782defa7ef655David 'Digit' Turner#define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ 41386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ 41486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 41586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ 41686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ 41786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 41886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP00_DIVZ 0 41986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP01_DB 1 42086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP02_NMI 2 42186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP03_INT3 3 42286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP04_INTO 4 42386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP05_BOUND 5 42486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP06_ILLOP 6 42586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP07_PREX 7 42686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP08_DBLE 8 42786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP09_XERR 9 42886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP0A_TSS 10 42986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP0B_NOSEG 11 43086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP0C_STACK 12 43186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP0D_GPF 13 43286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP0E_PAGE 14 43386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP10_COPR 16 43486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP11_ALGN 17 43586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP12_MCHK 18 43686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 43786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define EXCP_SYSCALL 0x100 /* only happens in user only emulation 43886797937017f52bff088d02edf64fb931177a7eaJun Nakajima for syscall instruction */ 43986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 44086797937017f52bff088d02edf64fb931177a7eaJun Nakajimaenum { 44186797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 44286797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ 44386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 44486797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ 44586797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_MULW, 44686797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_MULL, 44786797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_MULQ, 44886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 44986797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 45086797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_ADDW, 45186797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_ADDL, 45286797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_ADDQ, 45386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 45486797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 45586797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_ADCW, 45686797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_ADCL, 45786797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_ADCQ, 45886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 45986797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 46086797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SUBW, 46186797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SUBL, 46286797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SUBQ, 46386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 46486797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 46586797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SBBW, 46686797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SBBL, 46786797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SBBQ, 46886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 46986797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_LOGICB, /* modify all flags, CC_DST = res */ 47086797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_LOGICW, 47186797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_LOGICL, 47286797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_LOGICQ, 47386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 47486797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 47586797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_INCW, 47686797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_INCL, 47786797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_INCQ, 47886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 47986797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ 48086797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_DECW, 48186797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_DECL, 48286797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_DECQ, 48386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 48486797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ 48586797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SHLW, 48686797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SHLL, 48786797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SHLQ, 48886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 48986797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ 49086797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SARW, 49186797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SARL, 49286797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_SARQ, 49386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 49486797937017f52bff088d02edf64fb931177a7eaJun Nakajima CC_OP_NB, 49586797937017f52bff088d02edf64fb931177a7eaJun Nakajima}; 49686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 49786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifdef FLOATX80 49886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define USE_X86LDOUBLE 49986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 50086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 50186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifdef USE_X86LDOUBLE 50286797937017f52bff088d02edf64fb931177a7eaJun Nakajimatypedef floatx80 CPU86_LDouble; 50386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#else 50486797937017f52bff088d02edf64fb931177a7eaJun Nakajimatypedef float64 CPU86_LDouble; 50586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 50686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 50786797937017f52bff088d02edf64fb931177a7eaJun Nakajimatypedef struct SegmentCache { 50886797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t selector; 50986797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong base; 51086797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t limit; 51186797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t flags; 51286797937017f52bff088d02edf64fb931177a7eaJun Nakajima} SegmentCache; 51386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 51486797937017f52bff088d02edf64fb931177a7eaJun Nakajimatypedef union { 51586797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint8_t _b[16]; 51686797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint16_t _w[8]; 51786797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t _l[4]; 51886797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t _q[2]; 51986797937017f52bff088d02edf64fb931177a7eaJun Nakajima float32 _s[4]; 52086797937017f52bff088d02edf64fb931177a7eaJun Nakajima float64 _d[2]; 52186797937017f52bff088d02edf64fb931177a7eaJun Nakajima} XMMReg; 52286797937017f52bff088d02edf64fb931177a7eaJun Nakajima 52386797937017f52bff088d02edf64fb931177a7eaJun Nakajimatypedef union { 52486797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint8_t _b[8]; 52586797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint16_t _w[4]; 52686797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t _l[2]; 52786797937017f52bff088d02edf64fb931177a7eaJun Nakajima float32 _s[2]; 52886797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t q; 52986797937017f52bff088d02edf64fb931177a7eaJun Nakajima} MMXReg; 53086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 53186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifdef WORDS_BIGENDIAN 53286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_B(n) _b[15 - (n)] 53386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_W(n) _w[7 - (n)] 53486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_L(n) _l[3 - (n)] 53586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_S(n) _s[3 - (n)] 53686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_Q(n) _q[1 - (n)] 53786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_D(n) _d[1 - (n)] 53886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 53986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMX_B(n) _b[7 - (n)] 54086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMX_W(n) _w[3 - (n)] 54186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMX_L(n) _l[1 - (n)] 54286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMX_S(n) _s[1 - (n)] 54386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#else 54486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_B(n) _b[n] 54586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_W(n) _w[n] 54686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_L(n) _l[n] 54786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_S(n) _s[n] 54886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_Q(n) _q[n] 54986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define XMM_D(n) _d[n] 55086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 55186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMX_B(n) _b[n] 55286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMX_W(n) _w[n] 55386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMX_L(n) _l[n] 55486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMX_S(n) _s[n] 55586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 55686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMX_Q(n) q 55786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 55886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifdef TARGET_X86_64 55986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPU_NB_REGS 16 56086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#else 56186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPU_NB_REGS 8 56286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 56386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 56486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define NB_MMU_MODES 2 56586797937017f52bff088d02edf64fb931177a7eaJun Nakajima 56686797937017f52bff088d02edf64fb931177a7eaJun Nakajimatypedef struct CPUX86State { 56786797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* standard registers */ 56886797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong regs[CPU_NB_REGS]; 56986797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong eip; 57086797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong eflags; /* eflags register. During CPU emulation, CC 57186797937017f52bff088d02edf64fb931177a7eaJun Nakajima flags and DF are set to zero because they are 57286797937017f52bff088d02edf64fb931177a7eaJun Nakajima stored elsewhere */ 57386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 57486797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* emulator internal eflags handling */ 57586797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong cc_src; 57686797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong cc_dst; 57786797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cc_op; 57886797937017f52bff088d02edf64fb931177a7eaJun Nakajima int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ 57986797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t hflags; /* TB flags, see HF_xxx constants. These flags 58086797937017f52bff088d02edf64fb931177a7eaJun Nakajima are known at translation time. */ 58186797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ 58286797937017f52bff088d02edf64fb931177a7eaJun Nakajima 58386797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* segments */ 58486797937017f52bff088d02edf64fb931177a7eaJun Nakajima SegmentCache segs[6]; /* selector values */ 58586797937017f52bff088d02edf64fb931177a7eaJun Nakajima SegmentCache ldt; 58686797937017f52bff088d02edf64fb931177a7eaJun Nakajima SegmentCache tr; 58786797937017f52bff088d02edf64fb931177a7eaJun Nakajima SegmentCache gdt; /* only base and limit are used */ 58886797937017f52bff088d02edf64fb931177a7eaJun Nakajima SegmentCache idt; /* only base and limit are used */ 58986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 59086797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong cr[5]; /* NOTE: cr1 is unused */ 59186797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t a20_mask; 59286797937017f52bff088d02edf64fb931177a7eaJun Nakajima 59386797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* FPU state */ 59486797937017f52bff088d02edf64fb931177a7eaJun Nakajima unsigned int fpstt; /* top of stack index */ 59586797937017f52bff088d02edf64fb931177a7eaJun Nakajima unsigned int fpus; 59686797937017f52bff088d02edf64fb931177a7eaJun Nakajima unsigned int fpuc; 59786797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint8_t fptags[8]; /* 0 = valid, 1 = empty */ 59886797937017f52bff088d02edf64fb931177a7eaJun Nakajima union { 59986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifdef USE_X86LDOUBLE 60086797937017f52bff088d02edf64fb931177a7eaJun Nakajima CPU86_LDouble d __attribute__((aligned(16))); 60186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#else 60286797937017f52bff088d02edf64fb931177a7eaJun Nakajima CPU86_LDouble d; 60386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 60486797937017f52bff088d02edf64fb931177a7eaJun Nakajima MMXReg mmx; 60586797937017f52bff088d02edf64fb931177a7eaJun Nakajima } fpregs[8]; 60686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 60786797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* emulator internal variables */ 60886797937017f52bff088d02edf64fb931177a7eaJun Nakajima float_status fp_status; 60986797937017f52bff088d02edf64fb931177a7eaJun Nakajima CPU86_LDouble ft0; 61086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 61186797937017f52bff088d02edf64fb931177a7eaJun Nakajima float_status mmx_status; /* for 3DNow! float ops */ 61286797937017f52bff088d02edf64fb931177a7eaJun Nakajima float_status sse_status; 61386797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t mxcsr; 61486797937017f52bff088d02edf64fb931177a7eaJun Nakajima XMMReg xmm_regs[CPU_NB_REGS]; 61586797937017f52bff088d02edf64fb931177a7eaJun Nakajima XMMReg xmm_t0; 61686797937017f52bff088d02edf64fb931177a7eaJun Nakajima MMXReg mmx_t0; 61786797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong cc_tmp; /* temporary for rcr/rcl */ 61886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 61986797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* sysenter registers */ 62086797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t sysenter_cs; 62186797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong sysenter_esp; 62286797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong sysenter_eip; 62386797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t efer; 62486797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t star; 62586797937017f52bff088d02edf64fb931177a7eaJun Nakajima 62686797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t vm_hsave; 62786797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t vm_vmcb; 62886797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t tsc_offset; 62986797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t intercept; 63086797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint16_t intercept_cr_read; 63186797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint16_t intercept_cr_write; 63286797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint16_t intercept_dr_read; 63386797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint16_t intercept_dr_write; 63486797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t intercept_exceptions; 63586797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint8_t v_tpr; 63686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 63786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifdef TARGET_X86_64 63886797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong lstar; 63986797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong cstar; 64086797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong fmask; 64186797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong kernelgsbase; 64286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 64386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 64486797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t tsc; 64586797937017f52bff088d02edf64fb931177a7eaJun Nakajima 64686797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t pat; 64786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 64886797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* exception/interrupt handling */ 64986797937017f52bff088d02edf64fb931177a7eaJun Nakajima int error_code; 65086797937017f52bff088d02edf64fb931177a7eaJun Nakajima int exception_is_int; 65186797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong exception_next_eip; 65286797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong dr[8]; /* debug registers */ 65386797937017f52bff088d02edf64fb931177a7eaJun Nakajima union { 65486797937017f52bff088d02edf64fb931177a7eaJun Nakajima CPUBreakpoint *cpu_breakpoint[4]; 65586797937017f52bff088d02edf64fb931177a7eaJun Nakajima CPUWatchpoint *cpu_watchpoint[4]; 65686797937017f52bff088d02edf64fb931177a7eaJun Nakajima }; /* break/watchpoints for dr[0..3] */ 65786797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t smbase; 65886797937017f52bff088d02edf64fb931177a7eaJun Nakajima int old_exception; /* exception in flight */ 65986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 66086797937017f52bff088d02edf64fb931177a7eaJun Nakajima CPU_COMMON 66186797937017f52bff088d02edf64fb931177a7eaJun Nakajima 66286797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* processor features (e.g. for CPUID insn) */ 66386797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_level; 66486797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_vendor1; 66586797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_vendor2; 66686797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_vendor3; 66786797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_version; 66886797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_features; 66986797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_ext_features; 67086797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_xlevel; 67186797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_model[12]; 67286797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_ext2_features; 67386797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_ext3_features; 67486797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t cpuid_apic_id; 67586797937017f52bff088d02edf64fb931177a7eaJun Nakajima int cpuid_vendor_override; 67686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 67786797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* MTRRs */ 67886797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t mtrr_fixed[11]; 67986797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t mtrr_deftype; 68086797937017f52bff088d02edf64fb931177a7eaJun Nakajima struct { 68186797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t base; 68286797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t mask; 68386797937017f52bff088d02edf64fb931177a7eaJun Nakajima } mtrr_var[8]; 68486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 68586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifdef CONFIG_KQEMU 68686797937017f52bff088d02edf64fb931177a7eaJun Nakajima int kqemu_enabled; 68786797937017f52bff088d02edf64fb931177a7eaJun Nakajima int last_io_time; 68886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 68986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 69086797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* For KVM */ 69186797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64_t interrupt_bitmap[256 / 64]; 69286797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t mp_state; 69386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 69486797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* in order to simplify APIC support, we leave this pointer to the 69586797937017f52bff088d02edf64fb931177a7eaJun Nakajima user */ 69686797937017f52bff088d02edf64fb931177a7eaJun Nakajima struct APICState *apic_state; 69786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 69886797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64 mcg_cap; 69986797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64 mcg_status; 70086797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64 mcg_ctl; 70186797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint64 *mce_banks; 70286797937017f52bff088d02edf64fb931177a7eaJun Nakajima} CPUX86State; 70386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 70486797937017f52bff088d02edf64fb931177a7eaJun NakajimaCPUX86State *cpu_x86_init(const char *cpu_model); 70586797937017f52bff088d02edf64fb931177a7eaJun Nakajimaint cpu_x86_exec(CPUX86State *s); 70686797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_x86_close(CPUX86State *s); 70786797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, 70886797937017f52bff088d02edf64fb931177a7eaJun Nakajima ...)); 70986797937017f52bff088d02edf64fb931177a7eaJun Nakajimaint cpu_get_pic_interrupt(CPUX86State *s); 71086797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* MSDOS compatibility mode FPU exception support */ 71186797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_set_ferr(CPUX86State *s); 71286797937017f52bff088d02edf64fb931177a7eaJun Nakajima 71386797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* this function must always be used to load data in the segment 71486797937017f52bff088d02edf64fb931177a7eaJun Nakajima cache: it synchronizes the hflags with the segment cache values */ 71586797937017f52bff088d02edf64fb931177a7eaJun Nakajimastatic inline void cpu_x86_load_seg_cache(CPUX86State *env, 71686797937017f52bff088d02edf64fb931177a7eaJun Nakajima int seg_reg, unsigned int selector, 71786797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong base, 71886797937017f52bff088d02edf64fb931177a7eaJun Nakajima unsigned int limit, 71986797937017f52bff088d02edf64fb931177a7eaJun Nakajima unsigned int flags) 72086797937017f52bff088d02edf64fb931177a7eaJun Nakajima{ 72186797937017f52bff088d02edf64fb931177a7eaJun Nakajima SegmentCache *sc; 72286797937017f52bff088d02edf64fb931177a7eaJun Nakajima unsigned int new_hflags; 72386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 72486797937017f52bff088d02edf64fb931177a7eaJun Nakajima sc = &env->segs[seg_reg]; 72586797937017f52bff088d02edf64fb931177a7eaJun Nakajima sc->selector = selector; 72686797937017f52bff088d02edf64fb931177a7eaJun Nakajima sc->base = base; 72786797937017f52bff088d02edf64fb931177a7eaJun Nakajima sc->limit = limit; 72886797937017f52bff088d02edf64fb931177a7eaJun Nakajima sc->flags = flags; 72986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 73086797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* update the hidden flags */ 73186797937017f52bff088d02edf64fb931177a7eaJun Nakajima { 73286797937017f52bff088d02edf64fb931177a7eaJun Nakajima if (seg_reg == R_CS) { 73386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifdef TARGET_X86_64 73486797937017f52bff088d02edf64fb931177a7eaJun Nakajima if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 73586797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* long mode */ 73686797937017f52bff088d02edf64fb931177a7eaJun Nakajima env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 73786797937017f52bff088d02edf64fb931177a7eaJun Nakajima env->hflags &= ~(HF_ADDSEG_MASK); 73886797937017f52bff088d02edf64fb931177a7eaJun Nakajima } else 73986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 74086797937017f52bff088d02edf64fb931177a7eaJun Nakajima { 74186797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* legacy / compatibility case */ 74286797937017f52bff088d02edf64fb931177a7eaJun Nakajima new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) 74386797937017f52bff088d02edf64fb931177a7eaJun Nakajima >> (DESC_B_SHIFT - HF_CS32_SHIFT); 74486797937017f52bff088d02edf64fb931177a7eaJun Nakajima env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 74586797937017f52bff088d02edf64fb931177a7eaJun Nakajima new_hflags; 74686797937017f52bff088d02edf64fb931177a7eaJun Nakajima } 74786797937017f52bff088d02edf64fb931177a7eaJun Nakajima } 74886797937017f52bff088d02edf64fb931177a7eaJun Nakajima new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) 74986797937017f52bff088d02edf64fb931177a7eaJun Nakajima >> (DESC_B_SHIFT - HF_SS32_SHIFT); 75086797937017f52bff088d02edf64fb931177a7eaJun Nakajima if (env->hflags & HF_CS64_MASK) { 75186797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* zero base assumed for DS, ES and SS in long mode */ 75286797937017f52bff088d02edf64fb931177a7eaJun Nakajima } else if (!(env->cr[0] & CR0_PE_MASK) || 75386797937017f52bff088d02edf64fb931177a7eaJun Nakajima (env->eflags & VM_MASK) || 75486797937017f52bff088d02edf64fb931177a7eaJun Nakajima !(env->hflags & HF_CS32_MASK)) { 75586797937017f52bff088d02edf64fb931177a7eaJun Nakajima /* XXX: try to avoid this test. The problem comes from the 75686797937017f52bff088d02edf64fb931177a7eaJun Nakajima fact that is real mode or vm86 mode we only modify the 75786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 'base' and 'selector' fields of the segment cache to go 75886797937017f52bff088d02edf64fb931177a7eaJun Nakajima faster. A solution may be to force addseg to one in 75986797937017f52bff088d02edf64fb931177a7eaJun Nakajima translate-i386.c. */ 76086797937017f52bff088d02edf64fb931177a7eaJun Nakajima new_hflags |= HF_ADDSEG_MASK; 76186797937017f52bff088d02edf64fb931177a7eaJun Nakajima } else { 76286797937017f52bff088d02edf64fb931177a7eaJun Nakajima new_hflags |= ((env->segs[R_DS].base | 76386797937017f52bff088d02edf64fb931177a7eaJun Nakajima env->segs[R_ES].base | 76486797937017f52bff088d02edf64fb931177a7eaJun Nakajima env->segs[R_SS].base) != 0) << 76586797937017f52bff088d02edf64fb931177a7eaJun Nakajima HF_ADDSEG_SHIFT; 76686797937017f52bff088d02edf64fb931177a7eaJun Nakajima } 76786797937017f52bff088d02edf64fb931177a7eaJun Nakajima env->hflags = (env->hflags & 76886797937017f52bff088d02edf64fb931177a7eaJun Nakajima ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; 76986797937017f52bff088d02edf64fb931177a7eaJun Nakajima } 77086797937017f52bff088d02edf64fb931177a7eaJun Nakajima} 77186797937017f52bff088d02edf64fb931177a7eaJun Nakajima 77286797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* wrapper, just in case memory mappings must be changed */ 77386797937017f52bff088d02edf64fb931177a7eaJun Nakajimastatic inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) 77486797937017f52bff088d02edf64fb931177a7eaJun Nakajima{ 77586797937017f52bff088d02edf64fb931177a7eaJun Nakajima#if HF_CPL_MASK == 3 77686797937017f52bff088d02edf64fb931177a7eaJun Nakajima s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; 77786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#else 77886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#error HF_CPL_MASK is hardcoded 77986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 78086797937017f52bff088d02edf64fb931177a7eaJun Nakajima} 78186797937017f52bff088d02edf64fb931177a7eaJun Nakajima 78286797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* op_helper.c */ 78386797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* used for debug or cpu save/restore */ 78486797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f); 78586797937017f52bff088d02edf64fb931177a7eaJun NakajimaCPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper); 78686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 78786797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* cpu-exec.c */ 78886797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* the following helpers are only usable in user mode simulation as 78986797937017f52bff088d02edf64fb931177a7eaJun Nakajima they can trigger unexpected exceptions */ 79086797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); 79186797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); 79286797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); 79386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 79486797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* you can call this signal handler from your SIGBUS and SIGSEGV 79586797937017f52bff088d02edf64fb931177a7eaJun Nakajima signal handlers to inform the virtual CPU of exceptions. non zero 79686797937017f52bff088d02edf64fb931177a7eaJun Nakajima is returned if the signal was handled by the virtual CPU. */ 79786797937017f52bff088d02edf64fb931177a7eaJun Nakajimaint cpu_x86_signal_handler(int host_signum, void *pinfo, 79886797937017f52bff088d02edf64fb931177a7eaJun Nakajima void *puc); 79986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 80086797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* helper.c */ 80186797937017f52bff088d02edf64fb931177a7eaJun Nakajimaint cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, 80286797937017f52bff088d02edf64fb931177a7eaJun Nakajima int is_write, int mmu_idx, int is_softmmu); 80386797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_x86_set_a20(CPUX86State *env, int a20_state); 80486797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 80586797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t *eax, uint32_t *ebx, 80686797937017f52bff088d02edf64fb931177a7eaJun Nakajima uint32_t *ecx, uint32_t *edx); 80786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 80886797937017f52bff088d02edf64fb931177a7eaJun Nakajimastatic inline int hw_breakpoint_enabled(unsigned long dr7, int index) 80986797937017f52bff088d02edf64fb931177a7eaJun Nakajima{ 81086797937017f52bff088d02edf64fb931177a7eaJun Nakajima return (dr7 >> (index * 2)) & 3; 81186797937017f52bff088d02edf64fb931177a7eaJun Nakajima} 81286797937017f52bff088d02edf64fb931177a7eaJun Nakajima 81386797937017f52bff088d02edf64fb931177a7eaJun Nakajimastatic inline int hw_breakpoint_type(unsigned long dr7, int index) 81486797937017f52bff088d02edf64fb931177a7eaJun Nakajima{ 81586797937017f52bff088d02edf64fb931177a7eaJun Nakajima return (dr7 >> (DR7_TYPE_SHIFT + (index * 2))) & 3; 81686797937017f52bff088d02edf64fb931177a7eaJun Nakajima} 81786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 81886797937017f52bff088d02edf64fb931177a7eaJun Nakajimastatic inline int hw_breakpoint_len(unsigned long dr7, int index) 81986797937017f52bff088d02edf64fb931177a7eaJun Nakajima{ 82086797937017f52bff088d02edf64fb931177a7eaJun Nakajima int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 2))) & 3); 82186797937017f52bff088d02edf64fb931177a7eaJun Nakajima return (len == 2) ? 8 : len + 1; 82286797937017f52bff088d02edf64fb931177a7eaJun Nakajima} 82386797937017f52bff088d02edf64fb931177a7eaJun Nakajima 82486797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid hw_breakpoint_insert(CPUX86State *env, int index); 82586797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid hw_breakpoint_remove(CPUX86State *env, int index); 82686797937017f52bff088d02edf64fb931177a7eaJun Nakajimaint check_hw_breakpoints(CPUX86State *env, int force_dr6_update); 82786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 82886797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* will be suppressed */ 82986797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); 83086797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); 83186797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); 83286797937017f52bff088d02edf64fb931177a7eaJun Nakajima 83386797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* hw/apic.c */ 83486797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_set_apic_base(CPUX86State *env, uint64_t val); 83586797937017f52bff088d02edf64fb931177a7eaJun Nakajimauint64_t cpu_get_apic_base(CPUX86State *env); 83686797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_set_apic_tpr(CPUX86State *env, uint8_t val); 83786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifndef NO_CPU_IO_DEFS 83886797937017f52bff088d02edf64fb931177a7eaJun Nakajimauint8_t cpu_get_apic_tpr(CPUX86State *env); 83986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 84086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 84186797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* hw/pc.c */ 84286797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid cpu_smm_update(CPUX86State *env); 84386797937017f52bff088d02edf64fb931177a7eaJun Nakajimauint64_t cpu_get_tsc(CPUX86State *env); 84486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 84586797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* used to debug */ 84686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define X86_DUMP_FPU 0x0001 /* dump FPU state too */ 84786797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ 84886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 84986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#ifdef CONFIG_KQEMU 85086797937017f52bff088d02edf64fb931177a7eaJun Nakajimastatic inline int cpu_get_time_fast(void) 85186797937017f52bff088d02edf64fb931177a7eaJun Nakajima{ 85286797937017f52bff088d02edf64fb931177a7eaJun Nakajima int low, high; 85386797937017f52bff088d02edf64fb931177a7eaJun Nakajima asm volatile("rdtsc" : "=a" (low), "=d" (high)); 85486797937017f52bff088d02edf64fb931177a7eaJun Nakajima return low; 85586797937017f52bff088d02edf64fb931177a7eaJun Nakajima} 85686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 85786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 85886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define TARGET_PAGE_BITS 12 85986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 86086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define cpu_init cpu_x86_init 86186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define cpu_exec cpu_x86_exec 86286797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define cpu_gen_code cpu_x86_gen_code 86386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define cpu_signal_handler cpu_x86_signal_handler 86486797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define cpu_list x86_cpu_list 86586797937017f52bff088d02edf64fb931177a7eaJun Nakajima 86686797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define CPU_SAVE_VERSION 10 86786797937017f52bff088d02edf64fb931177a7eaJun Nakajima 86886797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* MMU modes definitions */ 86986797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMU_MODE0_SUFFIX _kernel 87086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMU_MODE1_SUFFIX _user 87186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#define MMU_USER_IDX 1 87286797937017f52bff088d02edf64fb931177a7eaJun Nakajimastatic inline int cpu_mmu_index (CPUState *env) 87386797937017f52bff088d02edf64fb931177a7eaJun Nakajima{ 87486797937017f52bff088d02edf64fb931177a7eaJun Nakajima return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0; 87586797937017f52bff088d02edf64fb931177a7eaJun Nakajima} 87686797937017f52bff088d02edf64fb931177a7eaJun Nakajima 87786797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* translate.c */ 87886797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid optimize_flags_init(void); 87986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 88086797937017f52bff088d02edf64fb931177a7eaJun Nakajimatypedef struct CCTable { 88186797937017f52bff088d02edf64fb931177a7eaJun Nakajima int (*compute_all)(void); /* return all the flags */ 88286797937017f52bff088d02edf64fb931177a7eaJun Nakajima int (*compute_c)(void); /* return the C flag */ 88386797937017f52bff088d02edf64fb931177a7eaJun Nakajima} CCTable; 88486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 88586797937017f52bff088d02edf64fb931177a7eaJun Nakajima/* XXX not defined yet. Should be fixed */ 88686797937017f52bff088d02edf64fb931177a7eaJun Nakajimastatic inline int is_cpu_user(CPUState *env) 88786797937017f52bff088d02edf64fb931177a7eaJun Nakajima{ 88886797937017f52bff088d02edf64fb931177a7eaJun Nakajima return 0; 88986797937017f52bff088d02edf64fb931177a7eaJun Nakajima} 89086797937017f52bff088d02edf64fb931177a7eaJun Nakajima 89186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#if defined(CONFIG_USER_ONLY) 89286797937017f52bff088d02edf64fb931177a7eaJun Nakajimastatic inline void cpu_clone_regs(CPUState *env, target_ulong newsp) 89386797937017f52bff088d02edf64fb931177a7eaJun Nakajima{ 89486797937017f52bff088d02edf64fb931177a7eaJun Nakajima if (newsp) 89586797937017f52bff088d02edf64fb931177a7eaJun Nakajima env->regs[R_ESP] = newsp; 89686797937017f52bff088d02edf64fb931177a7eaJun Nakajima env->regs[R_EAX] = 0; 89786797937017f52bff088d02edf64fb931177a7eaJun Nakajima} 89886797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif 89986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 90086797937017f52bff088d02edf64fb931177a7eaJun Nakajima#include "cpu-all.h" 90186797937017f52bff088d02edf64fb931177a7eaJun Nakajima#include "exec-all.h" 90286797937017f52bff088d02edf64fb931177a7eaJun Nakajima 90386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#include "svm.h" 90486797937017f52bff088d02edf64fb931177a7eaJun Nakajima 90586797937017f52bff088d02edf64fb931177a7eaJun Nakajimastatic inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) 90686797937017f52bff088d02edf64fb931177a7eaJun Nakajima{ 90786797937017f52bff088d02edf64fb931177a7eaJun Nakajima env->eip = tb->pc - tb->cs_base; 90886797937017f52bff088d02edf64fb931177a7eaJun Nakajima} 90986797937017f52bff088d02edf64fb931177a7eaJun Nakajima 91086797937017f52bff088d02edf64fb931177a7eaJun Nakajimastatic inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, 91186797937017f52bff088d02edf64fb931177a7eaJun Nakajima target_ulong *cs_base, int *flags) 91286797937017f52bff088d02edf64fb931177a7eaJun Nakajima{ 91386797937017f52bff088d02edf64fb931177a7eaJun Nakajima *cs_base = env->segs[R_CS].base; 91486797937017f52bff088d02edf64fb931177a7eaJun Nakajima *pc = *cs_base + env->eip; 91586797937017f52bff088d02edf64fb931177a7eaJun Nakajima *flags = env->hflags | 91686797937017f52bff088d02edf64fb931177a7eaJun Nakajima (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK)); 91786797937017f52bff088d02edf64fb931177a7eaJun Nakajima} 91886797937017f52bff088d02edf64fb931177a7eaJun Nakajima 91986797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid apic_init_reset(CPUState *env); 92086797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid apic_sipi(CPUState *env); 92186797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid do_cpu_init(CPUState *env); 92286797937017f52bff088d02edf64fb931177a7eaJun Nakajimavoid do_cpu_sipi(CPUState *env); 92386797937017f52bff088d02edf64fb931177a7eaJun Nakajima#endif /* CPU_I386_H */ 924