sad_halfpel_inline.h revision 3fdb405597f0e062a9bb8af20199c5e67f0f764c
1/* ------------------------------------------------------------------ 2 * Copyright (C) 1998-2009 PacketVideo 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either 13 * express or implied. 14 * See the License for the specific language governing permissions 15 * and limitations under the License. 16 * ------------------------------------------------------------------- 17 */ 18 19#ifndef _SAD_HALFPEL_INLINE_H_ 20#define _SAD_HALFPEL_INLINE_H_ 21 22#ifdef __cplusplus 23extern "C" 24{ 25#endif 26 27/* Intentionally not using the gcc asm version, since it (if fixed so 28 * as to not crash - the current register constraints are faulty) is 29 * slightly slower than the plain C version on modern GCC versions. */ 30#if !defined(__CC_ARM) /* Generic C version */ 31 32 __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 33 { 34 tmp = (tmp2 >> 1) - tmp; 35 if (tmp > 0) sad += tmp; 36 else sad -= tmp; 37 38 return sad; 39 } 40 41 __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 42 { 43 tmp = (tmp >> 2) - tmp2; 44 if (tmp > 0) sad += tmp; 45 else sad -= tmp; 46 47 return sad; 48 } 49 50#elif defined(__CC_ARM) /* only work with arm v5 */ 51 52 __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 53 { 54 __asm 55 { 56 rsbs tmp, tmp, tmp2, asr #1 ; 57 rsbmi tmp, tmp, #0 ; 58 add sad, sad, tmp ; 59 } 60 61 return sad; 62 } 63 64 __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 65 { 66 __asm 67 { 68 rsbs tmp, tmp2, tmp, asr #2 ; 69 rsbmi tmp, tmp, #0 ; 70 add sad, sad, tmp ; 71 } 72 73 return sad; 74 } 75 76#elif defined(__GNUC__) && defined(__arm__) /* ARM GNU COMPILER */ 77 78 __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 79 { 80 __asm__ volatile( 81 "rsbs %1, %1, %2, asr #1\n\t" 82 "rsbmi %1, %1, #0\n\t" 83 "add %0, %0, %1" 84 : "+r"(sad), "+r"(tmp) 85 : "r"(tmp2) 86 ); 87 88 return sad; 89 } 90 91 __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 92 { 93 __asm__ volatile( 94 "rsbs %1, %2, %1, asr #2\n\t" 95 "rsbmi %1, %1, #0\n\t" 96 "add %0, %0, %1" 97 : "+r"(sad), "+r"(tmp) 98 : "r"(tmp2) 99 ); 100 101 return sad; 102 } 103 104#endif 105 106#ifdef __cplusplus 107} 108#endif 109 110#endif //_SAD_HALFPEL_INLINE_H_ 111 112