1a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/* 2a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * Device.h 3a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * 4a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * Copyright(c) 1998 - 2009 Texas Instruments. All rights reserved. 5a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * All rights reserved. 6a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * 7a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * Redistribution and use in source and binary forms, with or without 8a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * modification, are permitted provided that the following conditions 9a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * are met: 10a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * 11a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * * Redistributions of source code must retain the above copyright 12a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * notice, this list of conditions and the following disclaimer. 13a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * * Redistributions in binary form must reproduce the above copyright 14a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * notice, this list of conditions and the following disclaimer in 15a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * the documentation and/or other materials provided with the 16a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * distribution. 17a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * * Neither the name Texas Instruments nor the names of its 18a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * contributors may be used to endorse or promote products derived 19a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * from this software without specific prior written permission. 20a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * 21a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt */ 33a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 34a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 35a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/**************************************************************************** 36a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * 37a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * MODULE: Device.h 38a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * PURPOSE: Contains Wlan hardware registers defines/structures 39a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * 40a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ****************************************************************************/ 41a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 42a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#ifndef DEVICE_H 43a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define DEVICE_H 44a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 45a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#include "Device1273.h" 46a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 47a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 48a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_PHI_CCA_THRSH_ENABLE_ENERGY_D 0x140A 49a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_PHI_CCA_THRSH_DISABLE_ENERGY_D 0xFFEF 50a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 51a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/* 52a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * Wlan hardware Registers. 53a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt */ 54a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 55a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*====================================================================== 56a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Interrupt Registers 57a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt=======================================================================*/ 58a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 59a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_REG_INTERRUPT_TRIG ( INT_TRIG ) 60a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 61a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_REG_INTERRUPT_TRIG_H ( INT_TRIG_H ) 62a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 63a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*============================================= 64a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Host Interrupt Mask Register - 32bit (RW) 65a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 66a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Setting a bit in this register masks the 67a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt corresponding interrupt to the host. 68a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 0 - RX0 - Rx first dubble buffer Data Interrupt 69a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 1 - TXD - Tx Data Interrupt 70a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 2 - TXXFR - Tx Transfer Interrupt 71a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 3 - RX1 - Rx second dubble buffer Data Interrupt 72a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 4 - RXXFR - Rx Transfer Interrupt 73a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 5 - EVENT_A - Event Mailbox interrupt 74a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 6 - EVENT_B - Event Mailbox interrupt 75a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 7 - WNONHST - Wake On Host Interrupt 76a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 8 - TRACE_A - Debug Trace interrupt 77a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 9 - TRACE_B - Debug Trace interrupt 78a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 10 - CDCMP - Command Complete Interrupt 79a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 11 - 80a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 12 - 81a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 13 - 82a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 14 - ICOMP - Initialization Complete Interrupt 83a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 16 - SG SE - Soft Gemini - Sense enable interrupt 84a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 17 - SG SD - Soft Gemini - Sense disable interrupt 85a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 18 - - 86a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 19 - - 87a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 20 - - 88a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 21- - 89a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Default: 0x0001 90a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt*==============================================*/ 91a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_REG_INTERRUPT_MASK ( HINT_MASK ) 92a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 93a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*============================================= 94a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Host Interrupt Mask Set 16bit, (Write only) 95a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 96a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Setting a bit in this register sets 97a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the corresponding bin in ACX_HINT_MASK register 98a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt without effecting the mask 99a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt state of other bits (0 = no effect). 100a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt==============================================*/ 101a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_HINT_MASK_SET_REG HINT_MASK_SET 102a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 103a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*============================================= 104a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Host Interrupt Mask Clear 16bit,(Write only) 105a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 106a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Setting a bit in this register clears 107a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the corresponding bin in ACX_HINT_MASK register 108a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt without effecting the mask 109a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt state of other bits (0 = no effect). 110a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt=============================================*/ 111a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_HINT_MASK_CLR_REG HINT_MASK_CLR 112a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 113a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*============================================= 114a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Host Interrupt Status Nondestructive Read 115a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 16bit,(Read only) 116a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 117a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The host can read this register to determine 118a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt which interrupts are active. 119a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Reading this register doesn't 120a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt effect its content. 121a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt=============================================*/ 122a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_REG_INTERRUPT_NO_CLEAR ( HINT_STS_ND ) 123a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 124a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*============================================= 125a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Host Interrupt Status Clear on Read Register 126a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 16bit,(Read only) 127a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 128a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The host can read this register to determine 129a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt which interrupts are active. 130a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Reading this register clears it, 131a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt thus making all interrupts inactive. 132a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt==============================================*/ 133a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_REG_INTERRUPT_CLEAR ( HINT_STS_CLR ) 134a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 135a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*============================================= 136a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Host Interrupt Acknowledge Register 137a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 16bit,(Write only) 138a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 139a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The host can set individual bits in this 140a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt register to clear (acknowledge) the corresp. 141a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt interrupt status bits in the HINT_STS_CLR and 142a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HINT_STS_ND registers, thus making the 143a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt assotiated interrupt inactive. (0-no effect) 144a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt==============================================*/ 145a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_REG_INTERRUPT_ACK ( HINT_ACK ) 146a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 147a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 148a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 149a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Host Software Reset - 32bit RW 150a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 151a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt [31:1] Reserved 152a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 0 SOFT_RESET Soft Reset - When this bit is set, 153a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt it holds the Wlan hardware in a soft reset state. 154a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt This reset disables all MAC and baseband processor 155a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt clocks except the CardBus/PCI interface clock. 156a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt It also initializes all MAC state machines except 157a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the host interface. It does not reload the 158a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt contents of the EEPROM. When this bit is cleared 159a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt (not self-clearing), the Wlan hardware 160a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt exits the software reset state. 161a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt===============================================*/ 162a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_REG_SLV_SOFT_RESET ( SLV_SOFT_RESET ) 163a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt #define SLV_SOFT_RESET_BIT 0x00000001 164a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 165a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 166a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt EEPROM Burst Read Start - 32bit RW 167a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 168a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt [31:1] Reserved 169a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 0 ACX_EE_START - EEPROM Burst Read Start 0 170a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Setting this bit starts a burst read from 171a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the external EEPROM. 172a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt If this bit is set (after reset) before an EEPROM read/write, 173a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the burst read starts at EEPROM address 0. 174a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Otherwise, it starts at the address 175a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt following the address of the previous access. 176a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt TheWlan hardware hardware clears this bit automatically. 177a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 178a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Default: 0x00000000 179a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt*================================================*/ 180a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_REG_EE_START ( EE_START ) 181a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt #define START_EEPROM_MGR 0x00000001 182a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 183a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*======================================================================= 184a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Embedded ARM CPU Control 185a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt========================================================================*/ 186a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 187a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Halt eCPU - 32bit RW 188a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 189a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 0 HALT_ECPU Halt Embedded CPU - This bit is the 190a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt compliment of bit 1 (MDATA2) in the SOR_CFG register. 191a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt During a hardware reset, this bit holds 192a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the inverse of MDATA2. 193a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt When downloading firmware from the host, 194a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt set this bit (pull down MDATA2). 195a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The host clears this bit after downloading the firmware into 196a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt zero-wait-state SSRAM. 197a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt When loading firmware from Flash, clear this bit (pull up MDATA2) 198a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt so that the eCPU can run the bootloader code in Flash 199a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HALT_ECPU eCPU State 200a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt -------------------- 201a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 1 halt eCPU 202a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 0 enable eCPU 203a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt===============================================*/ 204a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_REG_ECPU_CONTROL ( ECPU_CTRL ) 205a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 206a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 207a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*======================================================================= 208a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Command/Information Mailbox Pointers 209a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt========================================================================*/ 210a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 211a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 212a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Command Mailbox Pointer - 32bit RW 213a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 214a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt This register holds the start address of 215a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the command mailbox located in the Wlan hardware memory. 216a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The host must read this pointer after a reset to 217a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt find the location of the command mailbox. 218a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The Wlan hardware initializes the command mailbox 219a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt pointer with the default address of the command mailbox. 220a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The command mailbox pointer is not valid until after 221a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the host receives the Init Complete interrupt from 222a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the Wlan hardware. 223a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt===============================================*/ 224a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define REG_COMMAND_MAILBOX_PTR ( SCR_PAD0 ) 225a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 226a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 227a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Information Mailbox Pointer - 32bit RW 228a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 229a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt This register holds the start address of 230a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the information mailbox located in the Wlan hardware memory. 231a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The host must read this pointer after a reset to find 232a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the location of the information mailbox. 233a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The Wlan hardware initializes the information mailbox pointer 234a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt with the default address of the information mailbox. 235a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The information mailbox pointer is not valid 236a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt until after the host receives the Init Complete interrupt from 237a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the Wlan hardware. 238a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt===============================================*/ 239a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define REG_EVENT_MAILBOX_PTR ( SCR_PAD1 ) 240a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 241a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 242a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*======================================================================= 243a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Misc 244a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt========================================================================*/ 245a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 246a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 247a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define REG_ENABLE_TX_RX ( IO_CONTROL_ENABLE ) 248a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/* 249a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * Rx configuration (filter) information element 250a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * --------------------------------------------- 251a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt */ 252a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define REG_RX_CONFIG ( RX_CFG ) 253a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define REG_RX_FILTER ( RX_FILTER_CFG ) 254a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 255a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002 256a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_PROMISCUOUS 0x0008 /* promiscuous - receives all valid frames */ 257a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_BSSID 0x0020 /* receives frames from any BSSID */ 258a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_MAC 0x0010 /* receives frames destined to any MAC address */ 259a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010 260a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000 261a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020 262a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_ENABLE_ANY_BSSID 0x0000 263a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_DISABLE_BCAST 0x0200 /* discards all broadcast frames */ 264a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400 265a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800 266a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_COPY_RX_STATUS 0x2000 267a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CFG_TSF 0x10000 268a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 269a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CONFIG_OPTION_ANY_DST_MY_BSS ( RX_CFG_ENABLE_ANY_DEST_MAC | RX_CFG_ENABLE_ONLY_MY_BSSID) 270a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CONFIG_OPTION_MY_DST_ANY_BSS ( RX_CFG_ENABLE_ONLY_MY_DEST_MAC | RX_CFG_ENABLE_ANY_BSSID) 271a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CONFIG_OPTION_ANY_DST_ANY_BSS ( RX_CFG_ENABLE_ANY_DEST_MAC | RX_CFG_ENABLE_ANY_BSSID) 272a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CONFIG_OPTION_MY_DST_MY_BSS ( RX_CFG_ENABLE_ONLY_MY_DEST_MAC | RX_CFG_ENABLE_ONLY_MY_BSSID) 273a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 274a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CONFIG_OPTION_FOR_SCAN ( RX_CFG_ENABLE_PHY_HEADER_PLCP | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF) 275a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CONFIG_OPTION_FOR_MEASUREMENT ( RX_CFG_ENABLE_ANY_DEST_MAC ) 276a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CONFIG_OPTION_FOR_JOIN ( RX_CFG_ENABLE_ONLY_MY_BSSID | RX_CFG_ENABLE_ONLY_MY_DEST_MAC ) 277a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_CONFIG_OPTION_FOR_IBSS_JOIN ( RX_CFG_ENABLE_ONLY_MY_SSID | RX_CFG_ENABLE_ONLY_MY_DEST_MAC ) 278a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 279a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_FILTER_OPTION_DEF ( CFG_RX_MGMT_EN | CFG_RX_DATA_EN | CFG_RX_CTL_EN | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN) 280a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_FILTER_OPTION_FILTER_ALL 0 281a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_FILTER_OPTION_DEF_PRSP_BCN ( CFG_RX_PRSP_EN | CFG_RX_MGMT_EN | CFG_RX_CTL_EN | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN) 282a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define RX_FILTER_OPTION_JOIN ( CFG_RX_MGMT_EN | CFG_RX_DATA_EN | CFG_RX_CTL_EN | CFG_RX_BCN_EN | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK | CFG_RX_PRSP_EN) 283a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 284a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 285a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 286a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Phy regs 287a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ===============================================*/ 288a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_PHY_ADDR_REG SBB_ADDR 289a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_PHY_DATA_REG SBB_DATA 290a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_PHY_CTRL_REG SBB_CTL 291a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_PHY_REG_WR_MASK 0x00000001ul 292a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_PHY_REG_RD_MASK 0x00000002ul 293a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 294a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 295a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 296a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt EEPROM Read/Write Request 32bit RW 297a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 298a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 1 EE_READ - EEPROM Read Request 1 - Setting this bit 299a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt loads a single byte of data into the EE_DATA 300a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt register from the EEPROM location specified in 301a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt the EE_ADDR register. 302a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The Wlan hardware hardware clears this bit automatically. 303a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt EE_DATA is valid when this bit is cleared. 304a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 0 EE_WRITE - EEPROM Write Request - Setting this bit 305a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt writes a single byte of data from the EE_DATA register into the 306a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt EEPROM location specified in the EE_ADDR register. 307a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The Wlan hardware hardware clears this bit automatically. 308a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt*===============================================*/ 309a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_EE_CTL_REG EE_CTL 310a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define EE_WRITE 0x00000001ul 311a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define EE_READ 0x00000002ul 312a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 313a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 314a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt EEPROM Address - 32bit RW 315a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 316a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt This register specifies the address 317a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt within the EEPROM from/to which to read/write data. 318a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt===============================================*/ 319a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_EE_ADDR_REG EE_ADDR 320a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 321a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 322a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt EEPROM Data - 32bit RW 323a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 324a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt This register either holds the read 8 bits of 325a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt data from the EEPROM or the write data 326a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt to be written to the EEPROM. 327a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt===============================================*/ 328a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_EE_DATA_REG EE_DATA 329a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 330a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 331a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt EEPROM Base Address - 32bit RW 332a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 333a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt This register holds the upper nine bits 334a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt [23:15] of the 24-bit Wlan hardware memory 335a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt address for burst reads from EEPROM accesses. 336a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The EEPROM provides the lower 15 bits of this address. 337a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt The MSB of the address from the EEPROM is ignored. 338a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt===============================================*/ 339a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_EE_CFG EE_CFG 340a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 341a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 342a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt GPIO Output Values -32bit, RW 343a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 344a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt [31:16] Reserved 345a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt [15: 0] Specify the output values (at the output driver inputs) for 346a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt GPIO[15:0], respectively. 347a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt===============================================*/ 348a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_GPIO_OUT_REG GPIO_OUT 349a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_MAX_GPIO_LINES 15 350a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 351a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 352a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt Contention window -32bit, RW 353a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 354a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt [31:26] Reserved 355a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt [25:16] Max (0x3ff) 356a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt [15:07] Reserved 357a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt [06:00] Current contention window value - default is 0x1F 358a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt===============================================*/ 359a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG 360a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_CONT_WIND_MIN_MASK 0x0000007f 361a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_CONT_WIND_MAX 0x03ff0000 362a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 363a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/* 364a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * Indirect slave register/memory registers 365a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * ---------------------------------------- 366a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt */ 367a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HW_SLAVE_REG_ADDR_REG 0x00000004 368a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HW_SLAVE_REG_DATA_REG 0x00000008 369a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HW_SLAVE_REG_CTRL_REG 0x0000000c 370a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 371a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define SLAVE_AUTO_INC 0x00010000 372a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define SLAVE_NO_AUTO_INC 0x00000000 373a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define SLAVE_HOST_LITTLE_ENDIAN 0x00000000 374a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 375a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HW_SLAVE_MEM_ADDR_REG SLV_MEM_ADDR 376a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HW_SLAVE_MEM_DATA_REG SLV_MEM_DATA 377a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HW_SLAVE_MEM_CTRL_REG SLV_MEM_CTL 378a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HW_SLAVE_MEM_ENDIAN_REG SLV_END_CTL 379a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 380a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HW_FUNC_EVENT_INT_EN 0x8000 381a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HW_FUNC_EVENT_MASK_REG 0x00000034 382a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 383a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define ACX_MAC_TIMESTAMP_REG (MAC_TIMESTAMP) 384a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 385a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/*=============================================== 386a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HI_CFG Interface Configuration Register Values 387a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt ------------------------------------------ 388a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt===============================================*/ 389a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HI_CFG_UART_ENABLE 0x00000004 390a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HI_CFG_RST232_ENABLE 0x00000008 391a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HI_CFG_CLOCK_REQ_SELECT 0x00000010 392a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HI_CFG_HOST_INT_ENABLE 0x00000020 393a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040 394a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080 395a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100 396a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200 397a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400 398a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 399a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt/* 400a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile 401a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt * for platforms using active high interrupt level 402a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt */ 403a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#ifdef USE_IRQ_ACTIVE_HIGH 404a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HI_CFG_DEF_VAL \ 405a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HI_CFG_UART_ENABLE | \ 406a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HI_CFG_RST232_ENABLE | \ 407a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HI_CFG_CLOCK_REQ_SELECT | \ 408a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HI_CFG_HOST_INT_ENABLE 409a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#else 410a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#define HI_CFG_DEF_VAL \ 411a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HI_CFG_UART_ENABLE | \ 412a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HI_CFG_RST232_ENABLE | \ 413a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HI_CFG_CLOCK_REQ_SELECT | \ 414a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HI_CFG_HOST_INT_ENABLE | \ 415a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt HI_CFG_HOST_INT_ACTIVE_LOW 416a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#endif 417a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 418a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt#endif /* DEVICE_H */ 419a615fb1650af6e111053506f1b764b28a5b4631dDmitry Shmidt 420