1/* $NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $ */ 2 3/*- 4 * Copyright (c) 1996 Mark Brinicombe. 5 * Copyright (c) 1996 Brini. 6 * 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Brini. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * RiscBSD kernel project 37 * 38 * db_disasm.c 39 * 40 * Kernel disassembler 41 * 42 * Created : 10/02/96 43 * 44 * Structured after the sparc/sparc/db_disasm.c by David S. Miller & 45 * Paul Kranenburg 46 * 47 * This code is not complete. Not all instructions are disassembled. 48 */ 49 50#include <sys/cdefs.h> 51//__FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/arm/arm/disassem.c,v 1.2 2005/01/05 21:58:47 imp Exp $"); 52#include <sys/param.h> 53#include <stdio.h> 54 55#include "disassem.h" 56#include "armreg.h" 57//#include <ddb/ddb.h> 58 59/* 60 * General instruction format 61 * 62 * insn[cc][mod] [operands] 63 * 64 * Those fields with an uppercase format code indicate that the field 65 * follows directly after the instruction before the separator i.e. 66 * they modify the instruction rather than just being an operand to 67 * the instruction. The only exception is the writeback flag which 68 * follows a operand. 69 * 70 * 71 * 2 - print Operand 2 of a data processing instruction 72 * d - destination register (bits 12-15) 73 * n - n register (bits 16-19) 74 * s - s register (bits 8-11) 75 * o - indirect register rn (bits 16-19) (used by swap) 76 * m - m register (bits 0-3) 77 * a - address operand of ldr/str instruction 78 * e - address operand of ldrh/strh instruction 79 * l - register list for ldm/stm instruction 80 * f - 1st fp operand (register) (bits 12-14) 81 * g - 2nd fp operand (register) (bits 16-18) 82 * h - 3rd fp operand (register/immediate) (bits 0-4) 83 * j - xtb rotate literal (bits 10-11) 84 * i - bfx lsb literal (bits 7-11) 85 * w - bfx width literal (bits 16-20) 86 * b - branch address 87 * t - thumb branch address (bits 24, 0-23) 88 * k - breakpoint comment (bits 0-3, 8-19) 89 * X - block transfer type 90 * Y - block transfer type (r13 base) 91 * c - comment field bits(0-23) 92 * p - saved or current status register 93 * F - PSR transfer fields 94 * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN 95 * L - co-processor transfer size 96 * S - set status flag 97 * P - fp precision 98 * Q - fp precision (for ldf/stf) 99 * R - fp rounding 100 * v - co-processor data transfer registers + addressing mode 101 * W - writeback flag 102 * x - instruction in hex 103 * # - co-processor number 104 * y - co-processor data processing registers 105 * z - co-processor register transfer registers 106 */ 107 108struct arm32_insn { 109 u_int mask; 110 u_int pattern; 111 char* name; 112 char* format; 113}; 114 115static const struct arm32_insn arm32_i[] = { 116 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */ 117 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */ 118 { 0x0f000000, 0x0f000000, "swi", "c" }, 119 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */ 120 { 0x0f000000, 0x0a000000, "b", "b" }, 121 { 0x0f000000, 0x0b000000, "bl", "b" }, 122 { 0x0fe000f0, 0x00000090, "mul", "Snms" }, 123 { 0x0fe000f0, 0x00200090, "mla", "Snmsd" }, 124 { 0x0fe000f0, 0x00800090, "umull", "Sdnms" }, 125 { 0x0fe000f0, 0x00c00090, "smull", "Sdnms" }, 126 { 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" }, 127 { 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" }, 128 { 0x0fff03f0, 0x06cf0070, "uxtb16", "dmj" }, 129 { 0x0fe00070, 0x07e00050, "ubfx", "dmiw" }, 130 { 0x0d700000, 0x04200000, "strt", "daW" }, 131 { 0x0d700000, 0x04300000, "ldrt", "daW" }, 132 { 0x0d700000, 0x04600000, "strbt", "daW" }, 133 { 0x0d700000, 0x04700000, "ldrbt", "daW" }, 134 { 0x0c500000, 0x04000000, "str", "daW" }, 135 { 0x0c500000, 0x04100000, "ldr", "daW" }, 136 { 0x0c500000, 0x04400000, "strb", "daW" }, 137 { 0x0c500000, 0x04500000, "ldrb", "daW" }, 138 { 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */ 139 { 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */ 140 { 0x0e100000, 0x08000000, "stm", "XnWl" }, 141 { 0x0e100000, 0x08100000, "ldm", "XnWl" }, 142 { 0x0e1000f0, 0x00100090, "ldrb", "deW" }, 143 { 0x0e1000f0, 0x00000090, "strb", "deW" }, 144 { 0x0e1000f0, 0x001000d0, "ldrsb", "deW" }, 145 { 0x0e1000f0, 0x001000b0, "ldrh", "deW" }, 146 { 0x0e1000f0, 0x000000b0, "strh", "deW" }, 147 { 0x0e1000f0, 0x001000f0, "ldrsh", "deW" }, 148 { 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */ 149 { 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */ 150 { 0x0ff00ff0, 0x01000090, "swp", "dmo" }, 151 { 0x0ff00ff0, 0x01400090, "swpb", "dmo" }, 152 { 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */ 153 { 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */ 154 { 0x0fb0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */ 155 { 0x0ffffff0, 0x012fff10, "bx", "m" }, 156 { 0x0fff0ff0, 0x016f0f10, "clz", "dm" }, 157 { 0x0ffffff0, 0x012fff30, "blx", "m" }, 158 { 0xfff000f0, 0xe1200070, "bkpt", "k" }, 159 { 0x0de00000, 0x00000000, "and", "Sdn2" }, 160 { 0x0de00000, 0x00200000, "eor", "Sdn2" }, 161 { 0x0de00000, 0x00400000, "sub", "Sdn2" }, 162 { 0x0de00000, 0x00600000, "rsb", "Sdn2" }, 163 { 0x0de00000, 0x00800000, "add", "Sdn2" }, 164 { 0x0de00000, 0x00a00000, "adc", "Sdn2" }, 165 { 0x0de00000, 0x00c00000, "sbc", "Sdn2" }, 166 { 0x0de00000, 0x00e00000, "rsc", "Sdn2" }, 167 { 0x0df00000, 0x01100000, "tst", "Dn2" }, 168 { 0x0df00000, 0x01300000, "teq", "Dn2" }, 169 { 0x0df00000, 0x01500000, "cmp", "Dn2" }, 170 { 0x0df00000, 0x01700000, "cmn", "Dn2" }, 171 { 0x0de00000, 0x01800000, "orr", "Sdn2" }, 172 { 0x0de00000, 0x01a00000, "mov", "Sd2" }, 173 { 0x0de00000, 0x01c00000, "bic", "Sdn2" }, 174 { 0x0de00000, 0x01e00000, "mvn", "Sd2" }, 175 { 0x0ff08f10, 0x0e000100, "adf", "PRfgh" }, 176 { 0x0ff08f10, 0x0e100100, "muf", "PRfgh" }, 177 { 0x0ff08f10, 0x0e200100, "suf", "PRfgh" }, 178 { 0x0ff08f10, 0x0e300100, "rsf", "PRfgh" }, 179 { 0x0ff08f10, 0x0e400100, "dvf", "PRfgh" }, 180 { 0x0ff08f10, 0x0e500100, "rdf", "PRfgh" }, 181 { 0x0ff08f10, 0x0e600100, "pow", "PRfgh" }, 182 { 0x0ff08f10, 0x0e700100, "rpw", "PRfgh" }, 183 { 0x0ff08f10, 0x0e800100, "rmf", "PRfgh" }, 184 { 0x0ff08f10, 0x0e900100, "fml", "PRfgh" }, 185 { 0x0ff08f10, 0x0ea00100, "fdv", "PRfgh" }, 186 { 0x0ff08f10, 0x0eb00100, "frd", "PRfgh" }, 187 { 0x0ff08f10, 0x0ec00100, "pol", "PRfgh" }, 188 { 0x0f008f10, 0x0e000100, "fpbop", "PRfgh" }, 189 { 0x0ff08f10, 0x0e008100, "mvf", "PRfh" }, 190 { 0x0ff08f10, 0x0e108100, "mnf", "PRfh" }, 191 { 0x0ff08f10, 0x0e208100, "abs", "PRfh" }, 192 { 0x0ff08f10, 0x0e308100, "rnd", "PRfh" }, 193 { 0x0ff08f10, 0x0e408100, "sqt", "PRfh" }, 194 { 0x0ff08f10, 0x0e508100, "log", "PRfh" }, 195 { 0x0ff08f10, 0x0e608100, "lgn", "PRfh" }, 196 { 0x0ff08f10, 0x0e708100, "exp", "PRfh" }, 197 { 0x0ff08f10, 0x0e808100, "sin", "PRfh" }, 198 { 0x0ff08f10, 0x0e908100, "cos", "PRfh" }, 199 { 0x0ff08f10, 0x0ea08100, "tan", "PRfh" }, 200 { 0x0ff08f10, 0x0eb08100, "asn", "PRfh" }, 201 { 0x0ff08f10, 0x0ec08100, "acs", "PRfh" }, 202 { 0x0ff08f10, 0x0ed08100, "atn", "PRfh" }, 203 { 0x0f008f10, 0x0e008100, "fpuop", "PRfh" }, 204 { 0x0e100f00, 0x0c000100, "stf", "QLv" }, 205 { 0x0e100f00, 0x0c100100, "ldf", "QLv" }, 206 { 0x0ff00f10, 0x0e000110, "flt", "PRgd" }, 207 { 0x0ff00f10, 0x0e100110, "fix", "PRdh" }, 208 { 0x0ff00f10, 0x0e200110, "wfs", "d" }, 209 { 0x0ff00f10, 0x0e300110, "rfs", "d" }, 210 { 0x0ff00f10, 0x0e400110, "wfc", "d" }, 211 { 0x0ff00f10, 0x0e500110, "rfc", "d" }, 212 { 0x0ff0ff10, 0x0e90f110, "cmf", "PRgh" }, 213 { 0x0ff0ff10, 0x0eb0f110, "cnf", "PRgh" }, 214 { 0x0ff0ff10, 0x0ed0f110, "cmfe", "PRgh" }, 215 { 0x0ff0ff10, 0x0ef0f110, "cnfe", "PRgh" }, 216 { 0xff100010, 0xfe000010, "mcr2", "#z" }, 217 { 0x0f100010, 0x0e000010, "mcr", "#z" }, 218 { 0xff100010, 0xfe100010, "mrc2", "#z" }, 219 { 0x0f100010, 0x0e100010, "mrc", "#z" }, 220 { 0xff000010, 0xfe000000, "cdp2", "#y" }, 221 { 0x0f000010, 0x0e000000, "cdp", "#y" }, 222 { 0xfe100090, 0xfc100000, "ldc2", "L#v" }, 223 { 0x0e100090, 0x0c100000, "ldc", "L#v" }, 224 { 0xfe100090, 0xfc000000, "stc2", "L#v" }, 225 { 0x0e100090, 0x0c000000, "stc", "L#v" }, 226 { 0xf550f000, 0xf550f000, "pld", "ne" }, 227 { 0x0ff00ff0, 0x01000050, "qaad", "dmn" }, 228 { 0x0ff00ff0, 0x01400050, "qdaad", "dmn" }, 229 { 0x0ff00ff0, 0x01600050, "qdsub", "dmn" }, 230 { 0x0ff00ff0, 0x01200050, "dsub", "dmn" }, 231 { 0x0ff000f0, 0x01000080, "smlabb", "nmsd" }, // d & n inverted!! 232 { 0x0ff000f0, 0x010000a0, "smlatb", "nmsd" }, // d & n inverted!! 233 { 0x0ff000f0, 0x010000c0, "smlabt", "nmsd" }, // d & n inverted!! 234 { 0x0ff000f0, 0x010000e0, "smlatt", "nmsd" }, // d & n inverted!! 235 { 0x0ff000f0, 0x01400080, "smlalbb","ndms" }, // d & n inverted!! 236 { 0x0ff000f0, 0x014000a0, "smlaltb","ndms" }, // d & n inverted!! 237 { 0x0ff000f0, 0x014000c0, "smlalbt","ndms" }, // d & n inverted!! 238 { 0x0ff000f0, 0x014000e0, "smlaltt","ndms" }, // d & n inverted!! 239 { 0x0ff000f0, 0x01200080, "smlawb", "nmsd" }, // d & n inverted!! 240 { 0x0ff0f0f0, 0x012000a0, "smulwb","nms" }, // d & n inverted!! 241 { 0x0ff000f0, 0x012000c0, "smlawt", "nmsd" }, // d & n inverted!! 242 { 0x0ff0f0f0, 0x012000e0, "smulwt","nms" }, // d & n inverted!! 243 { 0x0ff0f0f0, 0x01600080, "smulbb","nms" }, // d & n inverted!! 244 { 0x0ff0f0f0, 0x016000a0, "smultb","nms" }, // d & n inverted!! 245 { 0x0ff0f0f0, 0x016000c0, "smulbt","nms" }, // d & n inverted!! 246 { 0x0ff0f0f0, 0x016000e0, "smultt","nms" }, // d & n inverted!! 247 { 0x00000000, 0x00000000, NULL, NULL } 248}; 249 250static char const arm32_insn_conditions[][4] = { 251 "eq", "ne", "cs", "cc", 252 "mi", "pl", "vs", "vc", 253 "hi", "ls", "ge", "lt", 254 "gt", "le", "", "nv" 255}; 256 257static char const insn_block_transfers[][4] = { 258 "da", "ia", "db", "ib" 259}; 260 261static char const insn_stack_block_transfers[][4] = { 262 "ed", "ea", "fd", "fa" 263}; 264 265static char const op_shifts[][4] = { 266 "lsl", "lsr", "asr", "ror" 267}; 268 269static char const insn_fpa_rounding[][2] = { 270 "", "p", "m", "z" 271}; 272 273static char const insn_fpa_precision[][2] = { 274 "s", "d", "e", "p" 275}; 276 277static char const insn_fpaconstants[][8] = { 278 "0.0", "1.0", "2.0", "3.0", 279 "4.0", "5.0", "0.5", "10.0" 280}; 281 282#define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f] 283#define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3] 284#define insn_stkblktrans(x) insn_stack_block_transfers[(3*((x >> 20)&1))^((x >> 23)&3)] 285#define op2_shift(x) op_shifts[(x >> 5) & 3] 286#define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03] 287#define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1] 288#define insn_fpaprect(x) insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1] 289#define insn_fpaimm(x) insn_fpaconstants[x & 0x07] 290 291/* Local prototypes */ 292static void disasm_register_shift(const disasm_interface_t *di, u_int insn); 293static void disasm_print_reglist(const disasm_interface_t *di, u_int insn); 294static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, 295 u_int loc); 296static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, 297 u_int loc); 298static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, 299 u_int loc); 300static u_int disassemble_readword(u_int address); 301static void disassemble_printaddr(u_int address); 302 303u_int 304disasm(const disasm_interface_t *di, u_int loc, int altfmt) 305{ 306 const struct arm32_insn *i_ptr = &arm32_i[0]; 307 308 u_int insn; 309 int matchp; 310 int branch; 311 char* f_ptr; 312 int fmt; 313 314 fmt = 0; 315 matchp = 0; 316 insn = di->di_readword(loc); 317 318/* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/ 319 320 while (i_ptr->name) { 321 if ((insn & i_ptr->mask) == i_ptr->pattern) { 322 matchp = 1; 323 break; 324 } 325 i_ptr++; 326 } 327 328 if (!matchp) { 329 di->di_printf("und%s\t%08x\n", insn_condition(insn), insn); 330 return(loc + INSN_SIZE); 331 } 332 333 /* If instruction forces condition code, don't print it. */ 334 if ((i_ptr->mask & 0xf0000000) == 0xf0000000) 335 di->di_printf("%s", i_ptr->name); 336 else 337 di->di_printf("%s%s", i_ptr->name, insn_condition(insn)); 338 339 f_ptr = i_ptr->format; 340 341 /* Insert tab if there are no instruction modifiers */ 342 343 if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') { 344 ++fmt; 345 di->di_printf("\t"); 346 } 347 348 while (*f_ptr) { 349 switch (*f_ptr) { 350 /* 2 - print Operand 2 of a data processing instruction */ 351 case '2': 352 if (insn & 0x02000000) { 353 int rotate= ((insn >> 7) & 0x1e); 354 355 di->di_printf("#0x%08x", 356 (insn & 0xff) << (32 - rotate) | 357 (insn & 0xff) >> rotate); 358 } else { 359 disasm_register_shift(di, insn); 360 } 361 break; 362 /* d - destination register (bits 12-15) */ 363 case 'd': 364 di->di_printf("r%d", ((insn >> 12) & 0x0f)); 365 break; 366 /* D - insert 'p' if Rd is R15 */ 367 case 'D': 368 if (((insn >> 12) & 0x0f) == 15) 369 di->di_printf("p"); 370 break; 371 /* n - n register (bits 16-19) */ 372 case 'n': 373 di->di_printf("r%d", ((insn >> 16) & 0x0f)); 374 break; 375 /* s - s register (bits 8-11) */ 376 case 's': 377 di->di_printf("r%d", ((insn >> 8) & 0x0f)); 378 break; 379 /* o - indirect register rn (bits 16-19) (used by swap) */ 380 case 'o': 381 di->di_printf("[r%d]", ((insn >> 16) & 0x0f)); 382 break; 383 /* m - m register (bits 0-4) */ 384 case 'm': 385 di->di_printf("r%d", ((insn >> 0) & 0x0f)); 386 break; 387 /* a - address operand of ldr/str instruction */ 388 case 'a': 389 disasm_insn_ldrstr(di, insn, loc); 390 break; 391 /* e - address operand of ldrh/strh instruction */ 392 case 'e': 393 disasm_insn_ldrhstrh(di, insn, loc); 394 break; 395 /* l - register list for ldm/stm instruction */ 396 case 'l': 397 disasm_print_reglist(di, insn); 398 break; 399 /* f - 1st fp operand (register) (bits 12-14) */ 400 case 'f': 401 di->di_printf("f%d", (insn >> 12) & 7); 402 break; 403 /* g - 2nd fp operand (register) (bits 16-18) */ 404 case 'g': 405 di->di_printf("f%d", (insn >> 16) & 7); 406 break; 407 /* h - 3rd fp operand (register/immediate) (bits 0-4) */ 408 case 'h': 409 if (insn & (1 << 3)) 410 di->di_printf("#%s", insn_fpaimm(insn)); 411 else 412 di->di_printf("f%d", insn & 7); 413 break; 414 /* j - xtb rotate literal (bits 10-11) */ 415 case 'j': 416 di->di_printf("ror #%d", ((insn >> 10) & 3) << 3); 417 break; 418 /* i - bfx lsb literal (bits 7-11) */ 419 case 'i': 420 di->di_printf("#%d", (insn >> 7) & 31); 421 break; 422 /* w - bfx width literal (bits 16-20) */ 423 case 'w': 424 di->di_printf("#%d", 1 + ((insn >> 16) & 31)); 425 break; 426 /* b - branch address */ 427 case 'b': 428 branch = ((insn << 2) & 0x03ffffff); 429 if (branch & 0x02000000) 430 branch |= 0xfc000000; 431 di->di_printaddr(loc + 8 + branch); 432 break; 433 /* t - blx address */ 434 case 't': 435 branch = ((insn << 2) & 0x03ffffff) | 436 (insn >> 23 & 0x00000002); 437 if (branch & 0x02000000) 438 branch |= 0xfc000000; 439 di->di_printaddr(loc + 8 + branch); 440 break; 441 /* X - block transfer type */ 442 case 'X': 443 di->di_printf("%s", insn_blktrans(insn)); 444 break; 445 /* Y - block transfer type (r13 base) */ 446 case 'Y': 447 di->di_printf("%s", insn_stkblktrans(insn)); 448 break; 449 /* c - comment field bits(0-23) */ 450 case 'c': 451 di->di_printf("0x%08x", (insn & 0x00ffffff)); 452 break; 453 /* k - breakpoint comment (bits 0-3, 8-19) */ 454 case 'k': 455 di->di_printf("0x%04x", 456 (insn & 0x000fff00) >> 4 | (insn & 0x0000000f)); 457 break; 458 /* p - saved or current status register */ 459 case 'p': 460 if (insn & 0x00400000) 461 di->di_printf("spsr"); 462 else 463 di->di_printf("cpsr"); 464 break; 465 /* F - PSR transfer fields */ 466 case 'F': 467 di->di_printf("_"); 468 if (insn & (1 << 16)) 469 di->di_printf("c"); 470 if (insn & (1 << 17)) 471 di->di_printf("x"); 472 if (insn & (1 << 18)) 473 di->di_printf("s"); 474 if (insn & (1 << 19)) 475 di->di_printf("f"); 476 break; 477 /* B - byte transfer flag */ 478 case 'B': 479 if (insn & 0x00400000) 480 di->di_printf("b"); 481 break; 482 /* L - co-processor transfer size */ 483 case 'L': 484 if (insn & (1 << 22)) 485 di->di_printf("l"); 486 break; 487 /* S - set status flag */ 488 case 'S': 489 if (insn & 0x00100000) 490 di->di_printf("s"); 491 break; 492 /* P - fp precision */ 493 case 'P': 494 di->di_printf("%s", insn_fpaprec(insn)); 495 break; 496 /* Q - fp precision (for ldf/stf) */ 497 case 'Q': 498 break; 499 /* R - fp rounding */ 500 case 'R': 501 di->di_printf("%s", insn_fparnd(insn)); 502 break; 503 /* W - writeback flag */ 504 case 'W': 505 if (insn & (1 << 21)) 506 di->di_printf("!"); 507 break; 508 /* # - co-processor number */ 509 case '#': 510 di->di_printf("p%d", (insn >> 8) & 0x0f); 511 break; 512 /* v - co-processor data transfer registers+addressing mode */ 513 case 'v': 514 disasm_insn_ldcstc(di, insn, loc); 515 break; 516 /* x - instruction in hex */ 517 case 'x': 518 di->di_printf("0x%08x", insn); 519 break; 520 /* y - co-processor data processing registers */ 521 case 'y': 522 di->di_printf("%d, ", (insn >> 20) & 0x0f); 523 524 di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f, 525 (insn >> 16) & 0x0f, insn & 0x0f); 526 527 di->di_printf(", %d", (insn >> 5) & 0x07); 528 break; 529 /* z - co-processor register transfer registers */ 530 case 'z': 531 di->di_printf("%d, ", (insn >> 21) & 0x07); 532 di->di_printf("r%d, c%d, c%d, %d", 533 (insn >> 12) & 0x0f, (insn >> 16) & 0x0f, 534 insn & 0x0f, (insn >> 5) & 0x07); 535 536/* if (((insn >> 5) & 0x07) != 0) 537 di->di_printf(", %d", (insn >> 5) & 0x07);*/ 538 break; 539 default: 540 di->di_printf("[%c - unknown]", *f_ptr); 541 break; 542 } 543 if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z') 544 ++f_ptr; 545 else if (*(++f_ptr)) { 546 ++fmt; 547 if (fmt == 1) 548 di->di_printf("\t"); 549 else 550 di->di_printf(", "); 551 } 552 }; 553 554 di->di_printf("\n"); 555 556 return(loc + INSN_SIZE); 557} 558 559 560static void 561disasm_register_shift(const disasm_interface_t *di, u_int insn) 562{ 563 di->di_printf("r%d", (insn & 0x0f)); 564 if ((insn & 0x00000ff0) == 0) 565 ; 566 else if ((insn & 0x00000ff0) == 0x00000060) 567 di->di_printf(", rrx"); 568 else { 569 if (insn & 0x10) 570 di->di_printf(", %s r%d", op2_shift(insn), 571 (insn >> 8) & 0x0f); 572 else 573 di->di_printf(", %s #%d", op2_shift(insn), 574 (insn >> 7) & 0x1f); 575 } 576} 577 578 579static void 580disasm_print_reglist(const disasm_interface_t *di, u_int insn) 581{ 582 int loop; 583 int start; 584 int comma; 585 586 di->di_printf("{"); 587 start = -1; 588 comma = 0; 589 590 for (loop = 0; loop < 17; ++loop) { 591 if (start != -1) { 592 if (loop == 16 || !(insn & (1 << loop))) { 593 if (comma) 594 di->di_printf(", "); 595 else 596 comma = 1; 597 if (start == loop - 1) 598 di->di_printf("r%d", start); 599 else 600 di->di_printf("r%d-r%d", start, loop - 1); 601 start = -1; 602 } 603 } else { 604 if (insn & (1 << loop)) 605 start = loop; 606 } 607 } 608 di->di_printf("}"); 609 610 if (insn & (1 << 22)) 611 di->di_printf("^"); 612} 613 614static void 615disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc) 616{ 617 int offset; 618 619 offset = insn & 0xfff; 620 if ((insn & 0x032f0000) == 0x010f0000) { 621 /* rA = pc, immediate index */ 622 if (insn & 0x00800000) 623 loc += offset; 624 else 625 loc -= offset; 626 di->di_printaddr(loc + 8); 627 } else { 628 di->di_printf("[r%d", (insn >> 16) & 0x0f); 629 if ((insn & 0x03000fff) != 0x01000000) { 630 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 631 if (!(insn & 0x00800000)) 632 di->di_printf("-"); 633 if (insn & (1 << 25)) 634 disasm_register_shift(di, insn); 635 else 636 di->di_printf("#0x%03x", offset); 637 } 638 if (insn & (1 << 24)) 639 di->di_printf("]"); 640 } 641} 642 643static void 644disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc) 645{ 646 int offset; 647 648 offset = ((insn & 0xf00) >> 4) | (insn & 0xf); 649 if ((insn & 0x004f0000) == 0x004f0000) { 650 /* rA = pc, immediate index */ 651 if (insn & 0x00800000) 652 loc += offset; 653 else 654 loc -= offset; 655 di->di_printaddr(loc + 8); 656 } else { 657 di->di_printf("[r%d", (insn >> 16) & 0x0f); 658 if ((insn & 0x01400f0f) != 0x01400000) { 659 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 660 if (!(insn & 0x00800000)) 661 di->di_printf("-"); 662 if (insn & (1 << 22)) 663 di->di_printf("#0x%02x", offset); 664 else 665 di->di_printf("r%d", (insn & 0x0f)); 666 } 667 if (insn & (1 << 24)) 668 di->di_printf("]"); 669 } 670} 671 672static void 673disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc) 674{ 675 if (((insn >> 8) & 0xf) == 1) 676 di->di_printf("f%d, ", (insn >> 12) & 0x07); 677 else 678 di->di_printf("c%d, ", (insn >> 12) & 0x0f); 679 680 di->di_printf("[r%d", (insn >> 16) & 0x0f); 681 682 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 683 684 if (!(insn & (1 << 23))) 685 di->di_printf("-"); 686 687 di->di_printf("#0x%03x", (insn & 0xff) << 2); 688 689 if (insn & (1 << 24)) 690 di->di_printf("]"); 691 692 if (insn & (1 << 21)) 693 di->di_printf("!"); 694} 695 696static u_int 697disassemble_readword(u_int address) 698{ 699 return(*((u_int *)address)); 700} 701 702static void 703disassemble_printaddr(u_int address) 704{ 705 printf("0x%08x", address); 706} 707 708static const disasm_interface_t disassemble_di = { 709 disassemble_readword, disassemble_printaddr, printf 710}; 711 712void 713disassemble(u_int address) 714{ 715 716 (void)disasm(&disassemble_di, address, 0); 717} 718 719/* End of disassem.c */ 720