disassem.c revision 96dbb4fc58fe2dcf4390e073dbb42cc77ef2f0b5
1/*	$NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $	*/
2
3/*-
4 * Copyright (c) 1996 Mark Brinicombe.
5 * Copyright (c) 1996 Brini.
6 *
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *	This product includes software developed by Brini.
20 * 4. The name of the company nor the name of the author may be used to
21 *    endorse or promote products derived from this software without specific
22 *    prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * RiscBSD kernel project
37 *
38 * db_disasm.c
39 *
40 * Kernel disassembler
41 *
42 * Created      : 10/02/96
43 *
44 * Structured after the sparc/sparc/db_disasm.c by David S. Miller &
45 * Paul Kranenburg
46 *
47 * This code is not complete. Not all instructions are disassembled.
48 */
49
50#include <sys/cdefs.h>
51//__FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/arm/arm/disassem.c,v 1.2 2005/01/05 21:58:47 imp Exp $");
52#include <sys/param.h>
53#include <stdio.h>
54
55#include "disassem.h"
56#include "armreg.h"
57//#include <ddb/ddb.h>
58
59/*
60 * General instruction format
61 *
62 *	insn[cc][mod]	[operands]
63 *
64 * Those fields with an uppercase format code indicate that the field
65 * follows directly after the instruction before the separator i.e.
66 * they modify the instruction rather than just being an operand to
67 * the instruction. The only exception is the writeback flag which
68 * follows a operand.
69 *
70 *
71 * 2 - print Operand 2 of a data processing instruction
72 * d - destination register (bits 12-15)
73 * n - n register (bits 16-19)
74 * s - s register (bits 8-11)
75 * o - indirect register rn (bits 16-19) (used by swap)
76 * m - m register (bits 0-3)
77 * a - address operand of ldr/str instruction
78 * e - address operand of ldrh/strh instruction
79 * l - register list for ldm/stm instruction
80 * f - 1st fp operand (register) (bits 12-14)
81 * g - 2nd fp operand (register) (bits 16-18)
82 * h - 3rd fp operand (register/immediate) (bits 0-4)
83 * j - xtb rotate literal (bits 10-11)
84 * b - branch address
85 * t - thumb branch address (bits 24, 0-23)
86 * k - breakpoint comment (bits 0-3, 8-19)
87 * X - block transfer type
88 * Y - block transfer type (r13 base)
89 * c - comment field bits(0-23)
90 * p - saved or current status register
91 * F - PSR transfer fields
92 * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN
93 * L - co-processor transfer size
94 * S - set status flag
95 * P - fp precision
96 * Q - fp precision (for ldf/stf)
97 * R - fp rounding
98 * v - co-processor data transfer registers + addressing mode
99 * W - writeback flag
100 * x - instruction in hex
101 * # - co-processor number
102 * y - co-processor data processing registers
103 * z - co-processor register transfer registers
104 */
105
106struct arm32_insn {
107	u_int mask;
108	u_int pattern;
109	char* name;
110	char* format;
111};
112
113static const struct arm32_insn arm32_i[] = {
114    { 0x0fffffff, 0x0ff00000, "imb",	"c" },		/* Before swi */
115    { 0x0fffffff, 0x0ff00001, "imbrange",	"c" },	/* Before swi */
116    { 0x0f000000, 0x0f000000, "swi",	"c" },
117    { 0xfe000000, 0xfa000000, "blx",	"t" },		/* Before b and bl */
118    { 0x0f000000, 0x0a000000, "b",	"b" },
119    { 0x0f000000, 0x0b000000, "bl",	"b" },
120    { 0x0fe000f0, 0x00000090, "mul",	"Snms" },
121    { 0x0fe000f0, 0x00200090, "mla",	"Snmsd" },
122    { 0x0fe000f0, 0x00800090, "umull",	"Sdnms" },
123    { 0x0fe000f0, 0x00c00090, "smull",	"Sdnms" },
124    { 0x0fe000f0, 0x00a00090, "umlal",	"Sdnms" },
125    { 0x0fe000f0, 0x00e00090, "smlal",	"Sdnms" },
126    { 0x0fff03f0, 0x06cf0070, "uxtb16", "dmj" },
127    { 0x0d700000, 0x04200000, "strt",	"daW" },
128    { 0x0d700000, 0x04300000, "ldrt",	"daW" },
129    { 0x0d700000, 0x04600000, "strbt",	"daW" },
130    { 0x0d700000, 0x04700000, "ldrbt",	"daW" },
131    { 0x0c500000, 0x04000000, "str",	"daW" },
132    { 0x0c500000, 0x04100000, "ldr",	"daW" },
133    { 0x0c500000, 0x04400000, "strb",	"daW" },
134    { 0x0c500000, 0x04500000, "ldrb",	"daW" },
135    { 0x0e1f0000, 0x080d0000, "stm",	"YnWl" },/* separate out r13 base */
136    { 0x0e1f0000, 0x081d0000, "ldm",	"YnWl" },/* separate out r13 base */
137    { 0x0e100000, 0x08000000, "stm",	"XnWl" },
138    { 0x0e100000, 0x08100000, "ldm",	"XnWl" },
139    { 0x0e1000f0, 0x00100090, "ldrb",	"deW" },
140    { 0x0e1000f0, 0x00000090, "strb",	"deW" },
141    { 0x0e1000f0, 0x001000d0, "ldrsb",	"deW" },
142    { 0x0e1000f0, 0x001000b0, "ldrh",	"deW" },
143    { 0x0e1000f0, 0x000000b0, "strh",	"deW" },
144    { 0x0e1000f0, 0x001000f0, "ldrsh",	"deW" },
145    { 0x0f200090, 0x00200090, "und",	"x" },	/* Before data processing */
146    { 0x0e1000d0, 0x000000d0, "und",	"x" },	/* Before data processing */
147    { 0x0ff00ff0, 0x01000090, "swp",	"dmo" },
148    { 0x0ff00ff0, 0x01400090, "swpb",	"dmo" },
149    { 0x0fbf0fff, 0x010f0000, "mrs",	"dp" },	/* Before data processing */
150    { 0x0fb0fff0, 0x0120f000, "msr",	"pFm" },/* Before data processing */
151    { 0x0fb0f000, 0x0320f000, "msr",	"pF2" },/* Before data processing */
152    { 0x0ffffff0, 0x012fff10, "bx",     "m" },
153    { 0x0fff0ff0, 0x016f0f10, "clz",	"dm" },
154    { 0x0ffffff0, 0x012fff30, "blx",	"m" },
155    { 0xfff000f0, 0xe1200070, "bkpt",	"k" },
156    { 0x0de00000, 0x00000000, "and",	"Sdn2" },
157    { 0x0de00000, 0x00200000, "eor",	"Sdn2" },
158    { 0x0de00000, 0x00400000, "sub",	"Sdn2" },
159    { 0x0de00000, 0x00600000, "rsb",	"Sdn2" },
160    { 0x0de00000, 0x00800000, "add",	"Sdn2" },
161    { 0x0de00000, 0x00a00000, "adc",	"Sdn2" },
162    { 0x0de00000, 0x00c00000, "sbc",	"Sdn2" },
163    { 0x0de00000, 0x00e00000, "rsc",	"Sdn2" },
164    { 0x0df00000, 0x01100000, "tst",	"Dn2" },
165    { 0x0df00000, 0x01300000, "teq",	"Dn2" },
166    { 0x0df00000, 0x01500000, "cmp",	"Dn2" },
167    { 0x0df00000, 0x01700000, "cmn",	"Dn2" },
168    { 0x0de00000, 0x01800000, "orr",	"Sdn2" },
169    { 0x0de00000, 0x01a00000, "mov",	"Sd2" },
170    { 0x0de00000, 0x01c00000, "bic",	"Sdn2" },
171    { 0x0de00000, 0x01e00000, "mvn",	"Sd2" },
172    { 0x0ff08f10, 0x0e000100, "adf",	"PRfgh" },
173    { 0x0ff08f10, 0x0e100100, "muf",	"PRfgh" },
174    { 0x0ff08f10, 0x0e200100, "suf",	"PRfgh" },
175    { 0x0ff08f10, 0x0e300100, "rsf",	"PRfgh" },
176    { 0x0ff08f10, 0x0e400100, "dvf",	"PRfgh" },
177    { 0x0ff08f10, 0x0e500100, "rdf",	"PRfgh" },
178    { 0x0ff08f10, 0x0e600100, "pow",	"PRfgh" },
179    { 0x0ff08f10, 0x0e700100, "rpw",	"PRfgh" },
180    { 0x0ff08f10, 0x0e800100, "rmf",	"PRfgh" },
181    { 0x0ff08f10, 0x0e900100, "fml",	"PRfgh" },
182    { 0x0ff08f10, 0x0ea00100, "fdv",	"PRfgh" },
183    { 0x0ff08f10, 0x0eb00100, "frd",	"PRfgh" },
184    { 0x0ff08f10, 0x0ec00100, "pol",	"PRfgh" },
185    { 0x0f008f10, 0x0e000100, "fpbop",	"PRfgh" },
186    { 0x0ff08f10, 0x0e008100, "mvf",	"PRfh" },
187    { 0x0ff08f10, 0x0e108100, "mnf",	"PRfh" },
188    { 0x0ff08f10, 0x0e208100, "abs",	"PRfh" },
189    { 0x0ff08f10, 0x0e308100, "rnd",	"PRfh" },
190    { 0x0ff08f10, 0x0e408100, "sqt",	"PRfh" },
191    { 0x0ff08f10, 0x0e508100, "log",	"PRfh" },
192    { 0x0ff08f10, 0x0e608100, "lgn",	"PRfh" },
193    { 0x0ff08f10, 0x0e708100, "exp",	"PRfh" },
194    { 0x0ff08f10, 0x0e808100, "sin",	"PRfh" },
195    { 0x0ff08f10, 0x0e908100, "cos",	"PRfh" },
196    { 0x0ff08f10, 0x0ea08100, "tan",	"PRfh" },
197    { 0x0ff08f10, 0x0eb08100, "asn",	"PRfh" },
198    { 0x0ff08f10, 0x0ec08100, "acs",	"PRfh" },
199    { 0x0ff08f10, 0x0ed08100, "atn",	"PRfh" },
200    { 0x0f008f10, 0x0e008100, "fpuop",	"PRfh" },
201    { 0x0e100f00, 0x0c000100, "stf",	"QLv" },
202    { 0x0e100f00, 0x0c100100, "ldf",	"QLv" },
203    { 0x0ff00f10, 0x0e000110, "flt",	"PRgd" },
204    { 0x0ff00f10, 0x0e100110, "fix",	"PRdh" },
205    { 0x0ff00f10, 0x0e200110, "wfs",	"d" },
206    { 0x0ff00f10, 0x0e300110, "rfs",	"d" },
207    { 0x0ff00f10, 0x0e400110, "wfc",	"d" },
208    { 0x0ff00f10, 0x0e500110, "rfc",	"d" },
209    { 0x0ff0ff10, 0x0e90f110, "cmf",	"PRgh" },
210    { 0x0ff0ff10, 0x0eb0f110, "cnf",	"PRgh" },
211    { 0x0ff0ff10, 0x0ed0f110, "cmfe",	"PRgh" },
212    { 0x0ff0ff10, 0x0ef0f110, "cnfe",	"PRgh" },
213    { 0xff100010, 0xfe000010, "mcr2",	"#z" },
214    { 0x0f100010, 0x0e000010, "mcr",	"#z" },
215    { 0xff100010, 0xfe100010, "mrc2",	"#z" },
216    { 0x0f100010, 0x0e100010, "mrc",	"#z" },
217    { 0xff000010, 0xfe000000, "cdp2",	"#y" },
218    { 0x0f000010, 0x0e000000, "cdp",	"#y" },
219    { 0xfe100090, 0xfc100000, "ldc2",	"L#v" },
220    { 0x0e100090, 0x0c100000, "ldc",	"L#v" },
221    { 0xfe100090, 0xfc000000, "stc2",	"L#v" },
222    { 0x0e100090, 0x0c000000, "stc",	"L#v" },
223    { 0xf550f000, 0xf550f000, "pld",	"ne" },
224    { 0x0ff00ff0, 0x01000050, "qaad",	"dmn" },
225    { 0x0ff00ff0, 0x01400050, "qdaad",	"dmn" },
226    { 0x0ff00ff0, 0x01600050, "qdsub",	"dmn" },
227    { 0x0ff00ff0, 0x01200050, "dsub",	"dmn" },
228    { 0x0ff000f0, 0x01000080, "smlabb",	"nmsd" },   // d & n inverted!!
229    { 0x0ff000f0, 0x010000a0, "smlatb",	"nmsd" },   // d & n inverted!!
230    { 0x0ff000f0, 0x010000c0, "smlabt",	"nmsd" },   // d & n inverted!!
231    { 0x0ff000f0, 0x010000e0, "smlatt",	"nmsd" },   // d & n inverted!!
232    { 0x0ff000f0, 0x01400080, "smlalbb","ndms" },   // d & n inverted!!
233    { 0x0ff000f0, 0x014000a0, "smlaltb","ndms" },   // d & n inverted!!
234    { 0x0ff000f0, 0x014000c0, "smlalbt","ndms" },   // d & n inverted!!
235    { 0x0ff000f0, 0x014000e0, "smlaltt","ndms" },   // d & n inverted!!
236    { 0x0ff000f0, 0x01200080, "smlawb", "nmsd" },   // d & n inverted!!
237    { 0x0ff0f0f0, 0x012000a0, "smulwb","nms" },   // d & n inverted!!
238    { 0x0ff000f0, 0x012000c0, "smlawt", "nmsd" },   // d & n inverted!!
239    { 0x0ff0f0f0, 0x012000e0, "smulwt","nms" },   // d & n inverted!!
240    { 0x0ff0f0f0, 0x01600080, "smulbb","nms" },   // d & n inverted!!
241    { 0x0ff0f0f0, 0x016000a0, "smultb","nms" },   // d & n inverted!!
242    { 0x0ff0f0f0, 0x016000c0, "smulbt","nms" },   // d & n inverted!!
243    { 0x0ff0f0f0, 0x016000e0, "smultt","nms" },   // d & n inverted!!
244    { 0x00000000, 0x00000000, NULL,	NULL }
245};
246
247static char const arm32_insn_conditions[][4] = {
248	"eq", "ne", "cs", "cc",
249	"mi", "pl", "vs", "vc",
250	"hi", "ls", "ge", "lt",
251	"gt", "le", "",   "nv"
252};
253
254static char const insn_block_transfers[][4] = {
255	"da", "ia", "db", "ib"
256};
257
258static char const insn_stack_block_transfers[][4] = {
259	"ed", "ea", "fd", "fa"
260};
261
262static char const op_shifts[][4] = {
263	"lsl", "lsr", "asr", "ror"
264};
265
266static char const insn_fpa_rounding[][2] = {
267	"", "p", "m", "z"
268};
269
270static char const insn_fpa_precision[][2] = {
271	"s", "d", "e", "p"
272};
273
274static char const insn_fpaconstants[][8] = {
275	"0.0", "1.0", "2.0", "3.0",
276	"4.0", "5.0", "0.5", "10.0"
277};
278
279#define insn_condition(x)	arm32_insn_conditions[(x >> 28) & 0x0f]
280#define insn_blktrans(x)	insn_block_transfers[(x >> 23) & 3]
281#define insn_stkblktrans(x)	insn_stack_block_transfers[(x >> 23) & 3]
282#define op2_shift(x)		op_shifts[(x >> 5) & 3]
283#define insn_fparnd(x)		insn_fpa_rounding[(x >> 5) & 0x03]
284#define insn_fpaprec(x)		insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1]
285#define insn_fpaprect(x)	insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1]
286#define insn_fpaimm(x)		insn_fpaconstants[x & 0x07]
287
288/* Local prototypes */
289static void disasm_register_shift(const disasm_interface_t *di, u_int insn);
290static void disasm_print_reglist(const disasm_interface_t *di, u_int insn);
291static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn,
292    u_int loc);
293static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn,
294    u_int loc);
295static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn,
296    u_int loc);
297static u_int disassemble_readword(u_int address);
298static void disassemble_printaddr(u_int address);
299
300u_int
301disasm(const disasm_interface_t *di, u_int loc, int altfmt)
302{
303	const struct arm32_insn *i_ptr = &arm32_i[0];
304
305	u_int insn;
306	int matchp;
307	int branch;
308	char* f_ptr;
309	int fmt;
310
311	fmt = 0;
312	matchp = 0;
313	insn = di->di_readword(loc);
314
315/*	di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/
316
317	while (i_ptr->name) {
318		if ((insn & i_ptr->mask) ==  i_ptr->pattern) {
319			matchp = 1;
320			break;
321		}
322		i_ptr++;
323	}
324
325	if (!matchp) {
326		di->di_printf("und%s\t%08x\n", insn_condition(insn), insn);
327		return(loc + INSN_SIZE);
328	}
329
330	/* If instruction forces condition code, don't print it. */
331	if ((i_ptr->mask & 0xf0000000) == 0xf0000000)
332		di->di_printf("%s", i_ptr->name);
333	else
334		di->di_printf("%s%s", i_ptr->name, insn_condition(insn));
335
336	f_ptr = i_ptr->format;
337
338	/* Insert tab if there are no instruction modifiers */
339
340	if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') {
341		++fmt;
342		di->di_printf("\t");
343	}
344
345	while (*f_ptr) {
346		switch (*f_ptr) {
347		/* 2 - print Operand 2 of a data processing instruction */
348		case '2':
349			if (insn & 0x02000000) {
350				int rotate= ((insn >> 7) & 0x1e);
351
352				di->di_printf("#0x%08x",
353					      (insn & 0xff) << (32 - rotate) |
354					      (insn & 0xff) >> rotate);
355			} else {
356				disasm_register_shift(di, insn);
357			}
358			break;
359		/* d - destination register (bits 12-15) */
360		case 'd':
361			di->di_printf("r%d", ((insn >> 12) & 0x0f));
362			break;
363		/* D - insert 'p' if Rd is R15 */
364		case 'D':
365			if (((insn >> 12) & 0x0f) == 15)
366				di->di_printf("p");
367			break;
368		/* n - n register (bits 16-19) */
369		case 'n':
370			di->di_printf("r%d", ((insn >> 16) & 0x0f));
371			break;
372		/* s - s register (bits 8-11) */
373		case 's':
374			di->di_printf("r%d", ((insn >> 8) & 0x0f));
375			break;
376		/* o - indirect register rn (bits 16-19) (used by swap) */
377		case 'o':
378			di->di_printf("[r%d]", ((insn >> 16) & 0x0f));
379			break;
380		/* m - m register (bits 0-4) */
381		case 'm':
382			di->di_printf("r%d", ((insn >> 0) & 0x0f));
383			break;
384		/* a - address operand of ldr/str instruction */
385		case 'a':
386			disasm_insn_ldrstr(di, insn, loc);
387			break;
388		/* e - address operand of ldrh/strh instruction */
389		case 'e':
390			disasm_insn_ldrhstrh(di, insn, loc);
391			break;
392		/* l - register list for ldm/stm instruction */
393		case 'l':
394			disasm_print_reglist(di, insn);
395			break;
396		/* f - 1st fp operand (register) (bits 12-14) */
397		case 'f':
398			di->di_printf("f%d", (insn >> 12) & 7);
399			break;
400		/* g - 2nd fp operand (register) (bits 16-18) */
401		case 'g':
402			di->di_printf("f%d", (insn >> 16) & 7);
403			break;
404		/* h - 3rd fp operand (register/immediate) (bits 0-4) */
405		case 'h':
406			if (insn & (1 << 3))
407				di->di_printf("#%s", insn_fpaimm(insn));
408			else
409				di->di_printf("f%d", insn & 7);
410			break;
411		/* j - xtb rotate literal (bits 10-11) */
412		case 'j':
413			di->di_printf("ror #%d", ((insn >> 10) & 3) << 3);
414			break;
415		/* b - branch address */
416		case 'b':
417			branch = ((insn << 2) & 0x03ffffff);
418			if (branch & 0x02000000)
419				branch |= 0xfc000000;
420			di->di_printaddr(loc + 8 + branch);
421			break;
422		/* t - blx address */
423		case 't':
424			branch = ((insn << 2) & 0x03ffffff) |
425			    (insn >> 23 & 0x00000002);
426			if (branch & 0x02000000)
427				branch |= 0xfc000000;
428			di->di_printaddr(loc + 8 + branch);
429			break;
430		/* X - block transfer type */
431		case 'X':
432			di->di_printf("%s", insn_blktrans(insn));
433			break;
434		/* Y - block transfer type (r13 base) */
435		case 'Y':
436			di->di_printf("%s", insn_stkblktrans(insn));
437			break;
438		/* c - comment field bits(0-23) */
439		case 'c':
440			di->di_printf("0x%08x", (insn & 0x00ffffff));
441			break;
442		/* k - breakpoint comment (bits 0-3, 8-19) */
443		case 'k':
444			di->di_printf("0x%04x",
445			    (insn & 0x000fff00) >> 4 | (insn & 0x0000000f));
446			break;
447		/* p - saved or current status register */
448		case 'p':
449			if (insn & 0x00400000)
450				di->di_printf("spsr");
451			else
452				di->di_printf("cpsr");
453			break;
454		/* F - PSR transfer fields */
455		case 'F':
456			di->di_printf("_");
457			if (insn & (1 << 16))
458				di->di_printf("c");
459			if (insn & (1 << 17))
460				di->di_printf("x");
461			if (insn & (1 << 18))
462				di->di_printf("s");
463			if (insn & (1 << 19))
464				di->di_printf("f");
465			break;
466		/* B - byte transfer flag */
467		case 'B':
468			if (insn & 0x00400000)
469				di->di_printf("b");
470			break;
471		/* L - co-processor transfer size */
472		case 'L':
473			if (insn & (1 << 22))
474				di->di_printf("l");
475			break;
476		/* S - set status flag */
477		case 'S':
478			if (insn & 0x00100000)
479				di->di_printf("s");
480			break;
481		/* P - fp precision */
482		case 'P':
483			di->di_printf("%s", insn_fpaprec(insn));
484			break;
485		/* Q - fp precision (for ldf/stf) */
486		case 'Q':
487			break;
488		/* R - fp rounding */
489		case 'R':
490			di->di_printf("%s", insn_fparnd(insn));
491			break;
492		/* W - writeback flag */
493		case 'W':
494			if (insn & (1 << 21))
495				di->di_printf("!");
496			break;
497		/* # - co-processor number */
498		case '#':
499			di->di_printf("p%d", (insn >> 8) & 0x0f);
500			break;
501		/* v - co-processor data transfer registers+addressing mode */
502		case 'v':
503			disasm_insn_ldcstc(di, insn, loc);
504			break;
505		/* x - instruction in hex */
506		case 'x':
507			di->di_printf("0x%08x", insn);
508			break;
509		/* y - co-processor data processing registers */
510		case 'y':
511			di->di_printf("%d, ", (insn >> 20) & 0x0f);
512
513			di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f,
514			    (insn >> 16) & 0x0f, insn & 0x0f);
515
516			di->di_printf(", %d", (insn >> 5) & 0x07);
517			break;
518		/* z - co-processor register transfer registers */
519		case 'z':
520			di->di_printf("%d, ", (insn >> 21) & 0x07);
521			di->di_printf("r%d, c%d, c%d, %d",
522			    (insn >> 12) & 0x0f, (insn >> 16) & 0x0f,
523			    insn & 0x0f, (insn >> 5) & 0x07);
524
525/*			if (((insn >> 5) & 0x07) != 0)
526				di->di_printf(", %d", (insn >> 5) & 0x07);*/
527			break;
528		default:
529			di->di_printf("[%c - unknown]", *f_ptr);
530			break;
531		}
532		if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z')
533			++f_ptr;
534		else if (*(++f_ptr)) {
535			++fmt;
536			if (fmt == 1)
537				di->di_printf("\t");
538			else
539				di->di_printf(", ");
540		}
541	};
542
543	di->di_printf("\n");
544
545	return(loc + INSN_SIZE);
546}
547
548
549static void
550disasm_register_shift(const disasm_interface_t *di, u_int insn)
551{
552	di->di_printf("r%d", (insn & 0x0f));
553	if ((insn & 0x00000ff0) == 0)
554		;
555	else if ((insn & 0x00000ff0) == 0x00000060)
556		di->di_printf(", rrx");
557	else {
558		if (insn & 0x10)
559			di->di_printf(", %s r%d", op2_shift(insn),
560			    (insn >> 8) & 0x0f);
561		else
562			di->di_printf(", %s #%d", op2_shift(insn),
563			    (insn >> 7) & 0x1f);
564	}
565}
566
567
568static void
569disasm_print_reglist(const disasm_interface_t *di, u_int insn)
570{
571	int loop;
572	int start;
573	int comma;
574
575	di->di_printf("{");
576	start = -1;
577	comma = 0;
578
579	for (loop = 0; loop < 17; ++loop) {
580		if (start != -1) {
581			if (loop == 16 || !(insn & (1 << loop))) {
582				if (comma)
583					di->di_printf(", ");
584				else
585					comma = 1;
586        			if (start == loop - 1)
587        				di->di_printf("r%d", start);
588        			else
589        				di->di_printf("r%d-r%d", start, loop - 1);
590        			start = -1;
591        		}
592        	} else {
593        		if (insn & (1 << loop))
594        			start = loop;
595        	}
596        }
597	di->di_printf("}");
598
599	if (insn & (1 << 22))
600		di->di_printf("^");
601}
602
603static void
604disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc)
605{
606	int offset;
607
608	offset = insn & 0xfff;
609	if ((insn & 0x032f0000) == 0x010f0000) {
610		/* rA = pc, immediate index */
611		if (insn & 0x00800000)
612			loc += offset;
613		else
614			loc -= offset;
615		di->di_printaddr(loc + 8);
616 	} else {
617		di->di_printf("[r%d", (insn >> 16) & 0x0f);
618		if ((insn & 0x03000fff) != 0x01000000) {
619			di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
620			if (!(insn & 0x00800000))
621				di->di_printf("-");
622			if (insn & (1 << 25))
623				disasm_register_shift(di, insn);
624			else
625				di->di_printf("#0x%03x", offset);
626		}
627		if (insn & (1 << 24))
628			di->di_printf("]");
629	}
630}
631
632static void
633disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc)
634{
635	int offset;
636
637	offset = ((insn & 0xf00) >> 4) | (insn & 0xf);
638	if ((insn & 0x004f0000) == 0x004f0000) {
639		/* rA = pc, immediate index */
640		if (insn & 0x00800000)
641			loc += offset;
642		else
643			loc -= offset;
644		di->di_printaddr(loc + 8);
645 	} else {
646		di->di_printf("[r%d", (insn >> 16) & 0x0f);
647		if ((insn & 0x01400f0f) != 0x01400000) {
648			di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
649			if (!(insn & 0x00800000))
650				di->di_printf("-");
651			if (insn & (1 << 22))
652				di->di_printf("#0x%02x", offset);
653			else
654				di->di_printf("r%d", (insn & 0x0f));
655		}
656		if (insn & (1 << 24))
657			di->di_printf("]");
658	}
659}
660
661static void
662disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc)
663{
664	if (((insn >> 8) & 0xf) == 1)
665		di->di_printf("f%d, ", (insn >> 12) & 0x07);
666	else
667		di->di_printf("c%d, ", (insn >> 12) & 0x0f);
668
669	di->di_printf("[r%d", (insn >> 16) & 0x0f);
670
671	di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
672
673	if (!(insn & (1 << 23)))
674		di->di_printf("-");
675
676	di->di_printf("#0x%03x", (insn & 0xff) << 2);
677
678	if (insn & (1 << 24))
679		di->di_printf("]");
680
681	if (insn & (1 << 21))
682		di->di_printf("!");
683}
684
685static u_int
686disassemble_readword(u_int address)
687{
688	return(*((u_int *)address));
689}
690
691static void
692disassemble_printaddr(u_int address)
693{
694	printf("0x%08x", address);
695}
696
697static const disasm_interface_t disassemble_di = {
698	disassemble_readword, disassemble_printaddr, printf
699};
700
701void
702disassemble(u_int address)
703{
704
705	(void)disasm(&disassemble_di, address, 0);
706}
707
708/* End of disassem.c */
709