Cross Reference: /external/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

Lines Matching refs:TRI
122   TRI(MF.getTarget().getRegisterInfo()),
128     BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
138           dbgs() << " " << TRI->getName(r));
148   State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
159       for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
172   for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
175     for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
203   for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
212               dbgs() << " " << TRI->getName(Reg) << "=g" <<
251       for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
313         dbgs() << header << TRI->getName(Reg); header = NULL; });
317   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
325           dbgs() << header << TRI->getName(Reg); header = NULL; });
326       DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
362     DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
375     for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
380               TRI->getName(AliasReg) << ")");
387       RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
406     for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
445     DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
461       RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
481         DEBUG(dbgs() << "=" << TRI->getName(Reg));
484         DEBUG(dbgs() << " " << TRI->getName(Reg));
494   BitVector BV(TRI->getNumRegs(), false);
511     BitVector RCBV = TRI->getAllocatableSet(MF, RC);
552     if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
557       DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
564               dbgs() << " " << TRI->getName(r));
573     bool IsSub = TRI->isSubRegister(SuperReg, Reg);
586     dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
600     TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
625     DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
637         unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
639           NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
642       DEBUG(dbgs() << " " << TRI->getName(NewReg));
660         for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
664             DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
745   for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
747       DEBUG(dbgs() << " " << TRI->getName(Reg));
801         DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
882                 << TRI->getName(AntiDepReg) << ":");
890             DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
891                   TRI->getName(NewReg) << "(" <<