Cross Reference: /external/llvm/lib/CodeGen/InlineSpiller.cpp

Lines Matching defs:Reg
117     SibValueInfo(unsigned Reg, VNInfo *VNI)
119         SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
157   bool isRegToSpill(unsigned Reg) {
159                      RegsToSpill.end(), Reg) != RegsToSpill.end();
162   bool isSibling(unsigned Reg);
174   bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
182   void spillAroundUses(unsigned Reg);
207 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
209 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
212   if (MI->getOperand(0).getReg() == Reg)
214   if (MI->getOperand(1).getReg() == Reg)
223   unsigned Reg = Edit->getReg();
226   // besides copies to/from Reg or spills/fills. We accept:
228   //   %snip = COPY %Reg / FILL fi#
230   //   %Reg = COPY %snip / SPILL %snip, fi#
242     // Allow copies to/from Reg.
243     if (isFullCopyOf(MI, Reg))
266   unsigned Reg = Edit->getReg();
269   RegsToSpill.assign(1, Reg);
274   if (Original == Reg)
277   for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
279     unsigned SnipReg = isFullCopyOf(MI, Reg);
307 bool InlineSpiller::isSibling(unsigned Reg) {
308   return TargetRegisterInfo::isVirtualRegister(Reg) &&
309            VRM.getOriginal(Reg) == Original;
488   // List of (Reg, VNI) that have been inserted into SibValues, but need to be
494     unsigned Reg;
496     tie(Reg, VNI) = WorkList.pop_back_val();
497     DEBUG(dbgs() << "  " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
526       LiveInterval &LI = LIS.getInterval(Reg);
549         SibValues.insert(std::make_pair(PHIs[i], SibValueInfo(Reg, PHIs[i])));
556           SibValues.insert(std::make_pair(NonPHI, SibValueInfo(Reg, NonPHI)));
562           WorkList.push_back(std::make_pair(Reg, NonPHI));
576     if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {
603     if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
637     unsigned Reg = RegsToSpill[i];
638     LiveInterval &LI = LIS.getInterval(Reg);
654           DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
657         DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'
747     unsigned Reg = LI->reg;
752     if (isRegToSpill(Reg))
760     for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);
769       if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
782       if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
922     unsigned Reg = RegsToSpill[i];
923     LiveInterval &LI = LIS.getInterval(Reg);
925          RI = MRI.use_nodbg_begin(Reg);
934     unsigned Reg = RegsToSpill[i];
935     LiveInterval &LI = LIS.getInterval(Reg);
942       MI->addRegisterDead(Reg, &TRI);
959     unsigned Reg = RegsToSpill[i-1];
960     if (!LIS.hasInterval(Reg)) {
964     LiveInterval &LI = LIS.getInterval(Reg);
967     Edit->eraseVirtReg(Reg);
979 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
987   if (InstrReg != Reg || FI != StackSlot)
1108 /// spillAroundUses - insert spill code around each use of Reg.
1109 void InlineSpiller::spillAroundUses(unsigned Reg) {
1110   DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
1111   LiveInterval &OldLI = LIS.getInterval(Reg);
1113   // Iterate over instructions using Reg.
1114   for (MachineRegisterInfo::reg_iterator RegI = MRI.reg_begin(Reg);
1140     if (coalesceStackAccess(MI, Reg))
1146       MIBundleOperands(MI).analyzeVirtReg(Reg, &Ops);
1156     unsigned SibReg = isFullCopyOf(MI, Reg);
1186     LiveInterval &NewLI = Edit->createFrom(Reg);