Lines Matching defs:SRL
882 else if (Opc == ISD::SRL)
1123 case ISD::SRL: return visitSRL(N);
1206 case ISD::SRL:
1901 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1904 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1905 AddToWorkList(SRL.getNode());
1955 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1969 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
2113 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2149 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2232 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2262 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2346 // For each of OP in SHL/SRL/SRA/AND...
2350 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2773 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2819 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2843 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2845 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2884 // Make sure everything beyond the low halfword is zero since the SRL 16
2894 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2907 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2930 if (N0.getOpcode() != ISD::SRL)
2952 } else { // Opc == ISD::SRL
3039 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
3209 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3534 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3653 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3667 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3768 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3801 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3826 // If the sign bit is known to be zero, switch this to a SRL.
3828 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3849 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3865 if (N1C && N0.getOpcode() == ISD::SRL &&
3871 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3877 N0.getOperand(0).getOpcode() == ISD::SRL &&
3890 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3912 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3914 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3926 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3947 // could be set on input to the CTLZ node. If this bit is set, the SRL
3948 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3949 // to an SRL/XOR pair, which is likely to simplify more.
3954 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3974 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
4014 // However when after the source operand of SRL is optimized into AND, the SRL
4797 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
5004 case ISD::SRL:
5017 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
5046 } else if (Opc == ISD::SRL) {
5047 // Another special-case: SRL is basically zero-extending a narrower value.
5066 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5080 // Because a SRL must be assumed to *need* to zero-extend the high bits
5082 // lowering of SRL and an sextload.
5236 if (N0.getOpcode() == ISD::SRL) {
5239 // We can turn this into an SRA iff the input to the SRL is already sign
5623 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
6719 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6722 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6745 // SRL constant is equal to the log2 of the AND constant. The back-end is
6775 // Replace the uses of SRL with SETCC
7493 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
9620 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
9741 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
9750 return DAG.getNode(ISD::SRL, DL, XType,
9757 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,