Cross Reference: /external/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

Lines Matching refs:Op0
402   unsigned Op0 = getRegForValue(I->getOperand(0));
403   if (Op0 == 0)   // Unhandled operand. Halt "fast" selection and bail.
427     unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
439                                      ISDOpcode, Op0, Op0IsKill, CF);
457                                    Op0, Op0IsKill,
777   unsigned Op0 = getRegForValue(I->getOperand(0));
778   if (Op0 == 0)
793               ResultReg).addReg(Op0);
799     ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
941   const Value *Op0 = EVI->getOperand(0);
942   Type *AggTy = Op0->getType();
946   DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
949   else if (isa<Instruction>(Op0))
950     ResultReg = FuncInfo.InitializeRegForValue(Op0);
1110                               unsigned /*Op0*/, bool /*Op0IsKill*/) {
1116                                unsigned /*Op0*/, bool /*Op0IsKill*/,
1132                                unsigned /*Op0*/, bool /*Op0IsKill*/,
1139                                unsigned /*Op0*/, bool /*Op0IsKill*/,
1146                                 unsigned /*Op0*/, bool /*Op0IsKill*/,
1157                                 unsigned Op0, bool Op0IsKill,
1176   unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1188                      Op0, Op0IsKill,
1207                                   unsigned Op0, bool Op0IsKill) {
1213       .addReg(Op0, Op0IsKill * RegState::Kill);
1216       .addReg(Op0, Op0IsKill * RegState::Kill);
1226                                    unsigned Op0, bool Op0IsKill,
1233       .addReg(Op0, Op0IsKill * RegState::Kill)
1237       .addReg(Op0, Op0IsKill * RegState::Kill)
1247                                    unsigned Op0, bool Op0IsKill,
1255       .addReg(Op0, Op0IsKill * RegState::Kill)
1260       .addReg(Op0, Op0IsKill * RegState::Kill)
1271                                    unsigned Op0, bool Op0IsKill,
1278       .addReg(Op0, Op0IsKill * RegState::Kill)
1282       .addReg(Op0, Op0IsKill * RegState::Kill)
1292                                    unsigned Op0, bool Op0IsKill,
1299       .addReg(Op0, Op0IsKill * RegState::Kill)
1304       .addReg(Op0, Op0IsKill * RegState::Kill)
1315                                    unsigned Op0, bool Op0IsKill,
1322       .addReg(Op0, Op0IsKill * RegState::Kill)
1326       .addReg(Op0, Op0IsKill * RegState::Kill)
1336                                     unsigned Op0, bool Op0IsKill,
1344       .addReg(Op0, Op0IsKill * RegState::Kill)
1349       .addReg(Op0, Op0IsKill * RegState::Kill)
1360                                      unsigned Op0, bool Op0IsKill,
1368       .addReg(Op0, Op0IsKill * RegState::Kill)
1373       .addReg(Op0, Op0IsKill * RegState::Kill)
1416                                               unsigned Op0, bool Op0IsKill,
1419   assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1421   const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1422   MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1425     .addReg(Op0, getKillRegState(Op0IsKill), Idx);
1431 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1432   return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);