Cross Reference: /external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Lines Matching refs:MCID
1002     const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1003     for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
1004       if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
1009     if (MCID.isCommutable())
1192   const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1193   assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
1194   unsigned NumRes = MCID.getNumDefs();
1195   for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
1318     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
1319     if (!MCID.ImplicitDefs)
1321     for (const uint16_t *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
2690     const MCInstrDesc &MCID = TII->get(Opc);
2691     unsigned NumRes = MCID.getNumDefs();
2692     unsigned NumOps = MCID.getNumOperands() - NumRes;
2694       if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) {
2917     const MCInstrDesc &MCID = TII->get(Opc);
2918     unsigned NumRes = MCID.getNumDefs();
2919     unsigned NumOps = MCID.getNumOperands() - NumRes;
2921       if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1)