Lines Matching refs:Cond

1068                               ISD::CondCode Cond, bool foldBooleans,
1073 switch (Cond) {
1084 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1097 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1099 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1102 Cond = ISD::SETNE;
1106 Cond = ISD::SETEQ;
1110 Zero, Cond);
1127 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1131 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1140 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1169 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1227 DAG.getConstant(0LL, newVT), Cond);
1240 switch (Cond) {
1261 switch (Cond) {
1271 getCondCodeAction(Cond, newVT.getSimpleVT())==Legal))
1274 Cond);
1281 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1290 return DAG.getConstant(Cond == ISD::SETNE, VT);
1309 Cond);
1311 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1315 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1351 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1364 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1366 Cond);
1383 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1389 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1395 if (ISD::isSignedIntSetCC(Cond)) {
1404 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1409 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1412 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1417 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1420 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1422 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1424 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1426 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1430 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1433 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1437 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1442 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1451 if (Cond == ISD::SETUGT &&
1458 if (Cond == ISD::SETULT &&
1467 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1475 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1482 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1496 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1509 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1512 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1513 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1514 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1521 ISD::CondCode NewCond = Cond;
1525 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1545 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1552 switch (ISD::getUnorderedFlavor(Cond)) {
1567 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1568 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1572 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1578 if (Cond == ISD::SETOEQ &&
1581 if (Cond == ISD::SETUEQ &&
1584 if (Cond == ISD::SETUNE &&
1587 if (Cond == ISD::SETONE &&
1591 if (Cond == ISD::SETOEQ &&
1594 if (Cond == ISD::SETUEQ &&
1597 if (Cond == ISD::SETUNE &&
1600 if (Cond == ISD::SETONE &&
1615 EqVal = ISD::isTrueWhenEqual(Cond);
1618 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1626 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1629 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1634 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1639 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1646 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1648 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1653 Cond);
1656 Cond);
1671 N0.getValueType()), Cond);
1684 Cond);
1695 Cond);
1711 DAG.getConstant(0, N0.getValueType()), Cond);
1715 DAG.getConstant(0, N0.getValueType()), Cond);
1723 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1734 DAG.getConstant(0, N1.getValueType()), Cond);
1738 DAG.getConstant(0, N1.getValueType()), Cond);
1746 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1758 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1760 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1766 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1768 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1776 switch (Cond) {