Lines Matching refs:Op0
1356 SDValue Op0 = N0;
1357 if (Op0.getOpcode() == ISD::TRUNCATE)
1358 Op0 = Op0.getOperand(0);
1360 if ((Op0.getOpcode() == ISD::XOR) &&
1361 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1362 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1365 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1368 if (Op0.getOpcode() == ISD::AND &&
1369 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1370 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1372 if (Op0.getValueType().bitsGT(VT))
1373 Op0 = DAG.getNode(ISD::AND, dl, VT,
1374 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1376 else if (Op0.getValueType().bitsLT(VT))
1377 Op0 = DAG.getNode(ISD::AND, dl, VT,
1378 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1381 return DAG.getSetCC(dl, VT, Op0,
1382 DAG.getConstant(0, Op0.getValueType()),
1385 if (Op0.getOpcode() == ISD::AssertZext &&
1386 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1387 return DAG.getSetCC(dl, VT, Op0,
1388 DAG.getConstant(0, Op0.getValueType()),