Lines Matching refs:VA

912     CCValAssign &VA = ArgLocs[i];
923 VA.getLocMemOffset(),
929 } else if (VA.isRegLoc()) {
930 MVT RegVT = VA.getLocVT();
932 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
935 } else { // VA.isRegLoc()
936 assert(VA.isMemLoc());
938 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
939 VA.getLocMemOffset(), true);
942 ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
949 switch (VA.getLocInfo()) {
953 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue);
958 unsigned DestSize = VA.getValVT().getSizeInBits();
970 VA.getValVT(), ArgValue,
1038 CCValAssign &VA = RVLocs[i];
1039 assert(VA.isRegLoc() && "Only register-returns should be created by PCS");
1049 switch (VA.getLocInfo()) {
1057 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1060 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1064 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1066 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1158 CCValAssign &VA = ArgLocs[i];
1166 switch (VA.getLocInfo()) {
1172 unsigned SrcSize = VA.getValVT().getSizeInBits();
1184 VA.getLocVT(),
1185 DAG.getUNDEF(VA.getLocVT()),
1193 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1197 if (VA.isRegLoc()) {
1201 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1205 assert(VA.isMemLoc() && "unexpected argument location");
1211 VA.getLocVT().getSizeInBits();
1213 int32_t Offset = VA.getLocMemOffset() + FPDiff;
1223 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
1226 DstInfo = MachinePointerInfo::getStack(VA.getLocMemOffset());
1355 CCValAssign VA = RVLocs[i];
1359 assert(VA.isRegLoc() && "Memory locations not expected for call return");
1361 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1366 switch (VA.getLocInfo()) {
1370 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1377 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);