Lines Matching refs:Cond
140 /// setting TBB to the destination basic block and populating the Cond vector
145 SmallVectorImpl<MachineOperand> &Cond) {
154 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
155 Cond.push_back(I->getOperand(0));
163 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
164 Cond.push_back(I->getOperand(0));
165 Cond.push_back(I->getOperand(1));
177 SmallVectorImpl<MachineOperand> &Cond,
203 classifyCondBranch(LastInst, TBB, Cond);
239 Cond.push_back(MachineOperand::CreateImm(AArch64::Bcc));
240 Cond.push_back(SecondLastInst->getOperand(0));
244 classifyCondBranch(SecondLastInst, TBB, Cond);
265 SmallVectorImpl<MachineOperand> &Cond) const {
266 switch (Cond[0].getImm()) {
268 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(Cond[1].getImm());
270 Cond[1].setImm(CC);
274 Cond[0].setImm(AArch64::CBNZw);
277 Cond[0].setImm(AArch64::CBNZx);
280 Cond[0].setImm(AArch64::CBZw);
283 Cond[0].setImm(AArch64::CBZx);
286 Cond[0].setImm(AArch64::TBNZwii);
289 Cond[0].setImm(AArch64::TBNZxii);
292 Cond[0].setImm(AArch64::TBZwii);
295 Cond[0].setImm(AArch64::TBZxii);
306 const SmallVectorImpl<MachineOperand> &Cond,
308 if (FBB == 0 && Cond.empty()) {
312 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
313 for (int i = 1, e = Cond.size(); i != e; ++i)
314 MIB.addOperand(Cond[i]);
319 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
320 for (int i = 1, e = Cond.size(); i != e; ++i)
321 MIB.addOperand(Cond[i]);