Lines Matching refs:DL
72 DebugLoc DL,
78 DebugLoc DL,
84 DebugLoc DL,
89 DebugLoc DL,
94 DebugLoc DL, unsigned DReg, unsigned Lane,
99 DebugLoc DL);
433 DebugLoc DL,
439 DL,
452 DebugLoc DL,
458 DL,
469 DebugLoc DL,
474 DL,
488 DebugLoc DL,
493 DL,
504 DebugLoc DL, unsigned DReg, unsigned Lane,
509 DL,
521 DebugLoc DL) {
525 DL,
536 DebugLoc DL = MI->getDebugLoc();
542 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
544 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
547 unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
548 unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
549 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
551 unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
552 unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
553 Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
555 Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
558 unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
559 unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
560 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
576 Out = createImplicitDef(MBB, InsertPt, DL);
577 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
578 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);