Cross Reference: /external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines Matching refs:MIB
681     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
682     MIB.addReg(SrcReg, getKillRegState(KillSrc));
684       MIB.addReg(SrcReg, getKillRegState(KillSrc));
685     AddDefaultPred(MIB);
751 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
755     return MIB.addReg(Reg, State);
758     return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
759   return MIB.addReg(Reg, State, SubIdx);
798         MachineInstrBuilder MIB =
802           MIB = AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
803                 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
833           MachineInstrBuilder MIB =
837           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
838           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
839           AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
854           MachineInstrBuilder MIB =
858           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
859           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
860           MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
861                 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
868         MachineInstrBuilder MIB =
872         MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
873         MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
874         MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
875         MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
876         MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
877         MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
878         MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
879               AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
979       MachineInstrBuilder MIB =
982       MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
983       MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
985         MIB.addReg(DestReg, RegState::ImplicitDefine);
1010         MachineInstrBuilder MIB =
1014         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1015         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1016         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1018           MIB.addReg(DestReg, RegState::ImplicitDefine);
1030         MachineInstrBuilder MIB =
1034         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1035         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1036         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1037         MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1039           MIB.addReg(DestReg, RegState::ImplicitDefine);
1046       MachineInstrBuilder MIB =
1050       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1051       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1052       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1053       MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1054       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1055       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1056       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1057       MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1059         MIB.addReg(DestReg, RegState::ImplicitDefine);
1158   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1170   AddDefaultPred(MIB);
1177   MIB.addReg(SrcRegS, RegState::Implicit);
1195   MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1197   return &*MIB;
1263     MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1266     MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
3824   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
3846       AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3868       AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3874       MIB.addReg(SrcReg, RegState::Implicit);
3897       MIB.addReg(DReg, RegState::Define)
3901       AddDefaultPred(MIB);
3905       MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
3907         MIB.addReg(ImplicitSReg, RegState::Implicit);
3933         MIB.addReg(DDst, RegState::Define)
3936         AddDefaultPred(MIB);
3940         MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
3941         MIB.addReg(SrcReg, RegState::Implicit);
3943           MIB.addReg(ImplicitSReg, RegState::Implicit);
3981       MIB.addReg(DDst, RegState::Define);
3987       MIB.addReg(CurReg, getUndefRegState(CurUndef));
3991       MIB.addReg(CurReg, getUndefRegState(CurUndef));
3993       MIB.addImm(1);
3994       AddDefaultPred(MIB);
3997         MIB.addReg(SrcReg, RegState::Implicit);
4001       MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4003         MIB.addReg(ImplicitSReg, RegState::Implicit);