Lines Matching refs:Op0
108 unsigned Op0, bool Op0IsKill);
111 unsigned Op0, bool Op0IsKill,
115 unsigned Op0, bool Op0IsKill,
120 unsigned Op0, bool Op0IsKill,
124 unsigned Op0, bool Op0IsKill,
128 unsigned Op0, bool Op0IsKill,
139 unsigned Op0, bool Op0IsKill,
304 unsigned Op0, bool Op0IsKill) {
310 .addReg(Op0, Op0IsKill * RegState::Kill));
313 .addReg(Op0, Op0IsKill * RegState::Kill));
323 unsigned Op0, bool Op0IsKill,
330 .addReg(Op0, Op0IsKill * RegState::Kill)
334 .addReg(Op0, Op0IsKill * RegState::Kill)
345 unsigned Op0, bool Op0IsKill,
353 .addReg(Op0, Op0IsKill * RegState::Kill)
358 .addReg(Op0, Op0IsKill * RegState::Kill)
370 unsigned Op0, bool Op0IsKill,
377 .addReg(Op0, Op0IsKill * RegState::Kill)
381 .addReg(Op0, Op0IsKill * RegState::Kill)
392 unsigned Op0, bool Op0IsKill,
399 .addReg(Op0, Op0IsKill * RegState::Kill)
403 .addReg(Op0, Op0IsKill * RegState::Kill)
414 unsigned Op0, bool Op0IsKill,
422 .addReg(Op0, Op0IsKill * RegState::Kill)
427 .addReg(Op0, Op0IsKill * RegState::Kill)
477 unsigned Op0, bool Op0IsKill,
480 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
485 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
1218 Value *Op0 = I->getOperand(0);
1231 SrcReg = getRegForValue(Op0);